Packaged Integrated Circuits Patents (Class 324/762.02)
  • Patent number: 11063598
    Abstract: A phase-locked loop (PLL) includes a voltage-controlled oscillator (VCO) that generates a PLL output signal having an oscillation frequency controlled by a control signal; a phase detector that generates a phase signal representing a difference in phase between the PLL output signal and a reference signal; a loop filter coupled to receive the phase signal; a switch; and a sampling circuit switchably coupled to receive the control signal of the VCO via the switch, and generating a code representing the control signal.
    Type: Grant
    Filed: October 16, 2020
    Date of Patent: July 13, 2021
    Assignee: Himax Imaging Limited
    Inventors: Xufeng Bao, Hack Soo Oh, Youngchul Sohn, Amit Mittra
  • Patent number: 11037843
    Abstract: Examples described herein include apparatuses and methods TSV resistance and short measurement in a stacked device. An example apparatus may include a chip comprising semiconductor substrate including a first surface and a second surface opposite to the first surface. The chip may include a first terminal formed above the first surface, a second terminal formed above the second surface, a buffer circuit coupled between the first and second terminals, a first through-substrate via (TSV) penetrating the semiconductor substrate, and a first switch coupled between the first terminal and the first TSV.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: June 15, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Naohisa Nishioka
  • Patent number: 11030366
    Abstract: A method includes: identifying ad hoc groups of elementary standard cells recurrent in a layout diagram; and selecting one group (selected group) of the recurrent ad hoc groups such that: the cells in the selected group have connections representing a corresponding logic circuit; each cell representing a logic gate; each ad hoc group has a number of transistors and a first number of logic gates; and the selected group providing a logical function. The method includes generating one or more macro standard cells such that: each macro standard cell has a number of transistors which is smaller than the number of transistors of a corresponding ad hoc group; or each macro standard cell has a second number of logic gates different than the first number of logic gates of the corresponding ad hoc group. The method also includes adding macro standard cells to the set of standard cells.
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: June 8, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Lin Liu, Sheng-Hsiung Chen, Jerry Chang-Jui Kao, Fong-Yuan Chang, Lee-Chung Lu, Shang-Chih Hsieh, Wei-Hsiang Ma
  • Patent number: 10990739
    Abstract: An integrated circuit device includes multiple circuit tiles disposed in a tiled arrangement in a circuit block between a first boundary and a second boundary. Each circuit tile is an instance of a circuit cell having a first edge and a second edge. The circuit cell has a scan channel circuit that includes a configurable scan channel switch and scan channels extending between the first edge and the second edge of the circuit cell through the configurable scan channel switch. Respective scan channels in the multiple circuit tiles are joined together and extend between the first boundary and the second boundary of the block of tiled arrangement. Each circuit tile can be configured to receive scan-in test data through a scan channel from either the first boundary or the second boundary, and to output scan-out result data of the circuit tile through a scan channel to either the first boundary or the second boundary.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: April 27, 2021
    Assignee: Amazon Technologies, Inc.
    Inventors: Dan Trock, Sergey Kleyman, Danny Sapoznikov
  • Patent number: 10983152
    Abstract: A device for determining impedance at a data pin of a communication interface. In one embodiment, the device includes a current source configured to selectively inject a test current to the data pin. The device also includes a sensing circuit for sensing a first test voltage corresponding to a voltage at the data pin without the test current injected, and a second test voltage corresponding to another voltage at the data pin with the test current injected. The sensing circuit determines the impedance at the data pin based on the first test voltage and the second test voltage.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: April 20, 2021
    Assignees: DIALOG SEMICONDUCTOR INC., DIALOG INTEGRATED CIRCUITS (TIANJIN) LIMITED
    Inventors: Fuqiang Shi, Jianming Yao, Weihai Huang, Yong Li, John William Kesterson
  • Patent number: 10901023
    Abstract: An example method includes stressing, under different circuit-stress test conditions, a plurality of different types of regional circuits susceptible to time dependent dielectric breakdown (TDDB), and in response, monitoring for levels of reliability failure associated with the plurality of different types of regional circuits. The method includes storing a set of stress-test data based on each of the levels of reliability failure, the set of stress-test data being stored within the integrated circuit to indicate reliability-threshold test data specific to the integrated circuit. Within the integrated circuit, an on-chip monitoring circuit indicates operational conditions of suspect reliability associated with dielectric breakdown of at least one of the plurality of different types of regional circuits.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: January 26, 2021
    Assignee: NXP B.V.
    Inventors: Jan-Peter Schat, Abdellatif Zanati
  • Patent number: 10895596
    Abstract: Methods and systems for localizing and resolving an integrated circuit include selecting one or more electrical stimuli to be applied to a device under test such that the electrical stimuli provide a baseline image and a distinguishing image effect when applied to the device under test. The one or more electrical stimuli are applied to the device under test. Emissions from the device under test are measured to provide a measurement data set and to collect the baseline image and the distinguishing image effect. The measurement includes dividing a field of view in a photon emission image into regions of interest. The measurement data set is analyzed to localize and evaluate circuit structures by comparing the baseline image and the distinguishing image effect. The analysis includes calculating a figure of merit for each region of interest that represents a degree of switching activity in the respective region of interest.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: January 19, 2021
    Assignee: International Business Machines Corporation
    Inventors: Peilin Song, Franco Stellari
  • Patent number: 10866283
    Abstract: A test system is provided. The test system includes a printed circuit board (PCB) and a plurality of integrated circuits (ICs) mounted on the PCB. A first IC of the plurality includes a first test circuit having a first test access port (TAP) controller. A second IC of the plurality includes a second test circuit having a second TAP controller and an embedded tester having a test data output coupled to a test data input of the first TAP controller by way of a link circuit. The embedded tester is configured to provide test control signals to the first TAP controller and the second TAP controller.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: December 15, 2020
    Assignee: NXP B.V.
    Inventor: Jan-Peter Schat
  • Patent number: 10853493
    Abstract: A system and method for detecting Trojans and other intermittent severe defects in a digital circuit design. A simulation of the digital circuit design results in a value change dump file, which is compiled to form a value change summary file containing counts of the numbers of value changes for the signals in the digital circuit design. A discriminative neural network analyzes the value change summary file to determine whether an intermittent severe defect is present. A corpus of digital circuit designs, with and without intermittent severe defects, is used to train the discriminative neural network. The training process may involve dimensionality reduction of the data, enlargement of the data set, and data compression using an autoencoder.
    Type: Grant
    Filed: October 9, 2017
    Date of Patent: December 1, 2020
    Assignee: Raytheon BBN Technologies Corp
    Inventors: Thomas Gilbert Roden, III, James Brian Schneider, Zachary Isaac Grove
  • Patent number: 10852351
    Abstract: Systems and methods of developing an integrated circuit implement selecting a desired yield for a circuit used in the integrated circuit. The desired yield corresponds to a desired failure probability of the circuit. The method includes determining a parameter threshold value that corresponds with the desired yield. The circuit passes if a parameter associated with the circuit is below the parameter threshold value and the desired yield indicates a percentage of instances of the circuit that pass according to the parameter threshold value. The method also includes using the parameter threshold value that corresponds with the desired yield during testing and improvement of a design of the integrated circuit, and providing the design of the integrated circuit for fabrication.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: December 1, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Tong Li, David Winston, Pravin Kamdar, Richard Daniel Kimmel
  • Patent number: 10802520
    Abstract: A system can include a device under test (DUT) having a DUT voltage, a cable connected to the DUT, the cable having a cable inductance, and a power supply configured as a current source to provide a wide bandwidth voltage source to the DUT, wherein the DUT voltage is independent of the cable inductance.
    Type: Grant
    Filed: April 12, 2013
    Date of Patent: October 13, 2020
    Assignee: Keithley Instruments, LLC
    Inventors: Kevin Cawley, Wayne Goeke, Gregory Sobolewski
  • Patent number: 10783979
    Abstract: A built-in self-test (BIST) circuit and a method of operating BIST circuit is disclosed. The BIST circuit is configured to generate a test pattern based on a plurality of test parameters including a first test parameter and a second test parameter and perform a test on at least one memory core. The method includes setting a sweep range comprising a sweep start point of the first test parameter and a sweep end point thereof; generating a first test pattern corresponding to each sweep point of the sweep range from the sweep start point of the first test parameter and the sweep end point thereof and providing the first test pattern to the at least one memory core; receiving output data corresponding to the first test pattern from the at least one memory core and comparing the output data and a predetermined reference data; and generating first test result information based on results of the comparing.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: September 22, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seung-ho Ok, Pyung-moon Zhang, Sang-hoon Shin, Ki-hyun Park, Yong-sik Park
  • Patent number: 10747258
    Abstract: A semiconductor device includes a system clock signal having a system clock period and a digital ring oscillator (DRO) cluster having DRO cells. Each of the DRO cells is disposed at a different location in the semiconductor device for producing a local ring oscillator clock signal. The local ring oscillator clock signal has a ring oscillator clock period that is shorter than the system clock period. The DRO cluster is configured to measure respective ring oscillator clock count in each of the DRO cells during a time window synchronized to the system clock.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: August 18, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Eyal Freund, Yaniv Shapira
  • Patent number: 10747657
    Abstract: Disclosed herein is a system for facilitating execution of test cases, in accordance with some embodiments. Accordingly, the system may include a communication device configured for receiving a first test case data including a plurality of first test steps and a second test case data including a plurality of second test steps. Further, the system may include a processing device configured for identifying a common test step between the plurality of first test steps and the plurality of second test steps. Further, the processing device may be configured for generating a plurality of first test results associated with the plurality of first test steps based on execution of the plurality of first test steps. Further, the system may include a storage device configured for storing the plurality of first test results in association with the plurality of first test steps.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: August 18, 2020
    Inventor: JayaSudha Yedalla
  • Patent number: 10735348
    Abstract: An intermediary server receives a resource request for a requested resource from a client computer. The intermediary server responds to the resource request by initiating an interactive dialog between the intermediary server and the client computer, where the interactive dialog identifies a desired resource ability of the requested resource. The intermediary server identifies, based on responses to the interactive dialog from the client computer, an alternative resource that best meets the desired resource ability, wherein the requested resource and the alternative resource are a same type of resource, and wherein the interactive dialog uses an interactive exchange that interprets interactive dialog responses from the client computer in order to identify the desired resource ability and the alternative resource that best meets the desired resource ability and then instructs a resource server to send the alternative resource to the client computer.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: August 4, 2020
    Assignee: International Business Machines Corporation
    Inventors: Rotem Aharonov, Salil Ahuja, Rama K. T. Akkiraju, David Amid, Ateret Anaby-Tavor, Jason M. Leonard, Mitchell Mason
  • Patent number: 10725089
    Abstract: A semiconductor includes a first circuit, a second circuit, and a comparison circuit. The first circuit includes a first transistor. The first circuit is configured to output a first output. A second circuit includes a second transistor. The second circuit is configured to output a second output. A comparison circuit is coupled to the first circuit and the second circuit. The comparison circuit is configured to compare the first output and the second output to generate a comparison result, and to output the comparison result. The first transistor decays over a time interval and the first output changes from a first voltage value to a second voltage value over the time interval. The second transistor does not decay over the time interval and the second output of the second circuit maintains to be the third voltage value over the time interval.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: July 28, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chih-Jen Chen
  • Patent number: 10715790
    Abstract: The present invention includes a system and method for three-dimensional imaging and analysis of electronic components. Specifically, it permits rapid and reliable inspection of the lead foot angle in integrated circuit packages. A first image capturing device, a second image capturing device and a third image capturing device are arranged in a “corner shape” or “L-shape.” The first image capturing device forms the corner and obtains an image of the bottom of the component. The perspective viewing angle of the second image capturing device and the perspective viewing angle of the third image capturing device are orthogonal to each other to allow accurate three-dimensional reconstruction of the lead angles and detection of flaws or bends.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: July 14, 2020
    Assignee: GENERIC POWER PTE LTD
    Inventors: Hak Wee Tang, Ruini Cao, Kok Yeow Lim, Zin Oo Thant
  • Patent number: 10585128
    Abstract: A method for analyzing noise spectrum of an electronic device includes storing a waveform data including a plurality of data points, the waveform data is obtained by measuring a target signal from the electronic device, removing data points corresponding to a background noise fluctuation based on a smooth curve of the waveform data, data points considered candidates for peaks are extracted from the waveform data, classifying the extracted data points based on a distance between adjacent data points in order to discriminate a cluster of distant data points from data points closely positioned to dominant peaks, determining the dominant peaks based on the cluster of distant data points such that the data points closely positioned to the dominant peaks are ignored, each dominant peak corresponds to the characteristic of the electronic device, and outputting the dominant peaks as an analysis result for the electronic device.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: March 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Shinichi Ikami, Lijie Qiao
  • Patent number: 10571499
    Abstract: A device for determining impedance at a data pin of a communication interface. In one embodiment, the device includes a current source configured to selectively inject a test current to the data pin. The device also includes a sensing circuit for sensing a first test voltage corresponding to a voltage at the data pin without the test current injected, and a second test voltage corresponding to another voltage at the data pin with the test current injected. The sensing circuit determines the impedance at the data pin based on the first test voltage and the second test voltage.
    Type: Grant
    Filed: September 23, 2014
    Date of Patent: February 25, 2020
    Assignees: DIALOG SEMICONDUCTOR INC., DIALOG INTEGRATED CIRCUITS (TIANJIN) LIMITED
    Inventors: Fuqiang Shi, Jianming Yao, Weihai Huang, Yong Li, John William Kesterson
  • Patent number: 10564047
    Abstract: Carbon nanotube-based multi-sensors for packaging applications and methods to form the carbon nanotube-based multi-sensors are capable of simultaneously measuring at least two measurands including temperature, strain, and humidity via changes in its electrical properties.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: February 18, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Eric Duchesne, Dominique Drouin, Hélène Frémont, Simon Landry, Aurore F. M. E. Quelennec, Umar Shafique, Patrick R. J. Wilson
  • Patent number: 10539613
    Abstract: An analog circuit fault diagnosis method using a single testable node comprises the following steps: (1) obtaining prior sample data vectors under each fault mode; (2) computing a statistical average of the prior sample data vectors under each of the fault modes; (3) decomposing a signal by an orthogonal Haar wavelet filter set; (4) extracting the feature factor of the prior sample fault modes; (5) extracting a fault-mode-to-be-tested feature factor; (6) computing a correlation coefficient matrix and correlation metric parameters between the feature factor of the prior sample fault modes and the feature factor of the fault-mode-to-be-tested; and (7) determining a fault mode according to a maximal correlation principle by comparing the correlation metric parameters.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: January 21, 2020
    Assignee: HEFEI UNIVERSITY OF TECHNOLOGY
    Inventors: Yigang He, Lifen Yuan, Lei Wu, Yesheng Sun, Chaolong Zhang, Ying Long, Zhen Cheng, Zhijie Yuan, Deqin Zhao
  • Patent number: 10514417
    Abstract: An IC degradation sensor is disclosed. The IC degradation management sensor includes an odd number of first logic gates electrically connected in a ring oscillator configuration, each first logic gate having an input and an output. Each first logic gate further includes a first PMOS transistor, a first NMOS transistor and a second logic gate having an input and an output. The input of the second logic gate is the input of the first logic gate, and the drains of the first PMOS transistor and the first NMOS transistor are electrically connected to the output of the second logic gate, and the output of the second logic gate is the output of the first logic gate.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: December 24, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Zeng Kang, Chih-Hsien Chang, Wen-Shen Chou, Yung-Chow Peng
  • Patent number: 10460697
    Abstract: A circuit device 500 includes a comparator circuit CP and a switching circuit SW. The switching circuit SW supplies a detection voltage Vdet that is based on a result of detection from the environment sensor to a first input terminal Tin1 of the comparator circuit CP and a reference voltage Vref to a second input terminal Tin2 of the comparator circuit CP during a first period out of a detection period, and supplies the reference voltage Vref to the first input terminal Tin1 and the detection voltage Vdet to the second input terminal Tin2 during a second period out of the detection period. TB>TA is satisfied, where TA denotes a duration of the detection period, and TB denotes a duration of a period from an end of a first detection period to a start of a second detection period that is subsequent to the first detection period.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: October 29, 2019
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Shigeru Okada
  • Patent number: 10445205
    Abstract: A method and device for performing testing across a plurality of smart devices is disclosed. The method includes registering the plurality of smart devices to be accessed for performing testing. The method further incudes determining at least one time-window for each of the plurality of smart devices, wherein a smart device is in an idle mode during the at least one time-window. The method includes gathering testing criteria and time duration for performing a testing operation. The method further includes dynamically creating a test group that includes one or more smart devices from the plurality of smart devices. Each of the one or more smart devices in the test group satisfy the testing criteria and the at least one time-window of each smart device in the test group is within the time duration.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: October 15, 2019
    Assignee: Wipro Limited
    Inventor: Darshan Havinal
  • Patent number: 10431136
    Abstract: The disclosure discloses an array substrate, a display panel, and a display device, and the array substrate includes: a plurality of data lines arranged in a display area, and a demultiplexer assembly, a test switch assembly, and a plurality of data signal fanout wires, arranged respectively in a non-display area, where each of the signal output terminals of the demultiplexer assembly is electrically connected with one of the plurality of data lines, each of the signal input terminals of the demultiplexer assembly is electrically connected respectively with one of the plurality of data signal fanout wires, and one of the output terminals of the test switch assembly; and the test switch assembly is arranged on the side of the demultiplexer assembly away from the display area.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: October 1, 2019
    Assignee: XIAMEN TIANMA MICRO-ELECTRONICS CO., LTD.
    Inventor: Hongbo Zhou
  • Patent number: 10380305
    Abstract: A method is disclosed for designing a test vehicle utilizing a layout of a real integrated circuit (IC) product. The method comprises: importing an original full-chip layout of the real IC product; partitioning the original full-chip layout into probe groups, each probe group comprising probe pads, and, a plurality of IC devices within an area of interest (AOI) having original routing interconnect for those IC devices; selecting a set of IC devices within the AOI; and, for the selected set of IC devices, using pattern extraction to remove the original routing interconnect, and create customized interconnect layers (CIL) to reconfigure connection between the individual IC devices. Incorporating the selected set of IC devices with the CIL into the original full-chip layout creates a modified full-chip layout such that a wafer fabricated using the modified full-chip layout comprises a real product with a built-in test vehicle.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: August 13, 2019
    Assignee: PDF Solutions, Inc.
    Inventors: Yih-Yuh Doong, Sheng-Che Lin, Chia-Chi Lin, Hans Eisenmann, Cho-Si Huang, Tzupin Shen, Christopher Hess, Kimon Michaels
  • Patent number: 10331413
    Abstract: A random number generating system and a random number generating method thereof are provided. The random number generating system includes a random number generator, a random mask circuit, a bit reduction logic circuit and a receiver. The random number generator provides a random number sequence. The random mask circuit receives the random number sequence to provide a random number mask sequence and a random mask indication sequence, wherein bits of the random mask indication sequence in a first logical level corresponded to bits of the random number mask sequence in the high impedance state. The bit reduction logic circuit receives the random number sequence and the random mask indication sequence to provide the comparison key. The receiver receives a random number mask sequence to provide a verification key, where the verification key is the same as the comparison key.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: June 25, 2019
    Assignee: Winbond Electronics Corp.
    Inventors: Wen-Chiao Ho, Pil-Sang Ryoo
  • Patent number: 10331531
    Abstract: Apparatus and a method for processor core self-testing are disclosed. The apparatus comprises processor core circuitry to perform data processing operations by executing data processing instructions. Separate self-test control circuitry causes the processor core circuitry to temporarily switch from a first state of executing the data processing instructions to a second state of executing a self-test sequence of instructions, before returning to the first state of executing the data processing instructions without a reboot of the processor core circuitry being required. There is also self-test support circuitry, wherein the processor core circuitry is responsive to the self-test sequence of instructions to cause an export of at least one self-test data item via the self-test support circuitry to the self-test control circuitry.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: June 25, 2019
    Assignee: ARM Limited
    Inventors: Balaji Venu, Kauser Yakub Johar, Marco Bonino
  • Patent number: 10289514
    Abstract: An apparatus and method for a user configurable reliability control loop. For example, one embodiment of a processor comprises: a reliability meter to track accumulated stress on components of the processor based on measured processor operating conditions; and a controller to receive stress rate limit information and to responsively specify a set of N operating limits on the processor in accordance with the accumulated stress and the stress rate limit information; and performance selection logic to output one or more actual operating conditions for the processor based on the N operating limits specified by the controller.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: May 14, 2019
    Assignee: Intel Corporation
    Inventors: Dorit Shapira, Krishnakanth V. Sistla, Efraim Rotem, Eric Distefano, James G. Hermerding, II, Esfir Natanzon
  • Patent number: 10276456
    Abstract: The present disclosure provides an array substrate, its manufacturing method and testing method, and a display device. The array substrate includes a (Test Element Group) TEG arranged at a non-display area and including a plurality of to-be-tested elements and a plurality of testing contact electrodes configured to test the to-be-tested elements. Each of the to-be-tested elements is connected to at least two of the testing contact electrodes, and at least one of the testing contact electrodes is shared by at least two of the to-be-tested elements.
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: April 30, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Yu Ji, Chengye Wu, Zhengyun Wu, Lei Feng, Bei Wang, Lei Song
  • Patent number: 10224296
    Abstract: Provided is a device for generating an identification key using a process variation during a manufacturing process of a conductive layer. The device for generating an identification key may include a plurality of conductive layers designed so as to be formed in a first region within a semiconductor chip, the density in which the plurality of conductive layers are disposed in the first region being at least a first threshold value and not more than a second threshold value, the first and second threshold values being less than a minimum density according to the design rules for ensuring that all of the plurality of conductive layers are formed in the first region; and a reader which provides an identification key by identifying if, among the plurality of conductive layers, a previously designated first conductive layer has been formed.
    Type: Grant
    Filed: February 17, 2014
    Date of Patent: March 5, 2019
    Assignee: ICTK Holdings Co., Ltd.
    Inventors: Byong Deok Choi, Dong Kyue Kim
  • Patent number: 10176234
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for impact analysis. One of the methods includes receiving information about at least two logical datasets, the information identifying, for each logical dataset, a field in that logical dataset and format information about that field. The method includes receiving information about a transformation identifying a first logical dataset from which the transformation is to receive data and a second logical dataset to which the transformed data is provided. The method includes receiving one or more proposed changes to at least one of the fields. The method includes analyzing the proposed changes based on information about the transformation and information about the first logical dataset and the second logical dataset. The method includes calculating metrics of the proposed change based on the analysis. The method also includes storing information about the metrics.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: January 8, 2019
    Assignee: Ab Initio Technology LLC
    Inventors: Joel Gould, Scott Studer
  • Patent number: 10148491
    Abstract: Methods, systems, and apparatus for detecting fault are disclosed. In one aspect, a signal having an initial pulse width is transmitted on a telecommunication line. A fault location index is identified based on at least one fluctuating echo tap of the signal. An updated pulse width is determined based on the initial pulse width and the fault location index. The fault location index is updated based on at least one fluctuating echo tap of an updated signal having the updated pulse width.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: December 4, 2018
    Assignee: ADTRAN, INC.
    Inventor: Arlynn W. Wilson
  • Patent number: 10090288
    Abstract: A semiconductor system includes a first semiconductor device suitable for outputting an external command and a termination control signal and being inputted with a data signal; and a second semiconductor device suitable for generating a termination enable signal in response to the external command and the termination control signal, generating a pull-up signal in response to the termination enable signal, and generating a pull-down signal in response to the termination enable signal and a test mode signal.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: October 2, 2018
    Assignee: SK hynix Inc.
    Inventor: Jung Hyun Kim
  • Patent number: 10036771
    Abstract: According to various embodiments, a circuit arrangement is provided which includes a bridge circuit having at least two field effect transistors and a measurement circuit configured to measure a forward voltage of a body diode of any one of the at least two field effect transistors resulting from a current flowing through the field effect transistor.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: July 31, 2018
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Benno Koeppl, Frank Auer, Andreas Kiep
  • Patent number: 10002810
    Abstract: Methods and circuits for monitoring circuit degradation include measuring degradation in a plurality of on-chip test oscillators that vary according to a quantity that influences hot carrier injection (HCI) degradation. The measured degradation for the plurality of test oscillators is extrapolated to determine a bias temperature instability (BTI) contribution to the measured degradation. The BTI contribution is subtracted from the measured degradation at a predetermined value of the quantity to determine the HCI degradation for devices represented by the predetermined value.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: June 19, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Keith A. Jenkins, Barry Linder
  • Patent number: 9945888
    Abstract: A high output voltage VOH level and a low output voltage VOL level parametric test system may include test circuitry coupled to output nodes of input/output (I/O) driver circuits. The test circuitry may source and sink current to the output nodes while the I/O driver circuits are in pull down and pull up states, respectively, in order to generate output voltages on the output nodes. The parametric test system may compare the output voltages with a plurality of high and low reference levels to determine ranges of the output voltages. The ranges may be used to determine whether the I/O driver circuits pass the VOH and VOL test requirements. The VOH/VOL test system may be implemented on-chip with other components of the external device, which may eliminate the need to perform other parametric testing with external test equipment.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: April 17, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Prasad Naidu, Jayanth Mysore Thimmaiah, Prashant Singhai
  • Patent number: 9933477
    Abstract: A method is described that includes monitoring degradation of a semiconductor chip's transistors during normal operation. The method further includes raising an internal voltage of the semiconductor chip in response to the degradation. The method further includes determining that the degradation has reached a threshold. The method further includes triggering application of an elevated temperature to the semiconductor chip so that the degradation is at least partially reversed. The method further includes applying a new lower internal voltage of the semiconductor chip in account of the degradation reversal.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: April 3, 2018
    Assignee: INTEL CORPORATION
    Inventors: Shmuel Zobel, Maxim Levit
  • Patent number: 9891873
    Abstract: A print system includes a memory, a replacement information output unit, and a display controller. The memory includes plural storage media that store image data to be supplied to a printer. The replacement information output unit receives, from each of the plural storage media, attribute information representing an internal state of the storage medium, and outputs information specifying a storage medium that needs to be replaced among the plural storage media by using the attribute information. The display controller receives the information output by the replacement information output unit and performs control to display, on a display, for the storage medium specified by the information, information indicating a physical position of the storage medium in the memory and indicating that the storage medium needs to be replaced.
    Type: Grant
    Filed: April 14, 2016
    Date of Patent: February 13, 2018
    Assignee: FUJI XEROX CO., LTD.
    Inventors: Nobuhide Kawabata, Yasuhiro Mori, Satoshi Misawa
  • Patent number: 9869708
    Abstract: A method of protecting devices within an integrated circuit during electro-static discharge (ESD) testing using an ESD test system is provided. The method includes applying a direct current (DC) bias voltage to an input of at least one device of the integrated circuit and applying an ESD simulated signal to at least one other input of the integrated circuit. The applied ESD simulated signal is conducted along a first current path to a first ground, while a low-current signal associated with the at least one device is conducted along a second current path to the second ground. The DC bias voltage is maintained between the input of the at least one device and the second ground at a substantially constant value in response to a signal variation on the second ground that results from the applied ESD simulated signal.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: January 16, 2018
    Assignee: International Business Machines Corporation
    Inventors: Shunhua Chang, James Paul Di Sarro, Robert J. Gauthier, Jr., Nathan Jack, Souvick Mitra
  • Patent number: 9857420
    Abstract: An integrated circuit includes a sensing output terminal, a driver, a first sensing input terminal, a second sensing input terminal and a sensor. The driver is used to transmit a sensing test signal through the sensing output terminal. The first sensing input terminal is coupled to the sensing output terminal through a first external circuit for receiving the sensing test signal. The second sensing input terminal is coupled to the sensing output terminal through a second external circuit for receiving the sensing test signal. The sensor is used to compare the sensing test signals received by the first sensing input terminal and the second sensing input terminal with a clock signal respectively to generate a first comparison result and a second comparison result.
    Type: Grant
    Filed: June 10, 2015
    Date of Patent: January 2, 2018
    Assignee: AU OPTRONICS CORP.
    Inventors: Chun-Kuei Wen, Hung-Min Shih, Che-Yu Kuo
  • Patent number: 9842784
    Abstract: A system according to some examples herein includes a base chip which may include a plurality of attachment slots for attaching dies thereto. One or more of the attachment slots may be programmable attachment slots. The base chip may further include circuitry for interconnecting the dies attached to the base chip. For example, the base chip may include a plurality of cross bar switches, each of which is associated with respective ones of the plurality of attachment slots. The base chip may further include a configuration block, which is adapted to receive and transmit test signals for determining electrically connected signal lines of one or more attachment slots when one or more dies are attached to the base chip and which is further adapted to receive configuration data for programming signal (including power and ground) channels of the cross bar switches.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: December 12, 2017
    Assignee: ZGLUE, INC.
    Inventors: Jawad Nasrullah, Ming Zhang
  • Patent number: 9778880
    Abstract: A memory control circuit unit, a memory storage device and a data transmitting method are provided. The memory storage device coupled to a first host system includes a reset pin. The memory control circuit unit of the memory storage device includes a pulse pattern detector. The reset pin is coupled to a second host system and is configured to receive a first pulse signal from the second host system. The pulse pattern detector is coupled to the reset pin, and is configured to determine whether the first pulse signal is conformed to a first predetermined serial pulse pattern or not. If the first pulse signal is conformed to the first predetermined serial pulse pattern, the memory control circuit unit is configured to disable a reset function of the memory storage device.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: October 3, 2017
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Ming-Fu Lai, Rui-Chang Huang
  • Patent number: 9741707
    Abstract: Approaches for checking a design of an integrated circuit using an antenna rule are provided. A method includes determining a figure of merit for a transistor based on a resistance of a shunt path of the transistor relative to the size of the antenna and the size of the transistor. The method also includes comparing the determined figure of merit to a limit. The method further includes deeming the transistor to pass the antenna rule when the figure of merit is less than the limit, and deeming the transistor to fail the antenna rule when the figure of merit is greater than the limit. The determining and the comparing are performed by a computer device.
    Type: Grant
    Filed: April 14, 2016
    Date of Patent: August 22, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Zachary Henderson, Jason D. Hibbeler, Terence B. Hook, Nicholas Palmer, Kirk D. Peterson
  • Patent number: 9720031
    Abstract: A method for increasing the reliability of transducers, having a first and a second IC, the two ICs have exactly the same or substantially the same monolithically integrated circuit components, each with a sensor and a signal contact designed for bidirectional data transmission and a reference contact and a supply voltage contact. A signal generated as a function of the physical quantity sensed by the relevant sensor is applied to the signal contact. The signal of the first IC is compared with the signal of the second IC by a monitoring device, and then the result of the comparison is communicated to an enable device, and the signal of the first IC is sent by an enable device to the control unit if both signals lie in a predefined useful band.
    Type: Grant
    Filed: November 10, 2015
    Date of Patent: August 1, 2017
    Assignee: TDK—Micronas GmbH
    Inventor: Michael Drescher
  • Patent number: 9672310
    Abstract: In an embodiment, the amount of supply voltage guardband to prevent incorrect operation due to aging effects may be modeled using an IC-specific age model generated early in the product life cycle of the IC. For example, high temperature operating life (HTOL) testing may be performed at multiple temperatures and/or voltages to develop the IC-specific age model. The IC-specific age model may be more accurate then the calculations used to develop guardband voltage as discussed previously, which rely on the aging of a single transistor. The IC-specific age model may be used along with monitoring of the aging effects during operation of the IC to predict an amount of increased guardband voltage that is currently desirable to apply to the IC. The predicted amount may vary from about zero when the IC is new to the full amount of guardband voltage when the IC is nearing end of life.
    Type: Grant
    Filed: July 9, 2015
    Date of Patent: June 6, 2017
    Assignee: Apple Inc.
    Inventors: Antonietta Oliva, John G. Dorsey, Keith Cox, Norman J. Rohrer, Sribalan Santhanam, Sung Wook Kang, Mohamed H. Abu-Rama, Ashish R. Jain
  • Patent number: 9647652
    Abstract: A semiconductor device includes a first pre-stress block suitable for generating a first load signal, which corresponds to an active signal during an active mode and/or to a high voltage level during a precharge mode, in response to a stress section signal; a first delay amount reflection block suitable for reflecting a first delay amount in the first load signal in response to one or more first delay amount control signals; and a first main stress block suitable for generating a word line driving control signal, which corresponds to the active signal during the active mode and the high voltage level during the precharge mode, in response to the stress section signal and the first load signal.
    Type: Grant
    Filed: January 19, 2016
    Date of Patent: May 9, 2017
    Assignee: SK Hynix Inc.
    Inventors: Sung-Soo Chi, Young-Sik Heo
  • Patent number: 9645196
    Abstract: A test structure (200) in an integrated circuit (100) includes a probe pad (210) disposed at a surface of a die (102) of the integrated circuit, a transmission gate (202) for connecting portions of an electronic circuit within the integrated circuit in response to a momentary signal applied to the probe pad, a first inverter (221) having an input coupled to the probe pad and having an output coupled to a control input of the transmission gate, and a second inverter (222) having an input coupled to an output of the first inverter and having an output coupled to another control input of the transmission gate. The output of the second inverter is coupled to the input of the first inverter. Upon power-up, the transmission gate is open. After the momentary signal is applied to the probe pad, the transmission gate closes and remains closed until power is disconnected.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: May 9, 2017
    Assignee: NXP USA, INC.
    Inventors: Fabio Duarte De Martin, Andre Luis Vilas Boas
  • Patent number: 9557369
    Abstract: Methods for reliability testing include applying a stress voltage to a device under test (DUT); measuring a leakage current across the DUT; triggering measurement of optical emissions from the DUT based on the timing of the measurement of the leakage current; and correlating measurements of the leakage current with measurements of the optical emissions to determine a time and location of a defect occurrence within the DUT by locating instances of increased noise in the leakage current that correspond in time with instances of increased optical emissions.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: January 31, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jifeng Chen, Dirk Pfeiffer, Thomas M. Shaw, Peilin Song, Franco Stellari
  • Patent number: 9542515
    Abstract: Methods, systems, and computer readable media are disclosed for simulating a circuit. The method may comprise a step of providing a network model of the circuit having a plurality of ports, the plurality of ports being associated with one or more net pairs. The method may also comprise combining the plurality of ports into one or more groups based on the net pairs, each group corresponding to a net pair. In addition, the method may comprise calculating, for each group, one or more expansion elements, wherein the one or more expansion elements are associated with a shared property among all ports of the group. Moreover, the method may comprise simulating the circuit using a combination of the expansion elements calculated for each group.
    Type: Grant
    Filed: November 28, 2011
    Date of Patent: January 10, 2017
    Assignee: Cadence Design Systems, Inc.
    Inventors: Jian Liu, Xiao Lin, Anyu Kuo, Jiayuan Fang