Abstract: A system including an interface and a plurality of solder joint testing modules. The interface is configured to receive test configuration data to configure each of a plurality of integrated system test (IST) modules. Each of the plurality of solder joint testing modules is configured to, based on the test configuration data, i) apply a pulse having a predetermined amplitude and width to a solder joint associated with a respective one of the plurality of IST modules, ii) monitor a resultant waveform that is generated in response to the pulse, and iii) determine an integrity of the solder joint in response to the resultant waveform. Each of the plurality of solder joint testing modules and the respective ones of the plurality of IST modules are located on a same system on chip (SOC).

Abstract: In a method for testing functionality of a field device or a field device for sending a control signal to a final controlling device of an industrial processing plant, the final controlling device is operated by a secondary power. With the method, a current/secondary power converter is provided for generating a predetermined secondary power safety control signal to bring the final controlling device into a predetermined safe position. An electronic safety circuit is provided connected to the current/secondary power converter which, depending on an electrical control signal received by the field device, is switched from a passive state into an active state in which the electronic safety circuit causes the current/secondary power converter to output the secondary output power safety control signal. The safety circuit automatically adopts the active state if the electrical control signal falls below or exceeds at least one of a current and a voltage threshold value specific to the safety circuit.

Abstract: A semiconductor integrated circuit includes a bump pad through which data is outputted, a probe test pad having a larger size than the bump pad, a first output drive unit configured to drive the bump pad at a first drivability in response to output data, a second output drive unit configured to drive the probe test pad at a second drivability higher than the first drivability in response to the output data, and a multiplexing unit configured to transfer the output data to the first output drive unit or the second output drive unit in response to a test mode signal.

Abstract: A computer system for safety critical sensor variables includes first and second sensors which respectively output first and second sensor variables, a computer, and an independent comparator. The computer calculates an output variable from the first sensor variable by a first function. The computer calculates a comparison variable from the output variable by a second function. The comparison variable and the second sensor variable are applied to the input of the comparator. The second sensor variable is not an input variable of the computer and differs from the first sensor variable in terms of its qualitative value. By calculations of the computer and, if appropriate, of the comparator, an expected comparison variable for the second sensor variable is determined from the calculated output variable, and the correspondence of the two variables is checked by the comparator. Specific internal errors of the computer can thereby be discovered.

Abstract: A method of testing an integrated circuit (IC) having a plurality of dies can include receiving, within a master die of the plurality of dies of the IC, a configuration data set specifying a circuit design, wherein the circuit design is instantiated within the master die. The method can include broadcasting the configuration data set to at least one slave die, wherein the circuit design is instantiated within each slave die and receiving, within the master die, a test vector set. The method also can include broadcasting the test vector set to the at least one slave die and responsive to each die executing the test vector set, storing test output data generated by each die.

Abstract: A method for adapting the signal transmission between two electronic devices (1, 2) that are connected to each other via a physical interface and that each have a transmitter (8a, 8b) and a receiver (7a, 7b), wherein analog signals are transmitted from the transmitter (8a, 8b) of one device (1, 2) along a transmission path (9a, 9b) to the receiver (7a, 7b) of the other device (1, 2). Known scattering parameters (10a, 10b, 10c, 11d) for describing the electromagnetic wave propagation in the transmission path (9a, 9b) between the receiver (7a, 7b) of the first device (1, 2) and the transmitter (8a, 8b) of the second device (1, 2) are retrieved by the first device (1, 2), transmitted to the second device (1, 2), and parameters of the transmitter (8a, 8b) in the second device (1, 2) are adapted with reference to a high-frequency description of the transmission path (9a, 9b) as a function of all of the scattering parameters (10a to 10d, 11a to 11d) known to the two devices.

Abstract: Embodiments herein present a method for automated simulation testbench generation for serializer/deserializer datapath systems. The method provides a database of transactors for generating and checking data within the datapath system, wherein the transactors are adaptable to arbitrary configurations of the datapath system. The database is provided with a single set of transactors per core. Next, the method automatically selects one set of transactors from the database for inclusion into the simulation testbenches. Following this, the method maps the first datapath and the second datapath through the datapath system by interconnecting the selected set of the transactors with the datapath system. The method further comprises setting control pins on the cores to facilitate propagation of the data through the cores of the datapath system. Subsequently, the control pins are traced to input ports and control registers.

Abstract: Some embodiments include apparatus, systems, and methods comprising semiconductor dice arranged in a stack, a number of connections configured to provide communication among the dice, at least a portion of the connections going through at least one of the dice, and a module configured to check for defects in the connections and to repair defects the connections.

Abstract: A semiconductor device includes, in one package: a plurality of semiconductor chips having different operating voltages; and a power supply circuit configured to receive an input voltage from an external power supply and supply operating voltages to the semiconductor chips. The power supply circuit is capable of switching and supplying a plurality of different voltages for each one of the semiconductor chips.

Abstract: Disclosed is a test circuit including a first transfer circuit, a second transfer circuit and comparators and performing parallel testing of a plurality of chips under test. The first transfer circuit includes flip-flops. A data pattern from a tester is supplied to the initial stage chip under test. To the remaining chips under test, output data from the corresponding stages of the first transfer circuit are supplied. The second transfer circuit sequentially transfers an output of the initial stage chip under test, as an expected value pattern, in response to clock cycles. The comparator compares output data of the chip under test with an expected value pattern from the corresponding stage of the second transfer circuit.

Abstract: It is possible to provide a circuit and method for carrying out a parallel test using BOST (Built Out Self Test). The circuit includes first transfer circuits (11-1, 11-2, . . . ) that extract a data pattern supplied to a complete operating article chip (10) in a BOST (3) from the BOST and that successively transmit the data pattern in response to a clock signal, and second transfer circuits (12-1, 12-2, . . . ) that extract output data from the complete operating article chip (10) as an expectation value pattern and that successively transmit the expectation value pattern in response to the clock signal. The data pattern supplied to the complete operating article chip (10) is applied to one chip to be measured (10-1) and the data pattern from a corresponding stage of the first transfer circuits (11-1, 11-2, . . . ) is applied to each of other chips to be measured (10-2, . . . ).

Abstract: A method of topside only dual-side testing of an electronic assembly includes providing a singulated through substrate via (TSV) die flip chip attached to a die support including a package substrate. The TSVs on the TSV die extend from its frontside to contactable TSV tips on its bottomside. The TSVs on the frontside of the TSV die are coupled to embedded topside substrate pads on a top surface of the ML substrate. The die support includes lateral coupling paths between at least a portion of the embedded topside substrate pads and lateral topside pads on a topside surface of the die support lateral to the die area. The contactable TSV tips are contacted with probes to provide a first topside connection to the TSVs, and the lateral topside pads are contacted with probes to provide a second topside connection. Dual-side testing across the electronic assembly is performed using the first and second topside connections.

Abstract: An integrated circuit device includes a stacked die and a base die having probe pads that directly couple to test logic of the base die to implement a scan chain for testing of the integrated circuit device. The base die further includes contacts disposed on a back side of the base die and through-die vias coupled to the contacts and coupled to programmable logic of the base die. The base die also includes a first probe pad configured to couple test input, a second probe pad configured to couple test output, and a third probe pad configured to couple control signals. Test logic of the base die is configured to couple to additional test logic of the stacked die to implement the scan chain. The probe pads are coupled directly to the test logic such that configuration of the programmable logic is not required to implement the scan chain.

Abstract: A method, system, and program product for identifying at least one bit failure among a plurality of semiconductor chips are provided. A first aspect of the invention provides a method of identifying at least one bit failure signature among a plurality of semiconductor chips, the method comprising: counting failures of each failing bit among the plurality of semiconductor chips; determining a most commonly failing bit (MCFB) among the failing bits; establishing a bit failure signature including the MCFB; counting failures of each failing bit on semiconductor chips on which the MCFB fails; determining a next most commonly failing bit (NMCFB) among the failing bits on semiconductor chips on which the MCFB fails; determining whether the NMCFB tends to fail when the MCFB fails; and in response to a determination that the NMCFB tends to fail when the MCFB fails, adding the NMCFB to the bit failure signature.

Abstract: To provide a semiconductor device including an interface chip and a core chip and a measurement-target signal line and a reference signal line each including a through silicon via provided in the core chip and electrically connecting the interface chip and the core chip. The interface chip outputs a test clock generated by a first signal generation circuit to the core chip. The core chip includes a second signal generation circuit that generates a predetermined measurement signal from the test clock, and outputs the predetermined measurement signal to the measurement-target signal line and the reference signal line in a simultaneous manner. Further, the interface chip detects a phase difference of a plurality of predetermined measurement signals input via the measurement-target signal line and the reference signal line by an operational amplifier, and outputs a test result to a determination circuit.

Abstract: A test kit for testing a chip subassembly and a testing method by using the same is provided. The chip subassembly includes at least two stacked chips each having a number of electric contacts is provided. The test kit includes a test socket and a test plate. The test socket is configured to electrically engage the electric contacts on a first side of the chip subassembly. The test plate has at least a number of first probes configured for electrically engaging the electric contacts on a second side of the chip subassembly. At least one of the test socket and the test plate has a number of second probes for electrically connecting the test socket and the test plate.

Abstract: The invention relates to an apparatus for testing an integrated circuit of an electronic device.

Abstract: A testing apparatus includes a test controller configured to output a plurality of chip selection signals for selecting chips to be tested from among a plurality of chips, a plurality of first control signals for controlling supply of a power supply voltage to the chips selected by the chip selection signals, and a plurality of second control signals for controlling receiving of test voltages output from the chips supplied with the power supply voltage, and a probe card including one or more test blocks each having a plurality of signal transmitters configured to respectively transfer the power supply voltage to the corresponding chips in response to the different first control signals and respectively apply the test voltages output from the corresponding chips to the test controller in response to the different second control signals.

Abstract: A socket for testing a semiconductor chip includes a base cover, a conductive sheet, upper plungers, a housing, lower plungers and a support plate. The base cover has a coupling opening in the central portion thereof, and the conductive sheet is fitted into the coupling opening of the base cover and includes conductive parts and an insulation part. The upper plungers are seated onto upper ends of the conductive parts and come into contact with corresponding terminals of the semiconductor chip. The housing has insert holes at positions corresponding to the upper plungers and fastens the upper plungers to the corresponding conductive parts. The lower plungers are provided under lower ends of the conductive parts and come into contact with corresponding terminals of a PCB to electrically connect the conductive parts to the PCB.

Abstract: An accelerated failure indicator embedded on a semiconductor chip includes an insulating region; a circuit located inside the insulating region; a heating element located inside the insulating region, the heating element configured to heat the circuit to a temperature higher than an operating temperature of the semiconductor chip; and a reliability monitor configured to monitor the circuit for degradation, and further configured to trigger an alarm in the event that the degradation of the circuit exceeds a predetermined threshold. A method of operating an accelerated failure indicator embedded on a semiconductor chip includes determining an operating temperature of the semiconductor chip; heating a circuit located inside an insulating region of the accelerated failure indicator to a temperature higher than the determined operating temperature; monitoring the circuit for degradation; and triggering an alarm in the event that the degradation of the circuit exceeds a predetermined threshold.

Abstract: A monitored test block for use in medium and high voltage electrical monitoring circuits such as found in substation facilities that signals via a communication protocol the operational status of potential, current and signal secondary circuits when connected to protection and monitoring devices (or test devices) such as protective relays, fault recorders or any other monitoring and controlling device. The monitored test block includes various safety features to prevent damage to the equipment or harm to a technician. The monitoring circuits may be located in the front for ease of access.

Abstract: A detecting system for detecting the connection of two connectors includes a number of first and second linking lines. The detecting system includes a number of first detection switches, a number of pull-down resistors, a number of second detection switches, a number of pull-up resistors, and a detection module. Each first linking line is grounded via each first detection switch and each pull-down resistor in series. The terminals of the pull-down resistors connected to the first detection switches are defined as first detecting ends. Each second linking line is electrically coupled to a high potential via each second detection switch and each pull-up resistors in series. The detection module with a threshold value preset is configured for comparing the voltage value at the first detecting ends with the threshold value, and outputting a result to determine whether the first linking lines are electrically connected to the second linking lines respectively.

Abstract: A set of first substrate and second substrate are manufactured with a built-in N-fold rotational symmetry around the center axis of each substrate, wherein N is an integer greater than 1. A set of N different interposers is provided such that an i-th interposer provides electrical connection between the first substrate and the second substrate with a rotational angle of (i?1)/N×2?. The first and second substrates are tested with each of the N different interposers therebetween. Once the rotational angle that provides the highest stacked chip yield is determined, the first and the second substrates can be bonded with an azimuthal rotation that provides the highest stacked chip yield.

Abstract: There is provided a test apparatus for testing a device under test, including: a plurality of test sections; and a first synchronization section and a second synchronization section that, for each of a plurality of domains that respectively include one or more of the plurality of test sections, synchronize the one or more test sections included in the domain, where each of the first synchronization section and the second synchronization section includes: a local collection section that collects, for each domain, synchronization requests from the test sections connected to the corresponding synchronization section; an exchange section that exchanges, for a discrete domain of that includes test sections connected to the first synchronization section and test sections connected to the second synchronization section, synchronization requests collected in the corresponding synchronization section with synchronization requests collected in the other synchronization section; a global collection section that collects

Abstract: Electrical circuit apparatus and methods including hermeticity testing structures for testing the hermeticity of the electrical circuit apparatus.

Abstract: Provided are a probe card including a first area group including a plurality of first areas, each including a plurality of probes for input pad and probes for output pad, the first areas being aligned in L rows by M columns (L, M: natural number); and a second area group including a plurality of second areas, each including a plurality of probes for input pad, the second areas being aligned in (L×N) rows by M columns (N: natural number); and the first area group and the second area group are continuously connected in a column direction according to the chip alignment, such that the first areas and the second areas are aligned in {L+(L×N)} rows by M columns.

Abstract: Wire bond pad and solder ball or controlled collapse chip connections C4 are combined on a planar surface of a an integrated circuit device to provide a die. Known good die (KGD) testing is optionally performed using wire bond connections or stress tolerant solder ball connections. The KGD testing is conducted after the integrated circuit dies are diced from a wafer. Solder ball or C4 array connections which withstand thermal stress are used to KGD test the die prior to final use of the wire bond pad connections to an end use device. Alternatively, wire bond pads are used to test the die while maintaining the solder ball or C4 array in a pristine condition for bonding to a final end product device. Both testing with the solder ball C4 array contacts and with the wire bond connections provides metallurgical connections for the KGD test. The solder ball or C4 array is connected to the wire bond pads and either connection can be used to burn-in test the die.