Abstract: A system and method are provided that enables a processor to undergo a functional test of its circuits prior to attachment to a semiconductor package and prior to use in a computing platform. The method of testing chips includes attaching a non-packaged semiconductor circuit to a test bed, loading computer instructions into a memory of the non-packaged semiconductor circuit, and operating the non-packaged semiconductor circuit in a test boot mode and executing the computer instructions in that mode. The operation logs one or more events of the execution of the instructions in the test boot mode and transmits the logs of the one or more events from the non-packaged semiconductor circuit via a joint test action group (JTAG) interface or a universal asynchronous receiver/transmitter (UART) interface.

Abstract: According to a certain embodiment, the test system includes a first test board, a test executable integrated circuit, and a first measuring apparatus. A device under test (DUT) is mounted on the first test board. The test executable integrated circuit is mounted on the first test board, and is configured to read firmware stored in the DUT in advance and to test the DUT. The first measuring apparatus instructs the test executable integrated circuit to start a test of the DUT. There are provided the test system, the test method, and the non-transitory computer readable medium, capable of reducing costs required for tests and also of shortening test time.

Abstract: A position detection and determination device and a position calibration device and method are provided. The position detection and determination device includes a standard positioning pin position limiting component configured to limit standard position information of a positioning pin of a load port of a silicon wafer pod; a positioning pin position detecting component configured to detect real-time position information of the positioning pin of the load port of the silicon wafer pod; and a determining module configured to obtain the standard position information and the real-time position information, and determine whether the position of the positioning pin of the load port of the silicon wafer pod is accurate or not according to the standard position information and the real-time position information.

Abstract: A sensor device for testing electrical connections using contactless fault detection is disclosed. The sensor device includes: a surface coil comprising a plurality of concentric loops disposed at a first region located away from the electrical connections. The concentric loops generate a first magnetic field passing through the electrical connections, and the first magnetic field is equivalent to that generated by a coaxial intermediate current loop adjacent to the electrical connections based on an excitation current in the surface coil. The sensor device further includes a sensor adapted to detect a second magnetic field at a second region located away from the electrical connections, wherein variations in the detected second magnetic field provide categories of performance of the electrical connections.

Abstract: An apparatus for the automated assembly of a probe head for testing electronic devices integrated on a semiconductor wafer, includes a support adapted to support at least two parallel guides, which are provided with a plurality of respective guides holes, and at least one holding means adapted to hold a contact probe to be housed in the guides holes, of the guides. Suitably, the support is a movable support adapted to be moved according to a preset trajectory between a first position, wherein the contact probe is held by the holding means at a predetermined position outside the guides holes, and a second position wherein the contact probe, which is held at the predetermined position, is housed in a set of guides holes that are substantially concentric to each other.

Abstract: An inspection jig includes contact terminals and a pitch conversion unit electrically connected to the contact terminals and configured to convert a first pitch between adjacent two of the contact terminals into a second pitch different from the first pitch. The contact terminals each include a tubular body that extends in an axial direction of the contact terminal and is electrically conductive, and a conductor that is electrically conductive and has a stick shape. The tubular body includes a spring portion that has a helical shape along a peripheral surface of the tubular body. The conductor includes an uninserted portion that protrudes from the tubular body toward a first side in the axial direction, and an inserted portion that is disposed in the tubular body and is fixed to a first axial end portion of the tubular body. The pitch conversion unit includes a board portion and a protruding portion.

Abstract: Apparatus and techniques for an integrated circuit (IC) package to automatically detect, through an input/out pin, external component parameters and parasitics. An example IC package generally includes a pin for coupling to a component external to the IC package, and at least one of a resistance detector, an inductance detector, or a capacitance detector coupled to the pin, and configured to detect at least one of a resistance, an inductance, or a capacitance, respectively, of a lumped parameter model for the component external to the IC package. The resistance detector, inductance detector, or capacitance detector may also be configured to detect parasitics associated with at least one of the component, the pin, or a connection between the component and the pin.

Abstract: Embodiments relate to a test method for testing an unpopulated printed circuit board. The method can involve the steps of: exposing the unpopulated printed circuit board to temperatures of a reflow soldering process in a first step; and testing the electrical connections of the unpopulated printed circuit board. Embodiments also relate to a test device and a method for producing populated printed circuit boards.

Abstract: Techniques and systems for enhanced adjustment of quantities and placement of decoupling capacitance on circuit boards for integrated circuits is provided herein. An example method includes iterating application of a load profile across different populations of decoupling capacitors on a circuit board for supply voltage domains of an integrated circuit device until a target transient performance is reached for the supply voltage domains. The load profile is applied onto electrical connections corresponding to the supply voltage domains for the integrated circuit device. The method also includes generating a capacitor population configuration for the circuit board based on a population of the decoupling capacitors that achieves the target transient performance.

Abstract: Embodiments are directed to probe structures, arrays, methods of using probes and arrays, and/or methods for making probes and/or arrays wherein the probes include at least one flat tensional spring segment.

Abstract: An automated test equipment for testing one or more DUTs comprises a test head and a DUT interface. The DUT interface comprises a plurality of blocks of spring-loaded pins, for example groups or fields of spring-loaded pins. For example, the DUT interface is configured for establishing an electronic signal path between the test head and a DUT board or load board, which holds the DUT or which provides a connection to the DUT. The automated test equipment is configured to allow for a variation of a distance between at least two blocks of spring-loaded pins.

Abstract: An automated test equipment for testing one or more DUTs comprises a test head and a DUT interface. The DUT interface comprises a plurality of blocks of spring-loaded pins, for example groups or fields of spring-loaded pins. For example, the DUT interface is configured for establishing an electronic signal path between the test head and a DUT board or load board, which holds the DUT or which provides a connection to the DUT. The automated test equipment is configured to allow for a variation of a distance between at least two blocks of spring-loaded pins.

Abstract: A system and method for performing time-dependent reliability prediction of a printed circuit board (PCB) embedded in a sensor that monitors the health (viz., performance) of operating equipment subject to different environmental stressors. The method includes developing a digital twin (DT) of the physical PCB, generating sensor data, transmitting the sensor data, and receiving sensor data and historical conditional data by the twinning module, wherein the historical condition data includes known failure data of one or more electronic components of the circuit board based on an internal condition or and external condition. The method further includes embedded physics-based reliability models informed by inputs from the sensor data and the historical conditional data, generating a real-time failure prediction signal based on the physics-based reliability models, and reporting the real-time failure prediction signal.

Abstract: A device includes a semiconductor fin, an isolation structure, a gate structure, source/drain structures, a sensing contact, a sensing pad structure, and a reading contact. The semiconductor fin includes a channel region and source/drain regions on opposite sides of the channel region. The isolation structure laterally surrounds the semiconductor fin. The gate structure is over the channel region of the semiconductor fin. The source/drain structures are respectively over the source/drain regions of the semiconductor fin. The sensing contact is directly on the isolation structure and adjacent to the gate structure. The sensing pad structure is connected to the sensing contact. The reading contact is directly on the isolation structure and adjacent to the gate structure.

Abstract: A memory module including: a first printed circuit board; a first socket and a second socket; and a daisy chain pattern formed in a first region of the first printed circuit board and connected to the first socket and the second socket, wherein an electrical signal on the daisy chain pattern is transferred to a host device when the first socket and the second socket are connected to the host device.

Abstract: A method for electrically contacting components in a semiconductor wafer includes providing a flexible board comprising a first main surface on which a plurality of conductor tracks are arranged, positioning the board with respect to a semiconductor wafer such that the first main surface of the board faces the semiconductor wafer, the board is bent and pressed onto the semiconductor wafer in such a way that contact elements of a plurality of components arranged in a row in the semiconductor wafer come into contact with the conductor tracks, and electrical signals are applied to the components through the conductor tracks.

Abstract: A method for obtaining board parameters of a printed circuit board, including the following steps: obtaining parameter information of a stripline on the printed circuit board; obtaining physical parameters of the stripline based on the parameter information of the stripline and a predetermined electromagnetic simulation application; calculating required board parameters of the printed circuit board based on the parameter information and the physical parameters of the stripline. In the present disclosure, the physical parameters of the stripline are obtained based on the physical nature of the stripline on the printed circuit board, and there is no need for fitting or adopting a hypothetical model in order to obtain board parameters corresponding to each frequency point of the stripline; the present disclosure is simple and straightforward during operation, and the obtained board parameters of the printed circuit board are highly accurate.

Abstract: An apparatus provides power for computer devices, such as servers, facilitating their testing outside of the typical server rack. A platform of supports the computer device while providing for a power supply unit beneath the platform to be connected to the device. The location of the power supply beneath the platform decreases the combined footprint of the apparatus and device under test. The power supply unit may be configured to connect to standard voltages, allowing the computer device to be tested where connection to rack-level voltage is not convenient.

Abstract: It is an object of the present invention to provide a printed circuit board capable of accurately detecting disconnections of circuit patterns with an automatic circuit pattern inspecting device even when positions of mounting lands are slightly deviated from normal positions due to manufacturing errors. For solving this object, the printed circuit board of the present invention is provided with a first mounting land 4a and a second mounting land 4b, and a first circuit pattern 6a and a second circuit pattern 6b on a surface thereof, wherein a first electric checker land 10a and a second checker land 10b which are electrically connected with the first mounting land 4a and the second mounting land 4b are provided on a surface of a wiring board 2.

Abstract: A method of inspecting a printed wiring board includes preparing a printed wiring board having product and inspection regions such that the board has inner-layer lands in the regions, forming vias on the inner-layer lands in the regions, forming outer peripheral part(s) in the wiring board such that the outer peripheral part(s) expose outer peripheral portion(s) of the inner-layer land in the inspection region, determining a center coordinate of the inner-layer land in the inspection region based on a position of the outer peripheral part(s), determining a center coordinate of the via(s) in the inspection region based on a shape of the via(s) in the inspection region, determining a misalignment amount based on a distance between the center coordinate of the inner-layer land and the center coordinate of the via(s) in the inspection region, and determining alignment accuracy between the via and the inner-layer land based on the misalignment amount.

Abstract: The probe assembly operates with a circuit board test apparatus and includes a main test probe and a secondary test probes. The probe assembly is capable of moving in X, Y and Z directions relative to a circuit board being tested (UUT). The two test probes are movable linearly relative to each other and rotatable together so as to accurately locate the two probes on selected pins on the UUT, for receiving signals from the selected pins, The received signals are transmitted to a display apparatus.

Abstract: A system on chip (SoC) for testing a component in a system during runtime includes a plurality of functional components; a system bus for allowing the plurality of functional components to communicate with each other; one or more wrappers, each connected to one of the plurality of functional components; and an in-system component tester (ICT). The ICT monitors, via the wrappers, states of the functional components; selects, as a component under test (CUT), at least one functional component in an idle state; tests, via the wrappers, the selected at least one functional component; interrupts the testing step with respect to the selected at least one functional component, based on a detection of a collision with an access from the system bus to the selected at least one functional component; and allows a connection of the at least one functional component to the system bus, based on the interrupting step.

Abstract: A lossless compression method for a test vector has following steps: S01: converting the test vector into a data stream with A rows and B columns, the data stream is expressed in binary; S02: compressing the data stream a column by a column sequentially to form compressed words and uncompressed words corresponding to test datum of each of the B columns; a compression method for the test datum of each of the B columns comprises: setting a window with a width of 1 bit and a depth of M rows, and sliding the window down a row by a row from top of test datum of a column, and forming the compressed words and the uncompressed words corresponding to the test datum of each of the B columns; S03: converging the compressed datum of the test datum of each of the B columns to form a compressed data stream.

Abstract: A reference via in a set of plated vias on a printed circuit board is located. A reference lead is applied to the reference via. A test via in the set of plated vias is located. A test lead is applied to the test via. An electrical conductance between the reference via and the test via is measured. A property of a core layer of the printed circuit board is identified based on the electrical conductance.

Abstract: According to one embodiment, a method includes: supplying electrical energy to a first path by an inspection circuit with a short circuit between two first terminals through a first probe; and detecting an electrical characteristic on the first path by the inspection circuit. The two first terminals are included in a plurality of second terminals included in a flexible printed circuit board. The flexible printed circuit board includes: an electronic component including the inspection circuit and a plurality of third terminals; the plurality of second terminals; and a plurality of first wired lines connecting the plurality of second terminals and the plurality of third terminals. The first path is formed by: the two first terminals; two second wired lines connected to the two first terminals among the plurality of first wired lines; and two fourth terminals connected to the two second wired lines among the plurality of third terminals.

Abstract: A resistance measuring device includes: a first jig; a plurality of first contacts; a second jig; a plurality of second contacts; a resistance measuring unit that supplies a current between a first contact and a second contact, which correspond to each other, detects a voltage between a first contact and a second contact, and calculates a resistance value of an object to be measured based on a relationship between a value of the supplied current and a value of the detected voltage; first wirings connecting the resistance measuring unit and each of the first contacts, for the first contacts, respectively; and second wirings connecting the resistance measuring unit and each of the second contacts while passing from the resistance measuring unit through the first jig, for the second contacts, respectively.

Abstract: A method for processing requests, that includes receiving, by a volatile storage component, a request from a user space application, writing the request into a shared memory partition, generating instructions associated with the request, and processing the instructions, where the request is a data request and where generating the instructions associated with the request includes detecting, by the volatile storage component, the data request in the shared memory partition, where the data request is written in a data queue.

Abstract: A contact element system has a plurality of pin-type or needle-type and electrically conductive contact elements of equal length, which each have two end regions for electrically contacting contact positions and each have an intermediate region under longitudinal loading, overcoming their bending rigidity, and are designed with lamellar sections in the intermediate region such that they have at least two strips which are substantially parallel to each other and run at a distance from one another. At least two of the contact elements have different cross sectional surfaces and differently formed strips in the intermediate region, wherein the forms of the strips are chosen such that the contact elements have the same or approximately the same bending rigidity.

Abstract: An automated test equipment for testing one or more DUTs comprises a test head and a DUT interface. The DUT interface comprises a plurality of blocks of spring-loaded pins, for example groups or fields of spring-loaded pins. For example, the DUT interface is configured for establishing an electronic signal path between the test head and a DUT board or load board, which holds the DUT or which provides a connection to the DUT. The automated test equipment is configured to allow for a variation of a distance between at least two blocks of spring-loaded pins.

Abstract: A test system is provided. The system includes a first test apparatus and a second test apparatus. A device power supply of the first test apparatus (ATE) is electrically connected with a device under test (DUT) through a driving branch (F) and a detecting branch (S), the driving branch (F) being configured to provide an original driving current to the DUT b the device power supply during testing, and the detecting branch (S) being configured to detect an effective driving current reaching the DUT. The second test apparatus includes a first voltage drop branch, the first voltage drop branch is connected to the detecting branch (S), and a voltage drop detected by the driving branch (F) is used to determine an effectiveness of an electrical connection formed between the driving branch and the device under test, and an electrical connection formed between the detecting branch (S) and the DUT.

Abstract: An ultrasound device comprises a transducer arrangement and an acoustically transmissive window over said arrangement, said window comprising an elastomer layer having conductive particles dispersed in the elastomer, the elastomer layer having a pressure-sensitive conductivity. An electroactive material actuator is provided for biasing the transducer arrangement towards the transmissive window. The electroactive material actuator is controlled in dependence on a measured pressure-sensitive conductivity. In this way, a feedback system is provided for controlling a contact pressure. The device can be implemented with low cost and with low power consumption.

Abstract: An illustrative parametric testing system includes a motherboard disposable over a wafer prober chuck. First electrical connectors are disposed on and electrically connected to the motherboard. At least one parametric testing cards is disposable in physical and electrical contact with an associated one of the first electrical connectors proximal a pad of a device under test. The parametric testing card includes electronic circuitry configured to receive a digital signal indicative of test plan instructions, generate an analog stimulus signal for a device under test responsive to the test plan instructions, perform an analog measurement of a stimulated device under test, and transmit a digital signal indicative of the measurement of a device under test. The system includes an interface to a computing system. The interface is electrically connectable to the motherboard. The system includes at least one power supply electrically connectable to the motherboard.

Abstract: A customer premise equipment (CPE) device may be functionally verified using a universal platform to simulate operating conditions of an environment in which the CPE is intended to operate. Functional verification may be performed for an operational use of a CPE device in an environment similar to that used by customers of a service provider. Functional verification may be applied to a variety of devices using a verification platform that can support various types of CPE devices, various models of CPE devices, and various operational configurations used by an operator.

Abstract: A foldable display apparatus, a method of manufacturing the same, and a controlling method of the same are disclosed. The foldable display apparatus includes a substrate including a metal thin film and an insulating layer provided on the metal thin film, an organic light-emitting unit formed on the substrate and emitting light in an direction away from the substrate, and a thin film encapsulating layer for encapsulating the organic light-emitting unit. The foldable display apparatus may be folded in a direction such that the metal thin film is exposed.

Abstract: An appliance with automatic sensing of printed circuit board (PCB) trace integrity and associated methods of sensing are provided. The appliance may include a controller operative to control operation of the appliance, a load in operative communication with the controller, and a PCB. The PCB may include a first trace supplying AC power to the load, a second trace supplying a return path for the AC power, a third trace supplying an alternate return path for the AC power, and current sensing circuitry. The current sensing circuitry may be configured to sense leakage current between the first trace and the third trace, with the leakage current being indicative of declining trace integrity of the PCB.

Abstract: Illustrative embodiments disclosed herein pertain to a testing apparatus for performing in-circuit tests upon a printed circuit board assembly. Each of these tests may require the use of a set of probes arranged in a customized layout. This is traditionally accomplished by using a set of predefined probe plates, some or all of which may include probes that are either redundant or duplicated amongst the various probe plates, thereby introducing an undesirable cost penalty. A testing apparatus in accordance with the disclosure incorporates a configurable probe fixture that includes a docking plate configured to support a first set of probe modules for carrying out a first test upon a printed circuit board assembly. Some or all of the probe modules can then be selectively removed or replaced by other probe modules for reconfiguring the testing apparatus to carry out other tests upon the printed circuit board assembly.

Abstract: The disclosed embodiments provide a system that detects counterfeit electronic components in a target device, which is part of an electrical generation and distribution system. During operation, the system obtains target EMI signals, which were gathered by monitoring target electromagnetic interference (EMI) emissions generated by the target device using one or more target antennas positioned in proximity to the target device. Next, the system generates a target EMI fingerprint for the target device from the target EMI signals. Finally, the system compares the target EMI fingerprint against a reference EMI fingerprint for the target device to determine whether the target device contains one or more counterfeit electronic components.

Abstract: A system, computer program product, and computer-executable method for detecting defects in an interconnect, the system, computer program product, and computer-executable method comprising receiving a data measurement relating to the interconnect, analyzing the data measurement, and determining whether the interconnect includes a defect based on the analyzing of the data measurement isolated from the impedance of the interconnect.

Abstract: A foldable display apparatus, a method of manufacturing the same, and a controlling method of the same are disclosed. The foldable display apparatus includes a substrate including a metal thin film and an insulating layer provided on the metal thin film, an organic light-emitting unit formed on the substrate and emitting light in an direction away from the substrate, and a thin film encapsulating layer for encapsulating the organic light-emitting unit. The foldable display apparatus may be folded in a direction such that the metal thin film is exposed.

Abstract: Embodiments of the present invention disclose a method, computer program product, and system for imaging radio and microwave electromagnetic radiation using a two-dimensional sensor array. A computing system receives a readout signal from one or more of a plurality of frequency sensors, arranged in a two-dimensional array, that have the ability to detect an image of focused radio and microwave frequency radiation. The computing system maps the readout signal of each of the plurality of sensors to a location corresponding to the physical location of the sensor on the two-dimensional array. The computing system converts the readout signal into a computer readable image.

Abstract: Equipment including at least one plug-in unit (102) and a body device (101) for receiving the plug-in unit is presented. The equipment includes a circuit (124) including a test signal generator for supplying a test signal to a measurement circuit including galvanic contacts provided by electrical connectors between the body device and a plug-in unit so that the test signal belongs at least partly to a frequency band used in data transfer between the plug-in unit and the body device. The equipment includes a monitoring circuit for generating a signal indicative of a difference between a quantity responsive to the test signal and a reference. As the test signal belongs at least partly to the frequency band used in the data transfer, the quality of the galvanic contacts between the body device and the plug-in unit can be monitored concerning the behavior on the data transfer frequency band.

Abstract: An imaging apparatus includes an imaging unit that is provided with an image pickup device and a fixed pattern outputting section that outputs a fixed pattern set in advance and includes a control unit and a path. The control unit is electrically connected to the imaging unit and receives an image acquired by the image pickup device and a fixed pattern outputted from the fixed pattern outputting means. The path electrically connects the imaging unit and the control unit, and electrically transmits an image and a fixed pattern from the imaging unit to the control unit. The control unit controls, depending on the image, an application which requires the image as one of inputs to the application. Further, the control unit compares a specific pattern prepared in advance according to the fixed pattern, with the fixed pattern, to determine the occurrence of an anomaly in the electrical connection of the path.

Abstract: An automatic test equipment includes a test apparatus, a first control device, a first assisting device, and a second control device. The test apparatus is applied for testing a first object, wherein the test apparatus has a first cover. The first control device has an activating device. The first assisting device is electrically connected to the first control device. The second control device is electrically connected to the first control device and the test apparatus. When the activating device is activated, the first control device controls the first assisting device to lower the first cover and then the first control device transmits a first control signal to the second control device for allowing the test apparatus to test the first object.

Abstract: The invention relates to a printed circuit arrangement comprising a printed circuit board having a corrosion test circuit comprising at least two conductive pads which are located proximate to each other in a measuring area, the arrangement further comprising a measuring device, characterized in that one pad is an excitation pad, being connected to an excitation signal source, and the other pad is a response pad, whereby the measuring device is connected at least to the response pad. This arrangement allows the measurement of the corrosion of a printed circuit board including short circuits and line cuts.

Abstract: An adjustable resistor device includes a first pin, a second pin, a resistance-adjusting branch circuit, and a resistance display circuit. The first and second pins are configured to connect to an external circuit. The resistance-adjusting branch circuit is connected between the first pin and the second pin, and provides resistors for testing the external circuit. The resistance display circuit displays a resistance of the resistance display circuit.

Abstract: The present disclosure provides a testing apparatus for executing a test program, to perform a first test on a circuit component on a circuit board and a second test on the circuit board. The testing apparatus includes a first module, a second module, and a signal transmission line that connects the two. The first module includes a control unit, a signal generation unit, a signal processing unit, a signal expansion unit, and a power supply unit. The control unit generates a first control signal or a second control signal. The signal generation unit generates a current signal or a voltage signal. The signal processing unit generates a numerical signal. The signal expansion unit generates a second data signal. The power supply unit generates a working voltage. The second module includes a test address assignment unit that assigns an address and a signal isolation unit that performs noise immunization process.

Abstract: A test system is provided. A printed circuit board (PCB) includes a plurality of traces and at least one test point. A central processing unit (CPU) socket including a plurality of first pins and a memory module slot including a plurality of second pins are disposed on the PCB. Each of the second pins is coupled to the corresponding first pin of the CPU socket via the corresponding trace. A CPU interposer board is inserted into the CPU socket, and a memory interposer board is inserted into the memory module slot. The traces form a test loop via the CPU interposer board and the memory interposer board. When an automatic test equipment (ATE) provides a test signal to the test loop via the test point, the ATE determines whether the test loop is normal according to a reflectometry result of the test signal.

Abstract: First and second measurement probes come into contact with first and second electrode pads, respectively, and third and fourth measurement probes come into contact with the first and second electrode pads, respectively. A current flows in a current path including the first and second electrode pads and a plurality of lines through the first and second measurement probes. A value of the current in the current path is measured, and a value of a voltage between the third and fourth measurement probes is measured. Conductivity between the first and second electrode pads is inspected based on the measured value of the current and the measured value of the voltage.

Abstract: A circuit board includes a main part on which a processor is mounted, a cut part to be cut off from the main part at a cut section before the board is reused, and a conductor pattern wired through the cut part via the cut section and to be cut off into a plurality of patterns at the cut section as the cut part is cut off. The processor detects a difference in signal level between a level of a signal output from the conductor pattern before the cut part is cut off, and a level of the signal output from the conductor pattern after the cut part is cut off, to determine a number of times the board is reused.

Abstract: Methods and apparatus are disclosed to simultaneously, wirelessly test semiconductor components formed on a semiconductor wafer. The semiconductor components transmit respective outcomes of a self-contained testing operation to wireless automatic test equipment via a common communication channel. Multiple receiving antennas observe the outcomes from multiple directions in three dimensional space. The wireless automatic test equipment determines whether one or more of the semiconductor components operate as expected and, optionally, may use properties of the three dimensional space to determine a location of one or more of the semiconductor components. The wireless testing equipment may additionally determine performance of the semiconductor components by detecting infrared energy emitted, transmitted, and/or reflected by the semiconductor wafer before, during, and/or after a self-contained testing operation.