Abstract: An integrated circuit includes a functional core configured to execute functional logic instructions; a functional memory device coupled to the functional core; a safety core configured to execute safety check logic instructions; a monitored address memory device coupled to the functional core and the safety core, the monitored address memory device configured to store memory addresses to be monitored; and a first safety memory device coupled to the functional memory device and the safety core. When a value in one of the monitored memory addresses changes, the changed value of the one of the monitored memory addresses is stored in the functional memory device and in the first safety memory device. The safety core performs a safety check on the changed value of the one of the monitored memory addresses stored in the first safety memory device.

Abstract: A data storage system for use in a high radiation environment includes an array of storage drives. Each storage drive includes a non-radiation-hardened drive controller, a non-radiation-hardened, non-volatile, storage medium, and a non-radiation-hardened volatile memory. The system includes a radiation-hardened storage controller coupled to the array. The radiation-hardened storage controller provides failure-resistant data redundancy among the storage drives of the array and provides host access to the array.

Abstract: The present invention provides an output buffer including a first transistor, a second transistor and a pad-tracking circuit is disclosed. The first transistor is coupled between a supply voltage and an output node, wherein the output node is coupled to a pad. The second transistor is coupled between the output node and a reference voltage. The pad-tracking circuit is coupled to the control circuit and the first transistor, and is configured to generate a gate control signal to a gate electrode of the first transistor. The output buffer is selectively operated in an input mode and a fail-safe mode, and when the output buffer switches between the input mode and the fail-safe mode and the supply voltage of the first transistor ramps up or ramps down, the pad-tracking circuit generates the gate control signal to the gate electrode of the first transistor according to the voltage of the pad.

Abstract: An integrated circuit includes a functional core configured to execute functional logic instructions; a functional memory device coupled to the functional core; a safety core configured to execute safety check logic instructions; a monitored address memory device coupled to the functional core and the safety core, the monitored address memory device configured to store memory addresses to be monitored; and a first safety memory device coupled to the functional memory device and the safety core. When a value in one of the monitored memory addresses changes, the changed value of the one of the monitored memory addresses is stored in the functional memory device and in the first safety memory device. The safety core performs a safety check on the changed value of the one of the monitored memory addresses stored in the first safety memory device.

Abstract: A method of measuring a clock signal includes launching an edge of a timing signal on a first edge of the clock signal, outputting an edge of a capture signal on a second edge of the clock signal, receiving the edge of the timing signal and the edge of the capture signal at a time-to-digital converter (TDC), and measuring a time delay using the TDC, wherein the time delay is between a time the edge of the timing signal is received at the TDC and a time the edge of the capture signal is received at the TDC.

Abstract: Disclosed is a linear voltage regulator with an input terminal, an output terminal, a pass device electrically connected to the input terminal and the output terminal, and an error amplifier that controls the output voltage at the output terminal by controlling the voltage drop across the pass device. The disclosed linear voltage regulator includes a light emitting section electrically connected in series with the pass device between the input terminal and the output terminal and a photovoltaic section, electrically connected to the output terminal, that receives photons emitted by the light emitting section and outputs a current to output terminal. The disclosed linear voltage regulator is more efficient than conventional linear voltage regulators because, unlike in those convention linear voltage regulators, the voltage drop across the pass device is only a fraction of the total potential difference between the input terminal and the output terminal.

Abstract: Logic gates are made from first and second resistive elements connected together to form a voltage divider. One or both of the resistive elements is a unipolar memristor. OR and NOT gates may be constructed to make a digital logic system.

Abstract: An electronic device for detecting a load type is described. The electronic device includes zero-cross circuitry configured to detect a line voltage zero cross and includes switching circuitry configured to perform switching based on the line voltage zero cross to supply a load voltage. The electronic device further includes load voltage measuring circuitry configured to measure the load voltage. The electronic device additionally includes a processor configured to determine a load type based on the load voltage measurement and configured to control the switching circuitry to drive the load based on the load type. An electronic device for detecting load coupling is also described. The electronic device includes load voltage measuring circuitry configured to measure load voltage without activating the load voltage. The electronic device also includes a processor configured to determine whether a load is coupled based on the load voltage measurement.

Abstract: Disclosed herein is a circuit including first and second input circuits. The first input circuit is configured to receive first and second logic signals and to source current to first and second control nodes if at least one of the first and second logic signals is at a logic low. The second input circuit is configured to receive the first and second logic signals and to sink current from the first and second control nodes if at least one of the first and second logic signals is at a logic high. A first output circuit is configured to source current to an output node when current is sunk from the first control node. A second output circuit is configured to sink current from the output node when current is sourced to the second control node. A latch is coupled to the output node.

Abstract: One general aspect includes a method for electric overcurrent protection, the method including: calculating, via a controller, a system electric current sum; receiving, via the controller, audio production electric current data; comparing, via the controller, the system electric current sum and audio production electric current data; and when the audio production electric current data exceeds the system electric current sum, invoke a fail-soft action configured to prevent electric overcurrent from being delivered to an audio speaker.

Abstract: A semiconductor apparatus can block the voltage from the power source when the voltage from the power source reaches an excessive level, without requiring a larger chip size. Provided is a semiconductor apparatus including a power semiconductor element a gate of which is controlled in response to a control signal, an overvoltage detector configured to detect that a voltage at a collector terminal of the power semiconductor element reaches an overvoltage level, and a block unit configured to, in response to the detection of the overvoltage level, control the gate of the power semiconductor element to transition to an off-voltage. The semiconductor apparatus may further include a reset unit configured to, in response to that the control signal is input that turns on the power semiconductor element, output a reset signal for a predetermined period of time.

Abstract: Logic gates are made from first and second resistive elements connected together to form a voltage divider. One or both of the resistive elements is a unipolar memristor. OR and NOT gates may be constructed to make a digital logic system.

Abstract: A control system includes an arithmetic device configured of an A system arithmetic unit including a data dividing unit, a B system arithmetic unit including a data dividing unit, and an A system communication control unit including a data combining unit and a collation unit, wherein the A system arithmetic unit and the B system arithmetic unit have a duplex configuration, the A system arithmetic unit and the B system arithmetic unit are separated by a gap, a frame output from the A system arithmetic unit is transmitted to a B system communication control unit through the A system communication control unit and an interface element, and a frame output from the B system arithmetic unit is transmitted to the A system communication control unit through the B system communication control unit and an interface element.

Abstract: A new lower-power gate design for memristor-based Boolean operations. Such a design offers a uniform cell that is configurable to perform all Boolean operations, including the XOR operation. For example, a circuit to perform the AND operation utilizes a first memristor and a second memristor connected in series. The circuit further includes a switch, where a node of the second memristor is connected to the switch. Furthermore, the circuit includes a third memristor connected to the switch in series, where the switch and the third memristor are connected in parallel to the first and second memristors. Additionally, the first voltage source is connected to the first memristor via a first resistor. In addition, a second voltage source is connected in series to the switch and the third memristor. In such a design, the delay is reduced to a single step and the area is reduced to at most 3 memristors.

Abstract: There are provided a switch driving device and a switch driving method capable of preventing a self-turn-on phenomenon. The switch driving device includes: a first signal output unit configured to output a pulsed first driving signal from a first output terminal thereof; a second signal output unit configured to output a pulsed second driving signal to a control terminal of a switching element from a second output terminal thereof; and a negative power supply generating unit configured to generate a negative voltage relative to a ground voltage and bias a low level of the second driving signal toward a negative side by the negative voltage. The negative power supply generating unit includes: a first capacitor configured to store charge by the first driving signal; and a second capacitor configured to generate the negative voltage across terminals thereof by the transfer of the charge from the first capacitor.

Abstract: A photocoupler isolation switch circuit is disclosed. The circuit includes a power chip and a voltage driving chip including a photocoupler device having a light emitting device and a photosensitive device. A first output terminal of the power chip connects to a first terminal of the light emitting device, and a second terminal of the light emitting device connects to ground; a second output terminal of the power chip connects to a first terminal of the photosensitive device and outputs a driving voltage, a second terminal of the photosensitive device connects to an output terminal of the photocoupler device; the photocoupler device controls a working status of the light emitting device according to a control voltage, the photosensitive device is turned on or off according to the working status; the driving voltage is outputted through the output terminal of the photocoupler device when the light emitting device is turned on.

Abstract: An apparatus includes a processing unit including a configuration memory and self-scrubber logic coupled to read the configuration memory to detect compromised data stored in the configuration memory. The apparatus also includes a watchdog unit external to the processing unit and coupled to the self-scrubber logic to detect a failure in the self-scrubber logic. The watchdog unit is coupled to the processing unit to selectively reset the processing unit in response to detecting the failure in the self-scrubber logic. The apparatus also includes an external memory external to the processing unit and coupled to send configuration data to the configuration memory in response to a data feed signal outputted by the self-scrubber logic.

Abstract: Disclosed is a method wherein selective voltage binning and leakage power screening of integrated circuit (IC) chips are performed. Additionally, pre-test power-optimized bin reassignments are made on a chip-by-chip basis. Specifically, a leakage power measurement of an IC chip selected from a voltage bin can is compared to a bin-specific leakage power screen value of the next slower voltage bin. If the leakage power measurement is higher, the IC chip will be left in the voltage bin to which it is currently assigned. If the leakage power measurement is lower, the IC chip will be reassigned to that next slower voltage bin. These processes can be iteratively repeated until no slower voltage bins are available or the IC chip cannot be reassigned. IC chips can subsequently be tested according to testing parameters, including the minimum test voltages, associated with the voltage bins to which they are finally assigned.

Abstract: A universal error-correction circuit with fault-tolerant nature includes an error-correction unit with fault-tolerant nature implemented by a logic gate, where digital input signals of the error-correction unit with fault-tolerant nature are separately I0, I1 . . . , I2k-1, and I2k, digital output signals of the error-correction unit with fault-tolerant nature are separately O0, O1, . . . , Ok-2, and Ok-1, and the digital input signals and the digital output signals belong to a set {0,1}, where k is a positive integer. The error-correction unit with fault-tolerant nature is configured to, when k=1, set O0=I0 if I0=I1, and O0=I2 otherwise; and when k>1, set Ok-1=I2k-1 if Ok-2=I2k-1, and Ok-1=I2k otherwise. Because a logical relationship between input and output is uniquely certain, the error-correction circuit with fault-tolerant nature may be implemented only by a logic gate.

Abstract: A computing unit computes a computed value for input data. A comparing unit compares the computed value of the computing unit with a computed value of another node which is included in an input/output set. An output unit outputs the computed value as output data of a node itself when the result of the comparison by the comparing unit shows that the computed value matches either one of computed values. When the computed value does not match any one of the computed values of other nodes, a transferring unit adds the computed value of the node itself to the input/output set, and transfers the input/output set to another node.

Abstract: This disclosure relates generally to radiation hardened digital circuits. In one embodiment, a radiation hardened digital circuit includes a delay network and a first Muller C element. The delay network is configured to generate a first delayed clock signal from a global clock signal such that that the first delayed clock signal is delayed with respect to the global clock signal. The first Muller C element is configured to generate a first clock input signal and set the first clock input signal to one of a set of clock states in response to the first delayed clock signal and the global clock signal each being provided in a same one of the set of clock states and is configured to hold the first clock input signal otherwise. Thus, a radiation strike is prevented from causing a soft error in the first clock input signal.

Abstract: In some embodiments, an equipment unit has a set of visual indicators, a power switch, and a set of compute components. The power switch receives a signal representing a status such that when the status is in a first mode, the power switch provides power to the set of visual indicators and when the status is in a second mode the power switch does not provide power to the set of visual indicators. The compute components are configured to receive power when the power switch does not provide power to the set of visual indicators.

Abstract: An integrated circuit includes a latch block suitable for storing a signal through four or more even-numbered coupling lines inverted and driven alternately with each other, wherein the coupling lines are divided into two or more coupling line groups each including coupling lines inverted and driven to the same logic level, and a charge buffer block coupled between two or more coupling lines included in one of the coupling line groups and suitable for slowing down a charge movement speed therebetween.

Abstract: A power control device may include a first power-supply voltage source configured to generate a first power-supply voltage, and a second power-supply voltage source configured to generate a second power-supply voltage having a voltage level different from that of the first power-supply voltage. The power control device may include a power driver configured to provide an internal power source in response to the second power-supply voltage, irrespective of the first power-supply voltage source and the second power-supply voltage source, during an initial power-up period.

Abstract: A safety-related control unit for controlling an automated installation in accordance with an application program containing control instructions. The safety-related control unit has first and second processors for executing at least some of the control instructions by processing a plurality of first and second program variables, respectively. The first processor also determines a first test value for at least one of the first program variables in accordance with an instantaneous value present for this first program variable at a first defined instance of time. The second processor determines a second test value for the at least one of the first program variables. The second test value corresponds to the first test value. The safety-related control unit also has a data memory for storing the instantaneous value, the first test value and the second test value in order to facilitate a quick restart of the control unit after an unexpected interrupt.

Abstract: A termination network circuit for a differential signal transmitter comprises a plurality of n resistance elements and a plurality of differential signal drivers. A first end of each of the resistance elements is coupled at a common node, where n is an integer value and is the number of conductors used to transmit a plurality of differential signals. Each differential signal driver may include a positive terminal driver and a negative terminal driver. The positive terminal driver is coupled to a second end of a first resistance element while the negative terminal driver is coupled to a second end of a second resistance element. The positive terminal driver and the negative terminal driver are separately and independently switchable to provide a current having a magnitude and direction. During a transmission cycle each of the resistance elements has a current of a different magnitude and/or direction than the other resistance elements.

Abstract: A system for controlling gate power includes a metal oxide semiconductor field effect transistor (MOSFET) configured to supply power to a load according to a gate control voltage applied to a gate of the MOSFET. The system includes a gate control circuit configured to turn on and off the gate control voltage supplied to the gate of the MOSFET. The system also includes a ramping circuit configured to perform at least one of ramping up a voltage applied to the gate of the MOSFET based on the gate control circuit turning on power to the gate of the MOSFET and ramping down the voltage applied to the gate of the MOSFET based on the gate control circuit turning off power to the gate of the MOSFET.

Abstract: This disclosure relates generally to sequential state elements (SSEs). More specifically, embodiments of flip-flops are disclosed, along with computerized methods and systems of designing the same. In one embodiment, the flip-flop includes a substrate and subcircuits that are formed on the substrate. The subcircuits provide subfunctions, wherein each of the subcircuits provides at least one of the subfunctions. More specifically, the subfunctions are provided in a sequential logical order by the subcircuits so that the flip-flop provides a flip-flop function. However, the subcircuits are interleaved out of the sequential logical order with respect to a corresponding subfunction provided by each of the subcircuits along a vector defined by the substrate. In this manner, interleaving the subcircuits along the vector of the substrate can provide separation between charge collection nodes without requiring increases in size. Thus, the flip-flop can be more compact and less expensive to manufacture.

Abstract: A system for regulating semiconductor devices may include a current regulator configured to regulate one or more currents provided to an insulated gate bipolar transistor (IGBT). The current regulator may regulate the currents by generating a current profile based at least in part on a collector voltage value associated with the IGBT, a rate of collector voltage change value associated with the IGBT, or any combination thereof. The current profile may include one or more current values to be provided to a gate of the IGBT such that the current values are configured to limit the rate of collector voltage change to a first value. The current regulator may then send the one or more current values to a current source configured to supply the gate of the IGBT with one or more currents that correspond to the one or more current values.

Abstract: A multi-chip package may include first and second integrated circuit dies that are each partitioned into multiple logic regions. The logic regions of the first and second dies may be coupled via interconnects. Each integrated circuit die may include at least one spare logic region. Multiple logic groups may be formed with each logic group including logic regions from the first and second integrated circuit dies and the interconnects that couple those logic regions. The logic groups may be evaluated to identify defective logic groups. In response to identifying a defective logic group, the defective logic group may be repaired by configuring the first and second integrated circuit dies to stop using the defective logic group and to use a spare logic group. The spare logic group may include spare logic regions of the first and second dies that are coupled by spare logic region interconnects.

Abstract: In some embodiments, provided is a processor chip including self deactivation logic to deactivate the processor chip after a threshold of qualified events have been monitored.

Abstract: An input/output (IO) circuit powered by an input/output (IO) supply voltage. The IO circuit includes a supply detector cell that detects a core supply voltage and generates a supply detect signal. A driver circuit is connected to a PAD and the driver circuit receives the supply detect signal. A failsafe circuit receives a PAD voltage. The failsafe circuit and the supply detector cell controls a leakage current from the PAD based on the IO supply voltage and the PAD voltage.

Abstract: An input/output (IO) circuit powered by an input/output (IO) supply voltage. The IO circuit includes a supply detector cell that detects a core supply voltage and generates a supply detect signal. A driver circuit is connected to a PAD and the driver circuit receives the supply detect signal. A failsafe circuit receives a PAD voltage. The failsafe circuit and the supply detector cell controls a leakage current from the PAD based on the IO supply voltage and the PAD voltage.

Abstract: A pipelined processor including a combinational logic of several stages, a voltage regulator, a counter, a comparator, and a plurality of stage registers. Each stage register is disposed between two adjacent stages of the combinational logic. The stage register includes a flip-flop, a latch, an XOR gate, and a MUX module. When the high level of a register clock is coming, the flip-flop latches first data at the rising edge, and the latch receives second data during the high level. The data latched by the flip-flop and the latch respectively are compared by the XOR gate. If they are same, the output Error of the XOR gate is low level, and the output of the flip-flop is delivered to the next stage. Otherwise, the output Error of the XOR gate is high level, and the output of the latch is delivered to the next stage.

Abstract: Methods and circuits are disclosed for backing up the value of a bi-stable circuit included in a set of programmable logic circuits of a programmable IC. The programmable logic circuits are configured to implement logic circuits having functions based on data values stored in a used portion of a plurality of configuration memory cells. The programmable IC includes a backup control circuit configured to back up and restore the value of the bi-stable circuit. In response to a first signal, a first data value stored by the bi-stable circuit is retrieved and stored in a first one of the plurality of configuration memory cells that is unused in implementing the logic circuits. In response to a second signal, the first data value is retrieved from the first one of the plurality of configuration memory cells and stored in the bi-stable circuit.

Abstract: In one general aspect, a data collection system for a circuit under test implemented as an integrated circuit or using a programmable logic device is disclosed. It comprises a configurable selection network connected to debug nodes of the circuit. The selection network can be reconfigured after implementation of the circuit to route data from selectable debug nodes in the circuit under test to a controller to allow analysis of the circuit. The data collection system can further comprise a configurable data packer. A method of use of the system associates data from the debug nodes with individual debug nodes of the circuit based on a configuration of the configurable selection network or that of the configurable data packer or both. The method and system of the invention allows for efficient data collection from different sets of debug nodes without having to re-implement the circuit.

Abstract: According to an embodiment, an apparatus includes: a first node configured to receive a data input signal of a data latch; a second node configured to receive a data output signal of the data latch; process and hold circuitry configured to process a difference between a value of the data input signal received at the first node and a value of the data output signal received at the second node and hold respective values at the first and second nodes responsive to the difference; and comparison circuitry configured to compare the value held at the first node and a value of the data output signal of the data latch; wherein the process and hold circuitry is configured to be biased toward the signal received at one of the first node and the second node.

Abstract: The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by element type, and which may be configurable. The state machine element assigns various functions based on element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. In response to detection of a fault or failure, the state machine element re-assigns the first configuration to another composite circuit element and creates a second data link for performance of the same function, providing for the IC to continue the same functioning despite defects which may arise during operation.

Abstract: Power isolation during time intervals of sensitive operations is disclosed. In one embodiment, a programmable chip package includes a programmable chip configured to perform a sensitive operation, and a switch configured to selectively couple a main power source to the programmable chip. The programmable chip package may also include an alternate power source and a controller that is configured to control the switch to decouple the main power source from the programmable chip during a time interval of the sensitive operation, wherein the programmable chip is configured to draw power from the alternate power source during the time interval. The controller is further configured to control the switch to couple the main power source to the programmable chip after the time interval.

Abstract: Systems and methods are provided for destroying or erasing circuitry elements, data, or both, such as transistors, volatile keys, or fuse blocks, located in an integrated circuit device. An initiation signal may be provided to induce latch-up in a circuitry element in response to a user command, a tampering event, or both. As a result of the latch-up effect, the circuitry element, data, or both may be destroyed or erased.

Abstract: This invention comprises a layout method to effectively protect logic circuits against soft errors (non-destructive errors) and circuit cells, with layout, which are protected against soft errors. In particular, the method protects against cases where multiple nodes in circuit are affected by a single event. These events lead to multiple errors in the circuit, and while several methods exist to deal with single node errors, multiple node errors are very hard to deal with using any currently existing protection methods. The method is particularly useful for CMOS based logic circuits in modern technologies (.ltoreq.90 nm), where the occurrence of multiple node pulses becomes high (due to the high integration level). It uses a unique layout configuration, which makes the circuits protected against single event generated soft-errors.

Abstract: A D-type flip-flop includes tristate inverter circuitry passing a processing signal through to storage circuitry 8 from where the processing signal passes via a transmission gate to slave storage circuitry. A transition detector is coupled to the input node of the storage circuitry and serves to generate an error signal if a transition is detected upon that input node during an error detecting period. Other forms of this technique may provide clock gating circuitry.

Abstract: An electronic circuit includes a plurality of programmable components connected in an electronic chain. An interface is adapted to connect the programmable components to an external controller wherein the controller is adapted to program the programmable components. A component isolation element is connected to the interface at an input end and to the electronic chain of the programmable components at an output end wherein the isolation element is adapted to isolate one component of the programmable components from the electronic chain and wherein the one component is a safety component.

Abstract: A plurality of digital circuits are manufactured from an identical circuit design. A power controller is operatively connect to the digital circuits, and a non-volatile storage medium is operatively connected to the power controller. The digital circuits are classified into different voltage bins, and each of the voltage bins has a current leakage limit. Each of the digital circuits has been previously tested to operate within a corresponding current leakage limit of a corresponding voltage bin into which each of the digital circuits has been classified. The non-volatile storage medium stores boundaries of the voltage bins as speed-binning test data. The power controller controls power-supply signals applied differently for each of the digital circuits based on which bin each of the digital circuit has been classified and the speed-binning test data.

Abstract: Approaches for estimating a derating factor for a plurality of potential soft errors in a circuit implementation of a circuit design. A plurality of respective estimated toggle rates are determined for a plurality of circuit elements for implementing the circuit design. A derating factor of the circuit design is determined as a function of the estimated toggle rates of the plurality of circuit elements. The derating factor is an estimation of a fraction of the plurality of potential soft errors that would cause functional failure of the circuit design.

Abstract: An integrated circuit includes a first multiplexer (mux) with multiple inputs and configured to produce a mux output signal. The electronic circuit also includes a first gated buffer to receive the mux output signal from the first multiplexer and produce a first gated buffer output signal, a second gated buffer to receive the first gated buffer output signal and to produce a second gated buffer output signal to be provided to a pin, and a receive buffer. The receive buffer is coupled to the pin and receives an input signal from the pin. The electronic circuit operates in a test mode in which the second gated buffer is disabled preventing a test signal provided to an input of the first mux from reaching the pin. Instead, the test signal is provided through the first mux to the first gated buffer and to the receive buffer thereby testing the first mux.

Abstract: A digital electronic circuit includes: a plurality of sequential elements; at least one data-conducting path connecting an input sequential element to a destination sequential element; a clock outputting a clock signal on a clock tree for setting the speed of the sequential elements; a monitoring device receiving, as an input, at least one data signal traveling on a conducting path and arriving at a destination sequential element, the monitoring device including: a module for defining at least one detection window according to the clock tree; and a detector for detecting a transition of each data signal received during a detection window; and wherein each detection window is defined so as to enable the detection or anticipation of a fault corresponding to a violation of the rise time or the maintenance time of a data signal relative to a clock signal edge received by the destination sequential element receiving the data signal.

Abstract: A system for protecting an input/output (I/O) pin of an integrated circuit device (IC) from single event transients is disclosed. The system includes a first delay circuit that is configured to delay a clock signal from the clock source by a first predetermined amount of time, and a second delay circuit that is configured to delay the clock signal by a second predetermined amount of time. The system further includes a first register that is clocked by the clock signal, a second register that is clocked by the clock signal delayed by the first predetermined amount of time, and a third register that is clocked by the clock signal delayed by the second predetermined amount of time. The system also includes voter circuits, where each voter circuit is configured to receive a first data signal from an output of the first register, a second data signal from an output of the second register, and a third data signal from an output of the third register.

Abstract: A circuit for detecting a single bit upset in a dynamic logic circuit includes a latch circuit having an input for receiving a reset signal, and an output for providing a flag output signal, the latch circuit being clocked by a first clock signal, a first transistor having a drain coupled to the output of the latch circuit, a gate for receiving a second clock signal, and a source, and a second transistor having a drain coupled to the source of the first transistor, a gate for receiving a third clock signal, and a source coupled to ground.

Abstract: A system comprises a first signal processing logic module and at least one further signal processing logic module. The system further comprises mismatch handler logic module arranged to detect a mismatch between outputs of the first and at least one further signal processing logic module, the mismatch between outputs indicating a failed operation. The mismatch handler logic module further arranged, upon detection of a mismatch between outputs of the first and at least one further signal processing logic module, to analyze internal states of the first and at least one further signal processing logic module, determine whether the cause of the output mismatch is due to a transient fault, and upon determination that the cause of the output mismatch is due to a transient fault, to re-synchronize the first and at least one further signal processing logic module.