Abstract: The present invention relates to an apparatus and a method for detecting an open circuit fault condition in a differential signal, and generating a fault detection signal. An open circuit fault condition is detected by employing weak current sources to pull the differential signal paths outside the valid ac common-mode range and toward the supply rails. If both signal paths can be pulled within a predetermined proximity to the supply rails by their respective weak current sources, an open condition fault is defined to exist and a fault detection signal is generated. The fault detection signal can be used by another device to report the fault condition.

Abstract: An input/output (I/O) port designed for electrical interconnection with multiple similar ports includes an input read circuit, an output drive circuit, and a circuit to control the port for input or output mode by electrically disconnecting the output drive circuit from the port. Also included is a back drive current protection circuit placed in series in between an external I/O line and the input read and output drive circuits which blocks backdrive currents from other active processors when the processor that includes the protection circuit is in a powered down state while still allowing full input/output functionality in a powered up state.

Abstract: An interface for translating data of different voltages includes an input terminal structured to accept an input from a circuit supplied by a power supply having a first voltage level, as well as an output terminal structured to provide an output from the interface a first circuit portion powered by a power supply having the first voltage level, a second circuit portion is powered by a power supply having a second voltage level, and a power supply detection circuit structured to accept a detection signal and to maintain a correct output at the output terminal even after the power supply having the first voltage level no longer supplies the first voltage level to the interface.

Abstract: A storage cell of an integrated circuit is operable in a radiation environment to capture and store at predetermined time intervals a time sample of a data input signal. A signal representative of the stored data sample for each time interval is generated at an output of the storage cell. At least three data capturing circuits operate to capture and store a time sample of the data input signal at each predetermined time interval, the stored data sample of each circuit being generated correspondingly at an output thereof. Coupled to the outputs of the data capturing circuits is a circuit for generating a signal representative of a stored data sample selected from at least two of the circuit outputs. Also coupled to the data capturing circuits is a circuit for causing each data capturing circuit to capture a different time sample of the input data signal from the other data capturing circuits over each predetermined time interval.

Abstract: A protecting unit is provided. The protecting unit can prevent accidents from occurring that become problems when data are transmitted due to for instance LVDS and for instance laser light is emitted based on the data. The protecting unit is applied in an instrument comprising an input end to which differential signal is transmitted, the input end being attachable to and detachable from an input line. Here, the voltage at the input end when the input line is not connected is set to a voltage different from that generated at the input end when the input line is connected, variation of the voltage at the input end is transmitted to an input terminal of a differential input/output circuit, and the voltage at the input end or a portion corresponding thereto is compared with a prescribed voltage to fix a state of output of the differential input/output circuit to a prescribed state based on the compared results.

Abstract: A multiple voted integrated circuit logic cell testable by a scan chain comprises: an odd plurality of latching registers, each register having a data input for receiving a scan chain data signal and capable of latching the scan chain data signal and generating an output signal representative thereof; a multiple vote circuit governed by the output signals of the registers for generating an output signal of the logic cell; and a circuit coupled to each latching register for altering selectively the scan chain data signal input thereto. A scan chain test system for and method of testing at least one multiple voted logic cell of the aforementioned type are also disclosed.

Abstract: A micro-pipeline type asynchronous circuit and a method for detecting and correcting soft error. The asynchronous circuit records in a first recording unit a signal output by a calculation unit and then records in a second recording unit the same signal delayed by at least the duration of the pulse of a soft error. The recorded signals then are compared in a comparer circuit. If they are identical, no soft error has been detected and the output signal is recorded after another delay that is longer than the pulse duration of the soft error, and a request signal is transmitted to a control unit of a next logic stage with a delay twice as long as the pulse duration of a soft error.

Abstract: A circuit provides an output signal in accordance with crossing points of a differential signal, which includes a normal input signal and a complementary input signal. The circuit includes a first amplifier for amplifying a first signal difference between the normal input signal and a first threshold value, and for providing as a first output signal the amplified first signal difference. The circuit includes a second amplifier for amplifying a second signal difference between the complementary input signal and a second threshold value, and for providing as a second output signal the amplified second signal difference. The circuit also includes a first comparator for providing a first logical level when a third signal difference between the first output signal and the second output signal is greater than a third threshold value, and for providing a second logical level when the third signal difference is smaller than the third threshold value.

Abstract: To provide a semiconductor integrated circuit having a redundancy-relieved data output function which can carry out a pass/fail test of a selecting operation of a redundancy-relieved output selecting circuit for redundancy-relieved output data. Data inputs D of scan flip-flops SFFC <i+3>, SFFC <i+2>, SFFC <i+1> and SFFC <i> are connected to redundancy-relieved output data XDO <i+3>, XDO <i+2>, XDO <i+1> and XDO <i> in place of output data DO <i+3>, DO <i+2>, DO <i+1> and DO <i> of a conventional RAM 211, respectively. An AND gate 21 receives a serial output SO <i+4> at one of inputs and receives a selector test signal PFIN at the other input, and an output thereof is sent to the other input of an AND gate 223.

Abstract: Failsafe interface circuits are provided for an integrated circuit having a core logic section providing a signal to, or receiving a signal from, a bond pad connection. The interface circuits employ high voltage tolerant, extended drain devices in circuit arrangements which insure that the stress of a failsafe event is only exhibited by the extended drain devices. A failsafe event is defined as a bond pad voltage which exceeds the supply voltage of the integrated circuit plus the threshold voltage of the transistors within the integrated circuit. Both failsafe output driver circuit and failsafe receiver circuit embodiments are provided.

Abstract: Failsafe interface circuits are provided for an integrated circuit having a core logic section providing a signal to, or receiving a signal from, a bond pad connection. The interface circuits employ high voltage tolerant, extended drain devices in circuit arrangements which insure that the stress of a failsafe event is only exhibited by the extended drain devices. A failsafe event is defined as a bond pad voltage which exceeds the supply voltage of the integrated circuit plus the threshold voltage of the transistors within the integrated circuit. Both failsafe output driver circuit and failsafe receiver circuit embodiments are provided.

Abstract: A voltage clamp for a failsafe buffer used in connection with an electronic device. The voltage clamp clamps a voltage present at the output terminal of the buffer only when the electronic device is powered-on, and present a high impedance when the electronic device is not powered-on. Thus, when an electronic device such as a printer, for example, is connected to a network and the device is in a powered-on state, the voltage at the output terminal of the buffer is clamped to approximately the value of the electronic device power source. When the electronic device is powered-off, a voltage present at the output of the buffer will not clamped by the voltage clamp. Instead, the buffer will present a high impedance to the network and to other electronic devices connected thereto. Consequently, when an electronic device having a failsafe buffer constructed in accordance with the present invention enters an inoperable state due to device failure, power loss, etc.

Abstract: A fail-safe microprocessor-based system and method permits the controlling and monitoring of electrical devices for use in fail-safe interfacing of electrical devices to microprocessor-based control equipment in applications that are highly safety-critical. Such devices as relays, lamps, motors, contactors, pushbuttons, limit switches, solenoids and the like are monitored and controlled using codes. These functions are performed by standard, “off-the-shelf” microprocessor-based systems that are not ordinarily employed in or configured for such safety-critical applications. The fail-safe system provides for sufficiently fail-safe checking for such systems to be rendered highly reliable.

Abstract: An active fail-safe method and apparatus for a LVDS receiver that uses a window comparator circuit to monitor the differential voltage at the receiver's input pins and drive the output to a known logic HIGH state in the absence of a valid input signal; i.e., when the input differential signal is less than a chosen threshold value of approximately 80 mV. Such a condition may occur when the cable is removed or damaged in such a way that no valid input signal is present. In the presence of a valid input signal, the circuit's output tracks the differential input without any degradation to the signal.

Abstract: In a fault-tolerant integrated power circuit, a plurality of power transistors, each having a power source electrically coupled to a common source line, a power gate and a power drain electrically coupled to a common drain line, is capable of driving a power current from the source line to the drain line. A first plurality of control transistors, each having a first source, a first gate and a first drain, is disposed so that the first drain of each of the first plurality of control transistors is electrically coupled to a corresponding power gate of a different one of the power transistors. A first transistor control circuit generates a first control signal that is electrically coupled to each first gate of the first plurality of control transistors.

Abstract: An integrated circuit provided with an improved fail-safe mode.

Abstract: A system and method for observing bi-directional information transmitted between two integrated circuits is disclosed. The bi-directional information is transmitted on first and second communication links between a first and a second integrated circuit. The second integrated circuit includes a first data port electrically coupled to the first and second communication links. A second data port of the second integrated circuit is electrically coupled to the first communication link at the first data port of the second integrated circuit. The second data port is capable of electrical connection with an analyzing device. A third data port of the second integrated circuit is electrically coupled to the second communication link at the first data port of the second integrated circuit. A third communication link electrically couples the third data port of the second integrated circuit to a first data port of a third integrated circuit.

Abstract: A fail-safe circuit for a differential receiver can tolerate high common-mode voltages. An output from a differential amplifier that receives a V+ and a V− differential signal can be blocked by a NOR gate when the fail-safe condition is detected, such as when the V+, V− lines are open. Pullup resistors pull V+, V− to Vcc when an open failure occurs. A pair of comparators receive a reference voltage on the non-inverting input. Once comparator outputs a high when the V+ line is above the reference voltage, and the other comparator outputs a high when the V− line is above the reference voltage. When both V+ and V− are above the reference voltage, the NOR gate blocks the output from the differential amplifier, providing a fail-safe. Since the reference voltage is very close to Vcc, a high common-mode bias can exist on V+, V− without falsely activating the fail-safe circuit.

Abstract: A method and apparatus for reducing leakage in dynamic Silicon-On-Insulator (SOI) logic circuits improves the performance of dynamic gates implemented in SOI technology. A bias generator is used to create a negative potential by using the pre-charge input signal to bootstrap a bulk capacitor charging circuit, shifting a positively charged bulk capacitor terminal to ground, causing a negative potential at the other terminal. A bias control circuit applies this negative potential to intermediate nodes of logic input ladders of a dynamic logic gate to reduce leakage and threshold lowering effects due to the voltage variation on the bodies of logic input transistors implemented in SOI logic.

Abstract: A semiconductor IC includes a test circuit comprising a logic circuit, a test timing generator, a first register serving as a test signal generation point, and second and third registers serving as test signal observation points. In this test circuit, a target signal transmission path to be tested is selected from a plurality of signal transmission paths in the logic circuit, and the test timing generator outputs a test clock having a cycle according to a delay time of the selected signal transmission path on design to the first to third registers, whereby the first register generates a test signal and the second and third registers observe the test signal. Therefore, the signal transmission paths connecting the test signal generation point and the test signal observation point are tested with high efficiency, whereby more signal transmission paths are tested for delay faults with less number of times the test is executed.

Abstract: The present invention is an apparatus and method to overcome the unwanted effects of parasitic bipolar discharge in silicon-on-insulator (SOI) field effect transistors (FET) by eliminating the effects the sneak current discharging path by applying a contention free arrangement methodology to realize the dynamic logic circuit. The SOI MOS devices are arranged so as to eliminate the effects of electrical connections between certain intermediate nodes of the dynamic logic circuit. Accordingly, eliminating any parasitic bipolar current leakage paths associated with such electrical connections between certain intermediate nodes of said stacked SOI MOS devices of said dynamic circuit.

Abstract: A voltage blocking circuit is disclosed, useable in a buffer portion of an integrated circuit, for a buffer portion of an IC chip that operates from a power supply different from the power supply that powers the core logic; however, the buffer remains in a high impendence state, regardless of whether or not power is supplied to the core logic.

Abstract: A scheme for reduction of extra standby current induced by process defects is disclosed. After the bit lines and cells with failure due to process defects are repaired by using redundancy in the repairing process, the fuses connected with the pull-transistors coupled to the defect bit lines are disconnected, therefore cutting the leakage current completely. The standby leakage current can be reduced such that the SRAM can pass the standby current test and the yield is improved.

Abstract: A radiation-tolerant logic circuit includes three similarly configured SRAM-based PLDs. These PLDs work in parallel to provide identical logic functions. To guard against data corruption that can result from radiation-induced upsets, the logic circuit includes a state-comparison circuit that periodically performs a bitwise comparison of the configuration and user data from each of the PLDs; if a bit from one PLD differs from the corresponding bit from the others, the state-comparison circuit sets a flag that indicates that the differing PLD is in error. The erroneous PLD is then reprogrammed using error-free state data. In one embodiment, the error-free state data is read from an error-free PLD.

Abstract: A V.35 compliant driver is disclosed. The driver has three operational modes: OFF, low power (approximately 1/3 full power), and full power. The driver is placed in an appropriate mode based on conditions sensed at driver outputs. More particularly, the driver turns OFF upon sensing a short circuit condition, and reverts back to a normal operating condition following cessation of the short circuit condition by transitioning through a low power mode. Innovative approaches for satisfying V.35 source impedance measurement requirements and driver termination are also disclosed. All of the components associated with the driver reside on a single integrated circuit.

Abstract: A totem pole driver with cross conductive protection and default low impedance state output employs a totem pole output formed by top and bottom output transistors. A first circuit path switches the bottom output transistor on or off in response to a switching signal. A second circuit path, slower than the first circuit path, switches the top output transistor on in response to the switching signal after the bottom output transistor is switched off. A third circuit path switches the top output transistor off in response to a sync signal known to lead the switching signal. An emergency voltage supply is made available to hold the bottom output transistor on and the top output transistor off if the regulated circuit voltage is lost.

Abstract: A circuit and method to force an output of a logic circuit to a known state when its supply voltage rises above a predetermined level includes an MOS logic transistor (122) connected between the supply voltage (129) and the output line (130) and connected to receive an input signal (126) on its gate. An MOS state controlling transistor (124) of opposite conductivity type from the MOS logic transistor (122) is connected between the output line (130) and a reference potential (-V.sub.ss), with its gate connected to the gate of the MOS logic transistor (122). A resistor (132) is connected between the supply voltage (128) and the gate of the MOS state controlling transistor (124). If the supply voltage (128) rises above the predetermined level established by the threshold voltage of the MOS state controlling transistor, the MOS state controlling transistor (124) conducts to produce the reference potential on the output line (130).

Abstract: An ECL to CMOS signal converter circuit including built-in toggle-fault detection circuitry and method of conversion are provided in which an RF transformer is used to translate ECL level digital signals to CMOS level signals. A diode biasing circuit shifts the average DC level of the CMOS level signals in a positive direction to avoid signal undershoot. An AC peak detection circuit is connected to the inactive leg of the RF transformer to monitor toggling of the ECL level input signal lines. A DC comparator circuit compares the detected peak voltage with a predetermined threshold voltage, and generates an alarm signal representing a toggle-fault whenever the detected peak voltage is lower than the predetermined threshold.

Abstract: A fail-safe logic circuit employs a transformer (T) and a level tester (1). The transformer receives input signals each representing a binary logic variable and provides the sum of magnetic flux based on the input signals. The level tester tests the level of the sum of the magnetic flux and provides a binary output (y) representing a logic value of 1 or 0. This circuit is simple and capable of lowering an output level.

Abstract: An apparatus for activating a dual-mode logic device is provided. The apparatus monitors a parameter of an input signal of the logic device. If the parameter falls outside of predetermined parametric ranges, the apparatus activates the logic device. In the preferred embodiment, the apparatus resides on the same semiconductor chip as the logic device, and monitors the voltage level of the input signal. If the voltage level falls outside the voltage range which represents a logical HIGH and the voltage range which represents a logical LOW, the apparatus activates the logic device.

Abstract: A system of terminating a differential transmission line is described, where the differential transmitter and differential receiver are supplied by different power sources. The termination circuit comprises an unbalanced voltage divider pair, a connection to the receiver's voltage source, an adjustable threshold voltage, and circuitry to reduce power consumption. An unbalanced voltage divider pair provides matched termination impedances, and prevents undesired receiver output upon loss of transmitter signals. The voltage supplying the unbalanced voltage divider pair provides a voltage differential at the receiver inputs upon loss of the transmitter power source. An adjustable threshold voltage provides the minimum receiver input threshold voltage on which the transmitter signals can be superimposed. Power consumption is reduced through the use of a current limiter, which is coupled with a high pass filter to maintain the characteristic impedance of the transmission line during high frequency transmission.

Abstract: A controller for a clock generator. The controller of the present invention enables a clock signal to the internal clocking mechanism of a device. The controller of the present invention includes a detector and a timer. The detector has two input sense levels, such that it is capable of detecting a clock signal at two separate levels, the first level being larger than the second. Initially, the detector only detects when the clock signal is at a level greater than or equal to the larger of the levels. When this occurs, the timer begins counting. When the clock signal has been at or above the greater level for a predetermined time as determined by the timer, the detector enables the clock signal to go to the internal clocking mechanism. Thereafter, the detector only senses when the clock signal falls below the second level. Thus, the detector enables the clock signal to go to the internal clocking mechanism while the level of the clock signal is above the second level.