Fail-safe Patents (Class 326/14)
  • Patent number: 8228091
    Abstract: Disclosed is a false-link protection circuit comprising at least one native switch coupled between a communication terminal of a first differential switch and a communication terminal of a second differential switch. The at least one native switch is configured to provide an attenuation path for a pulse link signal received by either communication terminal when the first and second differential switches are in a powered down state. According to one embodiment, a method to attenuate a pulse link signal comprises activating a native switch of a false-link protection circuit by powering down first and second differential switches, receiving a pulse link signal at a communication terminal of one of the first and second differential switches, and attenuating the pulse link signal by diverting it through the false-link protection circuit when the first and second differential switches are in a powered down state.
    Type: Grant
    Filed: February 25, 2010
    Date of Patent: July 24, 2012
    Assignee: Broadcom Corporation
    Inventors: Ark-Chew Wong, Joseph Aziz, Derek Tam, Kevin Chan
  • Patent number: 8222915
    Abstract: New and improved methods and circuit designs for asynchronous circuits that are tolerant to transient faults, for example of the type introduced through radiation or, more broadly, single-event effects. SEE-tolerant configurations are shown and described for combinational logic circuits, state-holding logic circuits and SRAM memory circuits.
    Type: Grant
    Filed: April 27, 2010
    Date of Patent: July 17, 2012
    Assignee: Achronix Semiconductor Corporation
    Inventors: Rajit Manohar, Clinton W. Kelly
  • Patent number: 8191021
    Abstract: A method for single event transient filtering in an integrated circuit device is described. The device comprises three sequential elements, each having a data input and a data output with each of the three data outputs coupled to one of three inputs of a voting gate. The method comprises generating first and second nominally equivalent logic signals in first and second SET domains, converting the first and second nominally equivalent logic signals into first, second and third nominally equivalent data channels, and transmitting the first, second and third nominally equivalent data channels to the data inputs of the first, second and third sequential elements. Provision is made for applying the method to logic designs implemented in programmable logic integrated circuit devices.
    Type: Grant
    Filed: January 29, 2009
    Date of Patent: May 29, 2012
    Assignee: Actel Corporation
    Inventor: Sana Rezgui
  • Patent number: 8130009
    Abstract: In one embodiment, an integrated circuit includes a self calibration unit configured to iterate a test on a logic circuit in the integrated circuit at respectively lower supply voltage magnitudes until the test fails. A lowest supply voltage magnitude at which the test passes is used to generate a requested supply voltage magnitude for the integrated circuit. In an embodiment, an integrated circuit includes a series connection of logic gates physically distributed over an area of the integrated circuit, and a measurement unit configured to launch a logical transition into the series and detect a corresponding transition at the output of the series. The amount of time between the launch and the detection is used to request a supply voltage magnitude for the integrated circuit.
    Type: Grant
    Filed: February 22, 2011
    Date of Patent: March 6, 2012
    Assignee: Apple Inc.
    Inventor: Vincent R. von Kaenel
  • Patent number: 8081010
    Abstract: Self Restoring Logic (SRL) provides for SEU tolerance in high speed circuits. An SRL cell is designed to be stable in one of two internal states. Upon an SEU event, the SRL cell will not transition between the internal stable states and recover from an SEU. SRL circuits are realized with SRL storage cells driving succeeding SRL storage cells directly or through combinational logic such that the corruption of any one internal state variable in the driving SRL cell and it's the associated combinational output logic can affect at most one internal state variable of the succeeding SRL cell. An SRL circuit does not allow propagation of single SEU faults.
    Type: Grant
    Filed: November 24, 2010
    Date of Patent: December 20, 2011
    Assignee: ICS, LLC
    Inventors: Sterling R. Whitaker, Gary K. Maki, Lowell H. Miles
  • Patent number: 8072234
    Abstract: A method for testing a set of circuitry in an integrated circuit (IC) is described. The IC includes multiple configurable circuits for configurably performing multiple operations. The method configures the IC to operate in a user mode with a set of test paths that satisfies a set of evaluation criteria. Each test path includes a controllable storage element for controllably storing a signal that the storage element receives. The method operates the IC in user mode. The method reads the values stored in the storage elements to determine whether the set of circuitry is operating within specified performance limits.
    Type: Grant
    Filed: May 23, 2010
    Date of Patent: December 6, 2011
    Assignee: Tabula, Inc.
    Inventor: Brian Fox
  • Patent number: 8067954
    Abstract: The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by element type, and which may be configurable. The state machine element assigns various functions based on element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. In response to detection of a fault or failure, the state machine element re-assigns the first configuration to another composite circuit element and creates a second data link for performance of the same function.
    Type: Grant
    Filed: March 7, 2010
    Date of Patent: November 29, 2011
    Assignee: Element CXI, LLC
    Inventors: Steven Hennick Kelem, Jaime C. Cummins, John L. Watson, Robert Plunkett, Stephen L. Wasson, Brian A. Box, Enno Wein, Charles A. Furciniti
  • Patent number: 8030970
    Abstract: The invention relates to a device for forming an electric circuit comprising logic means (30) generating and using small signals of intermediate levels between the device supply levels and means for detecting signals leaving the small signal range.
    Type: Grant
    Filed: June 6, 2006
    Date of Patent: October 4, 2011
    Assignee: Etat Francais, repr{acute over ())}{acute over (})}senté par le Secretariat General de la Defense Nationale
    Inventor: Loïc Duflot
  • Patent number: 7999567
    Abstract: Single Event Upset (SEU, also referred to as soft error) tolerant arbiters, bare arbiters, and filters are disclosed. An arbiter provides a filter section, and a bare arbiter, coupled to the filter section. The bare arbiter includes a redundant first input and a redundant second input, and a redundant first output and a redundant second output. A pull-down transistor in the bare arbiter conditionally overpowers a corresponding pull-up transistor in the bare arbiter when a contention condition is present in the bare arbiter.
    Type: Grant
    Filed: January 7, 2010
    Date of Patent: August 16, 2011
    Assignee: California Institute of Technology
    Inventors: Wonjin Jang, Christopher D. Moore, Alain J. Martin
  • Patent number: 7990173
    Abstract: A circuit for handling single event upsets includes a plurality of digital clock manager circuits. A plurality of counters are respectively coupled by their inputs to the outputs of the digital clock managers and a reset controller is coupled to the outputs of the counters. The reset controller is configured to determine an expected value of the counters. In response to an output value of one of the counters being less than the expected value, the reset controller triggers a reset of the digital clock manager coupled to the input of the one of the counters. In response to an output value of one of the counters being greater than or equal to the expected value, the reset controller continues operation without triggering a reset of a digital clock manager.
    Type: Grant
    Filed: March 16, 2010
    Date of Patent: August 2, 2011
    Assignee: Xilinx, Inc.
    Inventors: Chen W. Tseng, Carl H. Carmichael
  • Patent number: 7982489
    Abstract: The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by element type, and which may be configurable. The state machine element assigns various functions based on element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. In response to detection of a fault or failure, the state machine element re-assigns the first configuration to another composite circuit element and creates a second data link for performance of the same function.
    Type: Grant
    Filed: September 27, 2009
    Date of Patent: July 19, 2011
    Assignee: Element CXI, LLC
    Inventors: Steven Hennick Kelem, Jaime C. Cummins, John L. Watson, Robert Plunkett, Stephen L. Wasson, Brian A. Box, Enno Wein, Charles A. Furciniti
  • Patent number: 7944230
    Abstract: The present invention includes a circuit-level system and method for preventing the propagation of soft errors in logic cells. A radiation jammer circuit in accordance with the present invention, including an RC differentiator and a depletion mode MOS circuit, when inserted at the output of a logic cell, significantly reduces the propagation of transient glitches. The radiation jammer circuit is a novel transistor-level optimization technique, which has been used to reduce soft errors in a logic circuit. A method to insert radiation jammer cells on selective nodes in a logic circuit for low overheads in terms of delay, power, and area is also introduced.
    Type: Grant
    Filed: September 15, 2010
    Date of Patent: May 17, 2011
    Assignee: University of South Florida
    Inventors: Nagarajan Ranganathan, Koustav Bhattacharya
  • Patent number: 7915657
    Abstract: Disclosed herein is a semiconductor integrated circuit including: a memory circuit section used for storing data; and a non-memory circuit section which is provided to serve as a section other than the memory circuit section and used for storing no data, wherein the second-conduction-type impurity concentration of a second-conduction-type semiconductor area including a channel created for a first-conduction-type transistor employed in the non-memory circuit section is lower than the second-conduction-type impurity concentration of a second-conduction-type semiconductor area including a channel created for a first-conduction-type transistor employed in the memory circuit section.
    Type: Grant
    Filed: December 24, 2009
    Date of Patent: March 29, 2011
    Assignee: Sony Corporation
    Inventors: Nobukazu Mikami, Hiroki Usui, Takuya Nakauchi
  • Patent number: 7902857
    Abstract: An apparatus and method provides the foundation for designing reconfigurable electronic computing systems. The invention relies on an ability to change the resistance state of a memristor device to achieve an optimal voltage at specific circuit nodes, whereby this dynamically and autonomously causes the circuit to reconfigure itself and produce a different output for the same input relative to the circuit's initial state. The circuit's state remains constant until the memristor's resistance is changed, at which point the circuit's function is “reprogrammed”.
    Type: Grant
    Filed: April 8, 2010
    Date of Patent: March 8, 2011
    Assignee: The United States of America as represented by the Secretary of the Air Force
    Inventor: Robinson E. Pino
  • Patent number: 7898286
    Abstract: Cross-die connection structure and method for a die or chip includes buffer elements having a buffer driver and bypass, and control lines coupled to the buffer elements in order to select one of the buffer driver and bypass for each respective buffer element. A logic network is arranged with the buffer elements to form functional paths, a test unit is structured and arranged to test the functional paths and to be coupled to the control lines, and a configuration storage register to set the selected one of the buffer driver and bypass for each passing functional path.
    Type: Grant
    Filed: February 11, 2009
    Date of Patent: March 1, 2011
    Assignee: International Business Machines Corporation
    Inventors: Igor Arsovski, Hayden C. Cranford, Jr., Joseph A. Iadanza, Todd E. Leonard, Jason M. Norman, Hemen R. Shah, Sebastian T. Ventrone
  • Patent number: 7880497
    Abstract: The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by element type, and which may be configurable. The state machine element assigns various functions based on element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. In response to detection of a fault or failure, the state machine element re-assigns the first configuration to another composite circuit element and creates a second data link for performance of the same function.
    Type: Grant
    Filed: May 8, 2009
    Date of Patent: February 1, 2011
    Assignee: Element CXI, LLC
    Inventors: Steven Hennick Kelem, Jaime C. Cummins, John L. Watson, Robert Plunkett, Stephen L. Wasson, Brian A. Box, Enno Wein, Charles A. Furciniti, Christopher E. Phillips
  • Patent number: 7876132
    Abstract: A circuit includes a first comparator block configured to output a voltage equal to a higher of a supply voltage and a bias voltage, a second comparator block configured to output a voltage equal to a higher of the bias voltage and an external voltage supplied through an Input/Output (IO) pad, and a third comparator block configured to output a voltage equal to a higher of the output of the first comparator block and the output of the second comparator block. A voltage across one or more constituent active element(s) of each of the first comparator block, the second comparator block, and the third comparator block is within an upper tolerable limit thereof during each of a normal operation, a failsafe operation, and a tolerant operation.
    Type: Grant
    Filed: October 16, 2009
    Date of Patent: January 25, 2011
    Assignee: LSI Corporation
    Inventors: Pankaj Kumar, Pramod Elamannu Parameswaran, Makeshwar Kothandaraman, Vani Deshpande, John Kriz
  • Patent number: 7872502
    Abstract: One embodiment of the present invention is a method for constructing defect-and-failure-tolerant demultiplexers. This method is applicable to nanoscale, microscale, or larger-scale demultiplexer circuits. Demultiplexer circuits can be viewed as a set of AND gates, each including a reversibly switchable interconnection between a number of address lines, or address-line-derived signal lines, and an output signal line. Each reversibly switchable interconnection includes one or more reversibly switchable elements. In certain demultiplexer embodiments, NMOS and/or PMOS transistors are employed as reversibly switchable elements. In the method that represents one embodiment of the present invention, two or more serially connected transistors are employed in each reversibly switchable interconnection, so that short defects in up to one less than the number of serially interconnected transistors does not lead to failure of the reversibly switchable interconnection.
    Type: Grant
    Filed: July 12, 2006
    Date of Patent: January 18, 2011
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Warren Robinett, Philip J. Kuekes, R. Stanley Williams
  • Patent number: 7868646
    Abstract: In one embodiment, a programmable logic device includes a plurality of configuration cells that store configuration data, wherein the programmable logic device is adapted to provide soft error upset (SEU) protection for the configuration cells that are reprogrammable. The programmable logic device may further include or alternatively provide hard coding and/or hard encoding of the configuration cells.
    Type: Grant
    Filed: June 18, 2010
    Date of Patent: January 11, 2011
    Assignee: Lattice Semiconductor Corporation
    Inventors: Brad Sharpe-Geisler, Satwant Singh
  • Patent number: 7847581
    Abstract: An integrated circuit including a substrate of a semiconductor material having first and second opposite surfaces and including active areas leveling the first surface. The integrated circuit includes a device of protection against laser attacks, the protection device includes at least one first doped region extending between at least part of the active areas and the second surface, a device for biasing the first region, and a device for detecting an increase in the current provided by the biasing device.
    Type: Grant
    Filed: April 1, 2009
    Date of Patent: December 7, 2010
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Mathieu Lisart, Vincent Pouget
  • Patent number: 7843236
    Abstract: The invention discloses a low voltage differential signal (LVDS) receiver, which is realized in an integrated circuit. The LVDS receiver includes: an input stage circuit receiving a full-range common-mode voltage and converting it into a current signal; a current source circuit coupled to the input stage circuit to provide a current source; and a current mirror circuit coupled the input stage circuit and the current source circuit to provide several bias voltage signals for the current source circuit and output a voltage signal to a buffer.
    Type: Grant
    Filed: May 23, 2008
    Date of Patent: November 30, 2010
    Assignee: Etron Technology, Inc.
    Inventors: Chen-Yuan Chang, Hsien-Sheng Huang
  • Patent number: 7834653
    Abstract: A method includes controllably utilizing a control signal generated by an Input/Output (IO) core to isolate a current path from an external voltage supplied through an IO pad to a supply voltage by transmitting a same voltage at an input terminal of a transistor, configured to be part of a number of cascaded transistors of an IO driver of an interface circuit, to an output terminal thereof during a failsafe mode of operation and a tolerant mode of operation. The method also includes feeding back an appropriate voltage to a floating node created by the isolation of the current path, and controlling a voltage across each transistor of the number of cascaded transistors to be within an upper tolerable limit thereof through an application of a gate voltage to each transistor derived from the supply voltage or the external voltage supplied through the IO pad.
    Type: Grant
    Filed: October 31, 2009
    Date of Patent: November 16, 2010
    Assignee: LSI Corporation
    Inventors: Pankaj Kumar, Pramod Elamannu Parameswaran, Makeshwar Kothandaraman, Vani Deshpande
  • Patent number: 7816950
    Abstract: Semiconductor integrated circuit has a control circuit. The control circuit causes the clock signal generating circuit to control the first clock signal and the second clock signal to make a logic of data held by the first data holding terminal and a logic of data held by the second data holding terminal equal to each other, and switches on the switch circuit, and the error detection circuit senses a logic of the first data holding terminal and a logic of the second data holding terminal after switching on the switching circuit.
    Type: Grant
    Filed: August 12, 2009
    Date of Patent: October 19, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takayuki Miyazaki
  • Patent number: 7812629
    Abstract: The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by element type, and which may be configurable. The state machine element assigns various functions based on element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. In response to detection of a fault or failure, the state machine element re-assigns the first configuration to another composite circuit element and creates a second data link for performance of the same function.
    Type: Grant
    Filed: August 17, 2008
    Date of Patent: October 12, 2010
    Assignee: Element CXI, LLC
    Inventors: Steven Hennick Kelem, Jaime C. Cummins, John L. Watson, Robert Plunkett, Stephen L. Wasson, Brian A. Box, Enno Wein, Charles A. Furciniti, Christopher E. Phillips
  • Patent number: 7812630
    Abstract: A latch circuit includes a feedback circuit having inverter circuits and at least two input terminals and an input circuit for inputting input signals or signals having the same phase as the input signals to the input terminals of the feedback circuit in synchronization with a clock signal. In the feedback circuit section, only when the input signals or the signals having the same phase as the input signals are input to the at least two input terminals at the same time, positive feedback using a predetermined number of amplification stages is applied to the input terminals.
    Type: Grant
    Filed: December 2, 2008
    Date of Patent: October 12, 2010
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Taiki Uemura, Yoshiharu Tosaka
  • Patent number: 7800396
    Abstract: A semiconductor integrated circuit includes a circuit block connected to an arithmetic processing unit via a bus, a power supply noise data generator which is configured to generate a power supply noise data signal by converting power supply noise generated in power supply voltage of power supply operates the circuit block, an error detector which is configured to detect an error of data outputted from the circuit block to the bus, and a write controller which is configured to associate power supply noise information based on the power supply noise data signal with data on the bus and write the data in a storage unit, and to stop to write the data in response to the detection of the error by the error detector.
    Type: Grant
    Filed: May 30, 2009
    Date of Patent: September 21, 2010
    Assignee: Fujitsu Limited
    Inventors: Takashi Yamamoto, Takaharu Ishizuka, Toshikazu Ueki, Takeshi Owaki, Atsushi Morosawa
  • Patent number: 7764081
    Abstract: A Programmable Logic Device (PLD) is provided with configuration memory cells displaying a superior soft error immunity by combating single event upsets (SEUs) as the configuration memory cells are regularly refreshed from non-volatile storage depending on the rate SEUs may occur. Circuitry on the PLD uses a programmable timer to set a refresh rate for the configuration memory cells. Because an SEU which erases the state of a small sized memory cell due to collisions with cosmic particles may take some time to cause a functional failure, periodic refreshing will prevent the functional failure. The configuration cells can be DRAM cells which occupy significantly less space than the SRAM cells. Refresh circuitry typically provided for DRAM cells is reduced by using the programming circuitry of the PLD. Data in the configuration cells of the PLD are reloaded from either external or internal soft-error immune non-volatile memory.
    Type: Grant
    Filed: August 5, 2005
    Date of Patent: July 27, 2010
    Assignee: Xilinx, Inc.
    Inventors: Tim Tuan, Prasanna Sundararajan
  • Patent number: 7741865
    Abstract: In one embodiment, a programmable logic device includes a plurality of configuration cells that store configuration data, wherein the programmable logic device is adapted to provide soft error upset (SEU) protection for the configuration cells that are reprogrammable. The programmable logic device may further include or alternatively provide hard coding and/or hard encoding of the configuration cells.
    Type: Grant
    Filed: April 27, 2009
    Date of Patent: June 22, 2010
    Assignee: Lattice Semiconductor Corporation
    Inventors: Brad Sharpe-Geisler, Satwant Singh
  • Patent number: 7728617
    Abstract: Some embodiments of the invention provide a configurable integrated circuit (IC) that includes several configurable circuits grouped in several tiles. The configurable IC also includes a configuration network for loading configuration data into the IC, where the configuration data is for configuring several of the configurable circuit. In some embodiments, the configuration network includes several registers at several boundaries between the tiles, where the registers allow multiple configuration data sets to be routed to multiple tiles concurrently. The configuration network in some embodiments includes several address counters at several tiles, where each address counter allows one address to be loaded for a tile and then to be successively incremented based on increment instructions sent over the configuration network. At least, two different addresses specified by an address counter of a particular tile identify two different resources within the particular tile.
    Type: Grant
    Filed: September 22, 2008
    Date of Patent: June 1, 2010
    Assignee: Tabula, Inc.
    Inventors: Jason Redgrave, Teju Khubchandani
  • Patent number: 7719304
    Abstract: The present invention provides a radiation hardened flip-flop formed from a modified temporal latch and a modified dual interlocked storage cell (DICE) latch. The temporal latch is configured as the master latch and provides four output storage nodes, which represent outputs of the temporal latch. The DICE latch is configured as the slave latch and is made of two cross-coupled inverter latches, which together provide four DICE storage nodes. The four outputs of the temporal latch are used to write the four DICE storage nodes of the DICE latch. The temporal latch includes at least one feedback path that includes a delay element, which provides a delay.
    Type: Grant
    Filed: May 8, 2008
    Date of Patent: May 18, 2010
    Assignee: Arizona Board of Regents for and on behalf of Arizonia State University
    Inventors: Lawrence T. Clark, Jonathan E. Knudsen
  • Patent number: 7705624
    Abstract: The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by element type, and which may be configurable. The state machine element assigns various functions based on element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. In response to detection of a fault or failure, the state machine element re-assigns the first configuration to another composite circuit element and creates a second data link for performance of the same function.
    Type: Grant
    Filed: August 17, 2008
    Date of Patent: April 27, 2010
    Assignee: Element CXI, LLC
    Inventors: Steven Hennick Kelem, Jaime C. Cummins, John L. Watson, Robert Plunkett, Stephen L. Wasson, Brian A. Box, Enno Wein, Charles A. Furciniti, Christopher E. Phillips
  • Patent number: 7675314
    Abstract: In a receiver circuit that receives data and clock signals through the cables, the number of transitions of a signal obtained based on the data or clock signal is detected by a frequency detection circuit, and when the number of transitions is not more than a predetermined set value, a signal for resetting the operation of a serial-parallel converter circuit included in a data processing unit is output, so as to control the output of received data. Thus, disconnection of the cable can be detected with low power consumption without providing a pull-up resistor and pull-down resistor and noise resistance can be improved.
    Type: Grant
    Filed: April 11, 2008
    Date of Patent: March 9, 2010
    Assignee: Panasonic Corporation
    Inventors: Tsuyoshi Ebuchi, Toru Iwata, Takefumi Yoshikawa
  • Patent number: 7656185
    Abstract: A semiconductor IC device includes at least one IO port, a core logic, and at least one fail-safe IO circuit, the fail-safe IO circuit being coupled between the core logic and the IO port, wherein the fail-safe IO circuit is configured to receive a predetermined control signal and to maintain the IO port at a predetermined impedance with respect to the predetermined control signal.
    Type: Grant
    Filed: July 13, 2007
    Date of Patent: February 2, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae Gyu Kim, Eon Guk Kim, Ju Young Kim
  • Patent number: 7646209
    Abstract: A semiconductor integrated circuit, able to repair a fault and normally operate as an overall circuit even when a fault occurs in a portion of the circuit, and able to reduce a change of signal delay along with the repair of the fault, including N (larger than 2) number of circuit modules which can replace each other's functions; circuit blocks each including R (larger than 1 but smaller than N) number of I/O units for outputting at least one signal to one circuit module, and receiving at least one signal generated in the one circuit module; and a circuit module selection unit configured to select R number of circuit modules from among the N number of circuit modules in response to a control signal, connect the selected R number of circuit modules and R number of I/O units of the circuit block in a 1:1 correspondence, and connect one circuit module selected from at least two circuit modules in response to the control signal to each of the R number of I/O units, and a method of producing the same.
    Type: Grant
    Filed: July 10, 2006
    Date of Patent: January 12, 2010
    Assignee: Sony Corporation
    Inventors: Mitsuhiro Oomori, Tomofumi Arakawa
  • Patent number: 7639036
    Abstract: A semiconductor integrated circuit having a test circuit for inspecting states of connections between a plurality of pads and respective external terminals by bonding wires. The test circuit comprises, for each of a plurality of pads, a control terminal provided to receive a control signal of a logic level equal to the logic level of a signal applied to a corresponding one of the external terminals, an inverter which inverts the logic level on the control terminal, an inverted output terminal of the inverter being connected to the pad via a connection line; and an exclusive-NOR gate which outputs an exclusive NOR of the logic level on the connection line and the logic level on the control terminal.
    Type: Grant
    Filed: July 18, 2008
    Date of Patent: December 29, 2009
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Akira Akahori
  • Publication number: 20090309627
    Abstract: The present invention includes a circuit-level system and method for preventing the propagation of soft errors in logic cells. A radiation jammer circuit in accordance with the present invention, including an RC differentiator and a depletion mode MOS circuit, when inserted at the output of a logic cell, significantly reduces the propagation of transient glitches. The radiation jammer circuit is a novel transistor-level optimization technique, which has been used to reduce soft errors in a logic circuit. A method to insert radiation jammer cells on selective nodes in a logic circuit for low overheads in terms of delay, power, and area is also introduced.
    Type: Application
    Filed: June 15, 2009
    Publication date: December 17, 2009
    Inventors: Nagarajan Ranganathan, Koustav Bhattacharya
  • Patent number: 7616024
    Abstract: The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by element type, and which may be configurable. The state machine element assigns various functions based on element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. In response to detection of a fault or failure, the state machine element re-assigns the first configuration to another composite circuit element and creates a second data link for performance of the same function.
    Type: Grant
    Filed: June 21, 2007
    Date of Patent: November 10, 2009
    Assignee: Element CXI, LLC
    Inventors: Steven Hennick Kelem, Jaime C. Cummins, John L. Watson, Robert Plunkett, Stephen L. Wasson, Brian A. Box, Enno Wein, Charles A. Furciniti
  • Patent number: 7576557
    Abstract: A method of configuring an integrated circuit having programmable logic including the steps of generating a configuration bitstream in accordance with a configuration setup, storing the configuration bitstream into a portion of a memory, configuring the programmable logic of the integrated circuit with a first configuration portion of the configuration bitstream of the memory, monitoring the integrated circuit for at least one configuration error generated in response to an event upset, reconfiguring at least a portion of the programmable logic of the integrated circuit with a second configuration portion of the configuration bitstream in response to the at least one configuration error generated. The integrated circuit may operate normally during the process of reconfiguring the at least a portion of the programmable logic.
    Type: Grant
    Filed: March 26, 2008
    Date of Patent: August 18, 2009
    Assignee: Xilinx, Inc.
    Inventors: Chen Wei Tseng, Carl H. Carmichael
  • Patent number: 7550991
    Abstract: Some embodiments of the invention provide a configurable integrated circuit (IC) that includes several configurable circuits for configurably performing different operations and several user design state (UDS) circuits for storing user-design state values. The IC further includes a trace buffer for storing user-design state values associated with an operational trigger even of the IC. In some embodiments, the configurable circuits, UDS circuits, and tracer buffer are on a single IC die.
    Type: Grant
    Filed: March 13, 2006
    Date of Patent: June 23, 2009
    Assignee: Tabula, Inc.
    Inventors: Jason Redgrave, Brad Hutchings, Teju Khubchandani
  • Patent number: 7504851
    Abstract: New and improved methods and circuit designs for asynchronous circuits that are tolerant to transient faults, for example of the type introduced through radiation or, more broadly, single-event effects. SEE-tolerant configurations are shown and described for combinational logic circuits, state-holding logic circuits and SRAM memory circuits.
    Type: Grant
    Filed: April 25, 2007
    Date of Patent: March 17, 2009
    Assignee: Achronix Semiconductor Corporation
    Inventors: Rajit Manohar, Clinton W. Kelly
  • Patent number: 7499676
    Abstract: A low voltage differential signaling transceiver includes a transmitter and a receiver, the transmitter having a first terminal in signal communication with a transmission line, a source resistance in signal communication with the first terminal, a switch in signal communication with the source resistance and in switchable signal communication from ground or an input voltage, a voltage regulator in switchable signal communication with the switch for providing the input voltage to the switch, and a voltage controller in signal communication between the first terminal and the voltage regulator for controlling the input voltage to provide a controlled voltage to a receiver; and the receiver having an amplifier having a first input, a first pad in signal communication with the first input, a load resistance, and a second pad in signal communication with the load resistance, where the first and second pads are both in signal communication with one end of a first transmission line.
    Type: Grant
    Filed: October 6, 2005
    Date of Patent: March 3, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jac-Youl Lee, Jae-Suk Yu, Jong-Seon Kim
  • Publication number: 20080315911
    Abstract: In a receiver circuit that receives data and clock signals through the cables, the number of transitions of a signal obtained based on the data or clock signal is detected by a frequency detection circuit, and when the number of transitions is not more than a predetermined set value, a signal for resetting the operation of a serial-parallel converter circuit included in a data processing unit is output, so as to control the output of received data. Thus, disconnection of the cable can be detected with low power consumption without providing a pull-up resistor and pull-down resistor and noise resistance can be improved.
    Type: Application
    Filed: April 11, 2008
    Publication date: December 25, 2008
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Tsuyoshi Ebuchi, Toru Iwata, Takefumi Yoshikawa
  • Patent number: 7443191
    Abstract: The present system comprises a radiation tolerant programmable logic device having logic modules and routing resources coupling together the logic modules. Configuration data lines providing configuration data control the programming of the logic modules and the routing resources. Error correction circuitry coupled to the configuration data lines analyzes and corrects any errors in the configuration data that may occur due to a single event upset (SEU).
    Type: Grant
    Filed: September 21, 2007
    Date of Patent: October 28, 2008
    Assignee: Actel Corporation
    Inventor: William C. Plants
  • Publication number: 20080238472
    Abstract: A semiconductor integrated circuit device uses two keeper cells per configuration and/or enable bit as dual redundant storage with error detection thereof. One of the two keeper cells stores a logic level and the other keeper cell stores the inverse of that logic level before the integrated circuit device goes into a low power mode. An exclusive OR (XOR) is performed on the outputs of the two keeper cells (a keeper cell pair) such that if the two keeper cells of the keeper cell pair do not have opposite logic levels stored therein, then the respective XOR outputs an error signal for that keeper cell pair and the error signal is used to force the integrated circuit device out of the low power mode, depending on software control, with or without disturbing input-output (I/O) configuration control and data states present at the time the low power mode was entered.
    Type: Application
    Filed: January 22, 2008
    Publication date: October 2, 2008
    Inventor: Michael Simmons
  • Patent number: 7427872
    Abstract: In some embodiments, a chip includes first and second nodes, a variable voltage source, and transmitter and control circuitry. The transmitter includes a driver coupled to the first and second nodes, and first and second resistive structures coupled between the first and second nodes, respectively, and the variable voltage source. The control circuitry selects an impedance level for the first and second resistive structures, and detect coupling of a remote receiver to the transmitter through interconnects and detect decoupling of the remote receiver from the transmitter. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 13, 2005
    Date of Patent: September 23, 2008
    Assignee: Intel Corporation
    Inventors: Theodore Z. Schoenborn, Andrew W. Martwick
  • Patent number: 7427871
    Abstract: The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by element type, and which may be configurable. The state machine element assigns various functions based on element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. In response to detection of a fault or failure, the state machine element re-assigns the first configuration to another composite circuit element and creates a second data link for performance of the same function.
    Type: Grant
    Filed: June 21, 2006
    Date of Patent: September 23, 2008
    Assignee: Element CXI, LLC
    Inventors: Steven Hennick Kelem, Jaime C. Cummins, John L. Watson, Robert Plunkett, Stephen L. Wasson, Brian A. Box, Enno Wein, Charles A. Furciniti
  • Patent number: 7424642
    Abstract: A system and method for reintegration of a redundant controller after occurrence of a fault is provided, comprising synchronizing outputs of a primary controller with outputs of secondary controllers. The controller is placed in a different mode of operation in which its output is not used in system control. A meta-controller is activated to drive the primary controller to the same states at which the secondary or redundant controllers operate. A voting mechanism is used to determine a fault in an output to a controlled device. Control of the device using the secondary outputs is effected. The primary controller recalculates the primary output, based upon the primary output; a feedback signal; and, the secondary outputs. Control using the primary output is permitted when the primary output is within an allowable range of the secondary outputs.
    Type: Grant
    Filed: April 24, 2006
    Date of Patent: September 9, 2008
    Assignee: GM Global Technology Operations, Inc.
    Inventors: Mark N. Howell, Pradyumna K. Mishra
  • Patent number: 7423448
    Abstract: A radiation-hardened logic circuit prevents SET-induced transient pulses from propagating through the circuit, using two identical logic paths. The outputs of the two logic paths are fed into an exclusive-OR gate, which controls gating circuitry. The gating circuitry can be a controlled pass-gate circuit and a data latch, an adjustable threshold comparator, or two controlled latches. Transient pulse suppression is achieved with less circuitry and expense than is found in TMR circuits.
    Type: Grant
    Filed: March 3, 2006
    Date of Patent: September 9, 2008
    Assignee: Aeroflex Colorado Springs Inc.
    Inventor: Matthew Von Thun
  • Publication number: 20080197875
    Abstract: An integrated circuit is provided having at least one terminal for coupling and/or decoupling of electric signals, particularly of digital signals, and having integrated reference potential means, assigned to the terminal, for providing an electric reference potential to the terminal. It is provided according to an embodiment of the invention that the reference potential means is switchable, particularly by an override process.
    Type: Application
    Filed: January 16, 2008
    Publication date: August 21, 2008
    Inventor: Anton Koch
  • Patent number: 7397269
    Abstract: Provided is a disconnection and short detecting circuit capable of detecting disconnection and short of a signal line transmitting a differential clock signal. A differential buffer part DB1 has a first comparator to compare a non-inverting clock signal inputted from a PADI and an inverting clock signal inputted from a PADR; a second comparator to compare a non-inverting clock signal and a reference potential Vref; and a third comparator to compare an inverting clock signal and the reference potential Vref. Their respective outputs are defined as Y, YI and YR, respectively. If the signal line of either a non-inverting clock signal or an inverting clock signal is disconnected, or short-circuited to a grounding potential VSS of a logical value Low, the logical values outputted from the second and the third comparators are equal for a long period of time in one cycle of the non-inverting clock signal or the inverting clock signal.
    Type: Grant
    Filed: April 5, 2007
    Date of Patent: July 8, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Atsuhiko Ishibashi, Yasuhiro Fujino