With Test Facilitating Feature Patents (Class 326/16)
  • Patent number: 10644892
    Abstract: The present disclosure relates to implementations of physically unclonable functions (PUFs) for cryptographic and authentication purposes. Specifically, the disclosure describes implementations of machine learning engines (MLEs) in conjunction with PUFs generating outputs having multiple states.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: May 5, 2020
    Assignee: ARIZONA BOARD OF REGENTS ON BEHALF OF NORTHERN ARIZONA UNIVERSITY
    Inventors: Fatemeh Afghah, Bertrand Francis Cambou
  • Patent number: 10469273
    Abstract: The present disclosure relates to implementations of physically unclonable functions (PUFs) for cryptographic and authentication purposes. Specifically, the disclosure describes implementations of machine learning engines (MLEs) in conjunction with PUFs generating outputs having multiple states.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: November 5, 2019
    Assignee: Arizona Board of Regents on Behalf of Northern Arizona University
    Inventors: Fatemeh Afghah, Bertrand Francis Cambou
  • Patent number: 10454477
    Abstract: A dynamic decode circuit for decoding a plurality of input signals to produce a positive output pulse one gate delay following a clock signal, wherein the output pulse indicates the plurality of signals were in a predetermined state, wherein the output pulse is active during an evaluation phase of a clock cycle and not active during a precharge phase of the clock cycle, wherein precharge is performed by nfet transistors.
    Type: Grant
    Filed: May 19, 2019
    Date of Patent: October 22, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Antonio Raffaele Pelella
  • Patent number: 10425081
    Abstract: To realize control of a system for which a high level of safety is demanded by one SRAM-type FPGA, it is to eliminate a possibility that an undesirable control signal is output to the outside of the FPGA because of influence of failure by a soft error and the like and a problem. To solve this problem, there is provided a hard macro having fixed circuitry structure, programmable logic arranged via an interval close to the hard macro and having a changeable circuitry structure, and an I/F circuit which is provided inside the programmable logic and outputs a processing result in the programmable logic to the hard macro. It is a characteristic that the I/F circuit monitors soundness of the programmable logic and stops output of the processing result to be transmitted to the hard macro on the basis of a monitoring result.
    Type: Grant
    Filed: January 28, 2015
    Date of Patent: September 24, 2019
    Assignee: Hitachi, Ltd.
    Inventors: Teruaki Sakata, Tsutomu Yamada, Teppei Hirotsu
  • Patent number: 10374604
    Abstract: A dynamic decode circuit for decoding a plurality of input signals to produce a positive output pulse one gate delay following a clock signal, wherein the output pulse indicates the plurality of signals were all positive, wherein the output pulse is active during an evaluation phase of a clock cycle and not active during a precharge phase of the clock cycle, wherein precharge is performed by nfet transistors.
    Type: Grant
    Filed: August 12, 2018
    Date of Patent: August 6, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Antonio Raffaele Pelella
  • Patent number: 10365328
    Abstract: A register array includes a plurality of groups of latches. Each of the groups of latches includes a first latch, a second latch, and a test latch connected to the first latch and the second latch. During functional operation the first latch and the second latch process data, in response to the same read/write clock signal supplied simultaneously to the first read/write clock input and the second read/write clock input. During test operation a skewed test clock signal of an original test clock signal is supplied at different timings to the first latch, the second latch, and the test latch, and a single scan signal is input to the first latch. The single scan signal cascades from the first latch through the test latch to the second latch, and is output by the second latch, within a single cycle of the original test clock signal.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: July 30, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jian Sun, Chao Meng, Xiaoxiao Li, Yinpeng Lu
  • Patent number: 10229081
    Abstract: An information handling system includes a receiver and a transmitter. A margin detector of the receiver derives an eye plot for signals received via a plurality of high speed serial lanes. A first control module of the receiver identifies a weakest lane of the high speed serial lanes, and compares eye plots for a signal on the weakest lane from one crosstalk minimization iteration to the next. A second control module of the transmitter receives a signal from the first control module indicating whether an eye plot of the signal has improved from one crosstalk minimization iteration to the next, and iteratively controls a phase shift of aggressor signals in the high speed serial lanes during each iteration until the eye plot of the signal remains the same from one iteration to the next. A phase shift module of the transmitter phase shifts the aggressor signals during each iteration.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: March 12, 2019
    Assignee: Dell Products, LP
    Inventors: Stuart Allen Berke, Bhyrav M. Mutnury, Vadhiraj Sankaranarayanan
  • Patent number: 10222417
    Abstract: Embodiments relate to providing security of scan mode access and data in an integrated circuit. In embodiments, one or both of two layers of security are provided. A first layer includes requiring a complex initialization sequence to be performed in order to access scan mode. A second layer includes scrambling the scan data before it is output from the circuit under test, which prevents unauthorized persons from extracting useful information from the output scan data. Further embodiments relate to methodologies for utilizing these protection layers after manufacture of the integrated circuit and incorporating these protection layers in an integrated circuit design flow.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: March 5, 2019
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Akhil Garg, Dale Meehl, Sahil Jain
  • Patent number: 10185633
    Abstract: This disclosure is directed to processor state integrity protection using hash verification. A device may comprise processing circuitry and memory circuitry. The processing circuity may be triggered to enter a secure mode. Prior to entering the secure mode, the processing circuitry may determine a processor state of the processing circuitry and a hash of the processor state, and store them in secured memory within the memory circuitry. Prior to exiting the secure mode, the processing circuitry may compute an updated hash of the stored processor state and compare it to the previously stored hash. If the updated hash and stored hash are determined to be the same, then the processing circuitry may restore the processor state and normal operation resumes. If the updated hash and stored hash are determined to be different, then the stored processor state may be compromised and the processing circuitry may perform at least one protective action.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: January 22, 2019
    Assignee: Intel Corporation
    Inventor: Rodrigo R. Branco
  • Patent number: 10101385
    Abstract: The disclosure describes a novel method and apparatus for improving interposers to include embedded monitoring instruments for real time monitoring digital signals, analog signals, voltage signals and temperature sensors located in the interposer. An embedded monitor trigger unit controls the starting and stopping of the real time monitoring operations. The embedded monitoring instruments are accessible via an 1149.1 TAP interface on the interposer.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: October 16, 2018
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 10097181
    Abstract: Apparatuses and methods for standby current control of a signal path in a semiconductor device are described. An example apparatus includes: first and second logic gates coupled in series; a first circuit coupled between the first logic gate and a power supply line that activates the first logic gate responsive to a first control signal; and a second circuit coupled between the second logic gate and the power supply line that activates the second logic gate responsive to a second control signal that is different from the first control signal.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: October 9, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Tetsuya Arai
  • Patent number: 10090060
    Abstract: According to one embodiment, a data communication system includes: a data transmitting device that transmits a test pattern; and a data receiving device that receives the test pattern. The data receiving device receives the test pattern with every change in a threshold for determining whether received data is High or Low, compares the test pattern to an expected value for the respective changed thresholds, and selects the threshold based on the result of comparison between the test pattern and the expected value.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: October 2, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Akihiro Fukushima, Shuji Matsumoto, Makoto Hara, Yasushi Yamakawa
  • Patent number: 10037259
    Abstract: Systems, methods, and apparatuses to perform an operation comprising receiving an indication of a first error in a processor, identifying a first control signal, of a plurality of control signals in a debug bus, associated with the error, wherein each of the plurality of control signals are coupled to one of a plurality of input ports of a multiplexer, and changing a configuration state of the multiplexer to output the first control signal to a trace array.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: July 31, 2018
    Assignee: International Business Machines Corporation
    Inventors: Khandker N. Adeeb, Steven J. Battle, Brandon R. Goddard, Dung Q. Nguyen, Tu-An T. Nguyen, Nicholas R. Orzol, Brian D. Victor, Brendan M. Wong
  • Patent number: 10001999
    Abstract: A new approach is proposed which contemplates system and method for configuring a plurality of configurable registers in a programmable digital processing engine of a network device. Under the proposed approach, one or more slave configuration controllers (SCC) are utilized to configure a large number of configurable registers in a programmable engine, wherein each SCC is used to configure a plurality of configurable registers, which are organized in multiple configuration groups. The configurable registers in each configuration group are connected in a looped one-way daisy chain. During its operation, each of the slave configuration controllers is configured to receive instructions from a user via a master configuration controller (MCC), performs read or write operations on the configurable registers of one of the configuration groups as designated by the instructions from the user.
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: June 19, 2018
    Assignee: Cavium, Inc.
    Inventors: Anh Tran, Gerald Schmidt, Harish Krishnamoorthy
  • Patent number: 9910676
    Abstract: Methods and apparatus are provided for controlling one or more memory devices connected to an input output (IO) circuit through a serial peripheral interface (SPI), to make any device which is in execute in place (XIP) mode exit XIP mode. An example method comprises driving an initial signal from the IO circuit onto the data pins for a first plurality of clock cycles, the initial signal causing any memory device not in XIP mode to treat subsequent signals as a dummy read, disabling a driving function of the IO circuit prior to a negative edge of a last one of the first plurality of clock cycles, stopping generation of clock signals for a transition waiting period after the first plurality of clock cycles, and activating a weak pull-up of the IO circuit to apply logic high on all of the data pins for a second plurality of clock cycles.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: March 6, 2018
    Assignee: MICROSEMI SOLUTIONS (U.S.), INC.
    Inventors: Unnikrishnan Sivaraman Nair, Sujaata Ramalingam
  • Patent number: 9899990
    Abstract: A semiconductor circuit includes a first circuit and a second circuit. The first circuit determines a logic level of a second node and a logic level of a third node, on the basis of a logic level of input data, a logic level of a clock signal, and a logic level of a first node. The second circuit determines the logic level of the first node, on the basis of the logic level of the clock signal, the logic level of the second node and the logic level of the third node. The first circuit comprises a sub-circuit and a first transistor. The first circuit determines the logic level of the second node, on the basis of the logic level of the input data and the logic level of the first node. The first transistor is gated to the logic level of the clock signal to connect the third node with the second node.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: February 20, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: San-Ha Kim, Min-Su Kim, Matthew Berzins
  • Patent number: 9851400
    Abstract: A system, apparatus, and method for testing blocks of a system on a chip (SOC) are described herein. An SOC, in accordance with various embodiments, may include a serial communication interface configured to multiplex, serialize, and/or parallelize signals streams from selected blocks of the SOC to an off-chip test unit through an off-chip serial communication interface. Other embodiments may be described and claimed.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: December 26, 2017
    Assignee: Marvell International Ltd.
    Inventors: Roger Longstreet, Vivek Raghunath Khanzode, Hongying Sheng
  • Patent number: 9825638
    Abstract: A virtual critical path (VCP) circuit is defined separate from an actual critical path circuit. The VCP operates in accordance with a special clock signal. The actual critical path circuit operates in accordance with a system clock signal. The VCP circuit has a signal timing characteristic substantially equal to that of the actual critical path circuit. The VCP circuit includes computational circuitry defined to compute an output value based on an input value, and comparison circuitry defined to compare the output value with an expected result value. A match between the output value computed by the VCP circuit and the expected result value indicates that a frequency of the special clock signal is acceptable. The VCP circuit is used to determine a maximum acceptable frequency of the special clock signal. A frequency of the system clock signal is then set to the maximum acceptable frequency of the special clock signal.
    Type: Grant
    Filed: March 5, 2014
    Date of Patent: November 21, 2017
    Assignee: Sandisk Technologies LLC
    Inventors: Yan Dumchin, Yair Baram, Michael Tomashev, Leonid Minz, Yevgeny Kaplan, Suzanna Zilberman
  • Patent number: 9817066
    Abstract: A circuit couples a test access port (TAP) having a JTAG interface to another port having a serial interface different from the JTAG interface. The circuit includes a forwarding circuit and a timing control circuit. The forward circuit is coupled to couple a test data in (TDI) terminal, a test data out (TDO) terminal, and a test clock (TCK) terminal of the TAP to an input terminal, an output terminal, and a clock terminal of the another port, respectively. The timing control circuit is coupled to drive a select terminal of the another port with a select signal that activates serial data transfer through the serial interface to a device. The timing control circuit delays assertion of the select signal by a configurable time period after assertion of a shift data state of a state machine of the TAP.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: November 14, 2017
    Assignee: XILINX, INC.
    Inventors: Randal M. Kuramoto, Stephanie Trapp, Matthew K. Nielson
  • Patent number: 9798842
    Abstract: An integrated circuit may include observable storage circuits and unobservable or non-observable storage circuits. Among values stored in the observable and the non-observable storage circuits, only the values stored in the observable storage circuits are accessible for read-back and/or write-back operations during hardware emulation. A computer system may receive a circuit design that includes a design-under-test and implement at least a portion of the circuit design in the integrated circuit. The computer system may insert observable storage circuits into the circuit design and couple the observable storage circuits to the non-observable storage circuits such that the data stored in the non-observable storage circuits may be accessed during read-back operations using the inserted observable storage circuits.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: October 24, 2017
    Assignee: Altera Corporation
    Inventor: Michael Hutton
  • Patent number: 9798599
    Abstract: An embodiment of a circuit includes a data latch and a plurality of cascaded latches, wherein a first of the plurality of cascaded latches is configured to receive a first signal from the data latch and each subsequent cascaded latch is configured to receive a data output signal of a preceding cascaded latch, and an error-detection circuit configured to receive the respective data output signals and detect error in operation of the cascaded latches based thereon.
    Type: Grant
    Filed: February 25, 2015
    Date of Patent: October 24, 2017
    Assignee: STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Chittoor Parthasarathy, Abhishek Jain
  • Patent number: 9793895
    Abstract: An electronic circuit includes: a first logic circuit coupled to a first input line and a first output line; a second logic circuit coupled to a second input line and a second output line; a first line pattern coupled to the first output line and including an input line different from the second input line; and a second line pattern coupled to the second output line and different from the first input line, wherein at least a part of the first output line, the first line pattern, the second output line, or the second line pattern has a folded shape or a circular shape.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: October 17, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Dai Yamamoto, Naoya Torii, Ikuya Morikawa
  • Patent number: 9729128
    Abstract: A multi-bit flip-flop (MBFF) includes a plurality of 1-bit flip-flops, each having an input data selection circuit that receives a data signal and a scan data signal. The MBFF also includes a local signal generation circuit that receives a global clock signal and a global scan enable signal, and in response, provides local control signals, wherein each of the local control signals is generated in response to both the global clock signal and the global scan enable signal. The local control signals are provided to the input data selection circuits, and exclusively control the input data selection circuits to route either the input data signal or the scan input data signal as a master data bit, reducing transistor requirements. Local clock signals may be generated by the local signal generation circuit in response to the global clock signal, and may exclusively control data transfer within the flip-flops, improving setup time.
    Type: Grant
    Filed: April 9, 2015
    Date of Patent: August 8, 2017
    Assignee: Synopsys, Inc.
    Inventors: Manish Srivastava, Basannagouda Somanath Reddy
  • Patent number: 9722615
    Abstract: In a multi-context PLD (dynamically reconfigurable circuit), at the time of rewriting configuration data on a non-selected context during circuit operation, configuration data is stably stored. At the time of rewriting configuration data on a non-selected context, writing to a row which is to be rewritten continues until input signals supplied to input terminals of routing switches in the row become “L” all that time or the input signals become “L” at least once. More specifically, a write selection signal for the row continues to be output. In addition, while the write selection signal is being output, loading of configuration data into a driver circuit is not conducted, or loading of configuration data into a driver circuit is conducted but storage thereof in a line buffer is not conducted.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: August 1, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yoshiyuki Kurokawa
  • Patent number: 9722612
    Abstract: Techniques are provided to permit a programmable logic device (PLD) to comply with a communication standard before the PLD is fully configured. In one example, a method includes programming a first portion of a programmable logic device (PLD) with first configuration data. After the first portion is programmed, the first portion is operated in accordance with a communication standard to exchange data with a host system while a second portion of the PLD is programmed with second configuration data.
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: August 1, 2017
    Assignee: Lattice Semiconductor Corporation
    Inventors: Umesh Ananthiah, Tramie Tran, Jamie Freed
  • Patent number: 9721626
    Abstract: A semiconductor apparatus includes a clock buffer and a reference voltage generation unit. The clock buffer generates an internal clock signal, based on first and second clock signals, in a first operation mode, and generates the internal clock signal, based on the first clock signal and a reference voltage, when a normal operation test is performed in a second operation mode. The reference voltage generation unit generates the reference voltage when the normal operation test is performed in the second operation mode.
    Type: Grant
    Filed: November 10, 2014
    Date of Patent: August 1, 2017
    Assignee: SK Hynix Inc.
    Inventor: Tae Jin Kang
  • Patent number: 9673789
    Abstract: A signal-generating circuit includes a first P-type transistor, a second P-type transistor, a first N-type transistor, a second N-type transistor, a first inverter, a second inverter, and a third inverter. The first P-type transistor supplies a supply voltage to a first node according to an input signal. Both of the second P-type transistor and the first N-type transistor couple the first node to a second node according to the input signal. The second N-type transistor couples the first node to a ground according to the input signal. The first inverter is coupled to the second node to generate a first signal. The second inverter is coupled between the first node and a third node. The third inverter is coupled to the third node to generate a second signal. The second signal and the first signal are the reverse of each other and synchronous.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: June 6, 2017
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
    Inventor: Jade Deng
  • Patent number: 9633156
    Abstract: In accordance with embodiments of the present disclosure, a multi-bit pulsed latch circuit for an integrated circuit design system may include a pulse generator and a plurality of latches. The pulse generator may be configured to generate pulses. The plurality of latches may operate as storage elements and are coupled to the pulse generator in a manner so that the multi-bit pulsed latch circuit provides functionality of at least two flip flop elements, wherein the multi-bit pulsed latch circuit can replace the at least two flip flop elements that normally would be used by the integrated circuit design system.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: April 25, 2017
    Assignee: Cirrus Logic, Inc.
    Inventors: Bhoodev Kumar, Saurabh Singh, Lei Zhu
  • Patent number: 9608567
    Abstract: A transceiver comprising a tank circuit, a variable differential conductance, VDC, coupled to the tank circuit, and a variable resistance coupled to the VDC is disclosed. The variable resistance is arranged to bias the VDC into a region of positive differential conductance during a first state of operation of the transceiver, and bias the VDC into a region of negative differential conductance during a second state of operation of the transceiver.
    Type: Grant
    Filed: May 30, 2011
    Date of Patent: March 28, 2017
    Assignee: Acconeer AB
    Inventors: Mikael Egard, Mats Ärlelid, Lars-Erik Wernersson
  • Patent number: 9557380
    Abstract: Scan flip-flop and associated method are provided. The scan flip-flop includes a data input terminal, a scan input terminal, a flip-flop circuit, a first transistor and a plurality of second transistors. A gate of the first transistor is coupled to the scan input terminal, gates of the second transistors are commonly coupled to an enabling signal, drains and sources of the first transistor and the second transistors are serially coupled to the flip-flop circuit, so as to increase a delay between the scan input terminal and the flip-flop circuit.
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: January 31, 2017
    Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sho-Mo Chen, Chien-Cheng Wu
  • Patent number: 9514817
    Abstract: A non-volatile memory device includes plural non-memory cells. Each non-volatile memory cell includes a first switch, a first memristor, a second switch, a second memristor and a third switch. The control terminal of the first switch is coupled to a word line. The first memristor is provided with a first impedance. The control terminal of the second switch is coupled to the word line. The second memristor is provided with a second impedance. The first switch, the first memristor, the second switch and the second memristor are serially connected between a bit line and an inverted bit line in an alternate manner. The third switch is used for configuring the first impedance and the second impedance. The non-volatile memory device provided by the disclosure has a characteristic of quick access and the data stored therein does not require a dynamic update.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: December 6, 2016
    Assignees: Ningbo Advanced Memory Technology Corporation, Being Advanced Memory Taiwan Limited
    Inventors: Jia-Hwang Chang, Jui-Jen Wu, Sheng-Tsai Huang, Fan-Yi Jien
  • Patent number: 9488973
    Abstract: Provided are a PLC device and a method for controlling the same. The method includes: receiving input data from an external; storing the received input data in an input area of a data input/output unit; reading the input data from the input area of the data input/output unit in order to perform a calculation operation; storing output data, which is a result of the calculation operation, in an output area of the data input/output unit; and transmitting the output data in the output area of the data input/output unit to an output circuit.
    Type: Grant
    Filed: September 4, 2012
    Date of Patent: November 8, 2016
    Assignee: LSIS CO., LTD.
    Inventor: Jo Dong Park
  • Patent number: 9417282
    Abstract: A method for managing operation of a logic component is provided, with the logic component including a majority vote circuit and an odd number of flip-flops equal to at least three. The method includes, following a normal operating mode of the logic component, placing a flip-flop in a test mode, and injecting a test signal into a test input of the flip-flop being tested while a logic state of the other flip-flops is frozen. A test signal output is analyzed. At the end of the test, the logic component is placed back in the normal operating mode. The majority vote circuit restores a value of the output signal from the logic component that existed prior to initiation of the test.
    Type: Grant
    Filed: March 19, 2015
    Date of Patent: August 16, 2016
    Assignee: STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Jean-Marc Daveau, Sylvain Clerc, Philippe Roche
  • Patent number: 9384122
    Abstract: Embodiments of the invention are directed toward systems and/or methods that buffer data from various sensors with a high sampling rate in a semiconductor processing system. Such sampling can provide better data about the processing for diagnosing the conditions leading up to a processing fault in the system.
    Type: Grant
    Filed: June 6, 2013
    Date of Patent: July 5, 2016
    Assignee: APPLIED MATERIALS, INC.
    Inventor: Simon Yavelberg
  • Patent number: 9374219
    Abstract: A method and apparatus are described securely testing an integrated circuit (IC). When the IC is powered on, a first bit stream including unencrypted data bits and encrypted data bits is received by the IC, a second bit stream is generated based on a pseudorandom pattern, a third bit stream is generated by convolving the first bit stream with the second bit stream, the third bit stream is fed to at least one selected test data register (TDR), (i.e., a shift register), in the IC, a fourth bit stream is generated by delaying the second bit stream, and a fifth bit stream is generated by convolving a sixth bit stream output by the at least one selected TDR with the fourth bit stream. The fifth bit stream includes the same unencrypted data bits and encrypted data bits as the first bit stream.
    Type: Grant
    Filed: November 24, 2014
    Date of Patent: June 21, 2016
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Jason Doege
  • Patent number: 9362337
    Abstract: A non-volatile storage device adopt memristors to store data and uses fewer transistors to realize the same circuit function, whereby to decrease the chip area and reduce the time and energy spent in initiating the device. Further, the non-volatile storage device disposes appropriate electronic elements in the spacing between adjacent memristors to meet the layout design rule and achieve high space efficiency in the chip lest the space between memristors be wasted.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: June 7, 2016
    Assignees: NINGBO ADVANCED MEMORY TECHNOLOGY CORP., BEING ADVANCED MEMORY TAIWAN LIMITED
    Inventors: Jui-Jen Wu, Jiah-Wang Chang, Sheng-Tsai Huang, Fan-Yi Jien
  • Patent number: 9330793
    Abstract: A memory device includes a first memory block, a second memory block, a reception circuit configured to receiving a repair address and compression information, and a nonvolatile memory circuit including a first region for repairing the first memory block and a second region for repairing the second memory block, and configured to program the repair address in both the first region and the second region when the compression information represents high compression and program the repair address in either the first region or the second region when the compression information represents low compression.
    Type: Grant
    Filed: December 1, 2014
    Date of Patent: May 3, 2016
    Assignee: SK Hynix Inc.
    Inventors: Seon-Ki Cho, Yong-Ho Kong
  • Patent number: 9322868
    Abstract: A test circuit of a semiconductor integrated circuit includes a through via, a voltage driving unit, and a determination unit. The through via is charged by receiving an input voltage. The voltage driving unit generates a test voltage by charging or discharging the through via in response to a test control signal. The determination unit compares levels of the input voltage and the test voltage and outputs a resultant signal.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: April 26, 2016
    Assignee: SK Hynix Inc.
    Inventors: Sang Hoon Shin, Tae Yong Lee
  • Patent number: 9300275
    Abstract: In accordance with embodiments of the present disclosure, a multi-bit pulsed latch circuit for an integrated circuit design system may include a pulse generator and a plurality of latches. The pulse generator may be configured to generate pulses. The plurality of latches may operate as storage elements and are coupled to the pulse generator in a manner so that the multi-bit pulsed latch circuit provides functionality of at least two flip flop elements, wherein the multi-bit pulsed latch circuit can replace the at least two flip flop elements that normally would be used by the integrated circuit design system.
    Type: Grant
    Filed: July 24, 2014
    Date of Patent: March 29, 2016
    Assignee: Cirrus Logic, Inc.
    Inventors: Bhoodev Kumar, Saurabh Singh, Lei Zhu
  • Patent number: 9261557
    Abstract: A semiconductor apparatus includes a clock enable signal buffer unit configured to receive an input clock enable signal, and generate an output clock enable signal; a buffer control unit configured to generate a buffer enable signal in response to the output clock enable signal and a test enable signal; an input/output buffer unit configured to receive input patterns and generate output patterns; and a compression test unit configured to test the output patterns and the output clock enable signal according to the test enable signal.
    Type: Grant
    Filed: November 4, 2014
    Date of Patent: February 16, 2016
    Assignee: SK Hynix Inc.
    Inventors: Chang Hyun Lee, Young Jun Ku
  • Patent number: 9218049
    Abstract: In one embodiment, an integrated circuit includes a self calibration unit configured to iterate a test on a logic circuit in the integrated circuit at respectively lower supply voltage magnitudes until the test fails. A lowest supply voltage magnitude at which the test passes is used to generate a requested supply voltage magnitude for the integrated circuit. In an embodiment, an integrated circuit includes a series connection of logic gates physically distributed over an area of the integrated circuit, and a measurement unit configured to launch a logical transition into the series and detect a corresponding transition at the output of the series. The amount of time between the launch and the detection is used to request a supply voltage magnitude for the integrated circuit.
    Type: Grant
    Filed: June 12, 2013
    Date of Patent: December 22, 2015
    Assignee: Apple Inc.
    Inventor: Vincent R. von Kaenel
  • Patent number: 9208844
    Abstract: An integrated circuit receives a DDR (Double Data Rate) data signal and an associated DDR clock signal, and communicates those signals from integrated circuit input terminals a substantial distance across the integrated circuit to a subcircuit that then receives and uses the DDR data. Within the integrated circuit, a DDR retiming circuit receives the DDR data signal and the associated DDR clock signal from the terminals. The DDR retiming circuit splits the DDR data signal into two components, and then transmits those two components over the substantial distance toward the subcircuit. The subcircuit then recombines the two components back into a single DDR data signal and supplies the DDR data signal and the DDR clock signal to the subcircuit. The DDR data signal and the DDR clock signal are supplied to the subcircuit in such a way that setup and hold time requirements of the subcircuit are met.
    Type: Grant
    Filed: July 31, 2014
    Date of Patent: December 8, 2015
    Assignee: Netronome Systems, Inc.
    Inventors: Joseph M. Lamb, Chunli Cai, Ranjit D. Loboprabhu
  • Patent number: 9157960
    Abstract: Various embodiments comprise apparatuses and methods for testing and repairing through-substrate vias in a stack of interconnected dice. In various embodiments, an apparatus is provided that includes a number of through-substrate vias to couple to one or more devices, at least one redundant through-substrate via to allow a repair of the apparatus, and a pair of pull-up devices coupled to the through-substrate vias and the redundant through-substrate via to provide a high-data value to the first end of the respective through-substrate vias. A test register is coupled the second end of each of the through-substrate vias and the redundant through-substrate via to store a received version of the high-data value. A comparator compares the high-data value with the received version of the high-data value to test the through-substrate vias for short-circuit connections.
    Type: Grant
    Filed: March 2, 2012
    Date of Patent: October 13, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Venkatraghavan Bringivijayaraghavan, Jason M. Brown
  • Patent number: 9075112
    Abstract: A design-for-test (DFT) circuitry is disclosed. The DFT circuitry includes a first multiplexer operable to transfer one of a clock signal or an inverted clock signal based on a clock polarity control signal. The DFT circuitry also includes a burst counter coupled to the first multiplexer. The burst counter is operable to output a signal at a first logic state for a predefined pulse count. The DFT circuitry also includes a second multiplexer that is operable to output one of the clock polarity control signal or the clock signal according to a signal output from the burst counter. The DFT circuitry may also include a third multiplexer that forwards control signals identifying the predefined pulse count to the burst counter from different sources such as an external pin, a programmable interconnect, and a memory element.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: July 7, 2015
    Assignee: Altera Corporation
    Inventors: Kalyana Ravindra Kantipudi, Dhwani Shah, Jayabrata Ghosh Dastidar
  • Patent number: 9075669
    Abstract: Provided is a time series data processing device with which it is possible to change to a new process during the execution of an old process, and to control the selection and the output sequence of output data when processes are switched. A first processing unit executes a first process and generates first results data, and a second processing unit executes a second process and generates second results data. When an instruction to change processes is received from the outside, the first process in the first processing unit is stopped, and output of the first results data is prohibited. Then, the process in the first processing unit is changed from the first process to a third process and is started, and output of third results data is enabled.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: July 7, 2015
    Assignee: NEC CORPORATION
    Inventor: Masamichi Takagi
  • Patent number: 9041429
    Abstract: The disclosure relates generally to sequential state elements (SSEs), triple-mode redundant state machines (TMRSMs), and methods and systems for testing triple-mode redundant pipeline stages (TMRPSs) within the TMRSMs using triple-mode redundant SSEs (TMRSSEs). The SSEs, TMRSMs, TMRPSs, and TMRSSEs may be formed as integrated circuits on a semiconductor substrate. Of particular focus in this disclosure are SSEs used to sample and hold bit states. Embodiments of the SSEs have a self-correcting mechanism to protect against radiation-induced soft errors. The SSE may be provided in a pipeline circuit of a TMRSM to receive and store a bit state of a bit signal generated by combinational circuits within the pipeline circuit. More specifically, the SSEs may be provided in a TMRSSE configured to perform self-correction. Also disclosed are methods for using the TMRSSE to test redundant pipeline stages of the TMRSM.
    Type: Grant
    Filed: October 24, 2013
    Date of Patent: May 26, 2015
    Assignee: Arizona Board of Regents, a body corporate of the State of Arizona, acting for and on behalf of Arizona State University
    Inventor: Lawrence T. Clark
  • Patent number: 9041431
    Abstract: Embedded logic is implemented in a partially reconfigurable programmable logic device (PLD), thus allowing debugging of implemented instantiations of logic after partial reconfiguration. Several instantiations of logic are received at the PLD. One instantiation of logic is implemented in a reconfigurable region of logic within the PLD. The instantiation of logic includes a port that provides a constant interface between the reconfigurable region of logic and a fixed region of logic within the PLD. The port may receive signals from probe points implemented within the reconfigurable region of logic. The port may provide the signals to a signal interface implemented within a fixed region of logic. Furthermore, an embedded logic analyzer may be implemented in either the reconfigurable region of logic or the fixed region of logic. The embedded logic analyzer receives signals from the probe points and provides signal visibility to an external computing system.
    Type: Grant
    Filed: January 22, 2014
    Date of Patent: May 26, 2015
    Assignee: Altera Corporation
    Inventors: Alan Louis Herrmann, David W. Mendel
  • Patent number: 9018978
    Abstract: A novel configurable integrated circuit (IC) that has several configurable circuits for configurably performing different operations is provided. During the operation of the IC, each particular configurable circuit performs a particular operation that is specified by a particular configuration data set for the particular configurable circuit. While the IC operates and a first set of configurable circuits performs a first set of operations, configuration data is loaded from the outside of the IC for configuring a second set of configurable circuits. The configurable IC includes a configuration network for rapid loading configuration data in the IC from outside of the IC. The configuration network is a pipelined network.
    Type: Grant
    Filed: April 25, 2014
    Date of Patent: April 28, 2015
    Assignee: Tabula, Inc.
    Inventors: Brad Hutchings, Jason Redgrave, Teju Khubchandani, Herman Schmit, Steven Teig
  • Patent number: 8989660
    Abstract: Hardware interrupt functionality associated with a disable pin may be used to place a near-field communication (NFC) device into various operational modes. For example, various intermediate voltage windows may be defined within an I/O voltage domain and a resistive divider running off an I/O rail may generate multiple reference voltages within the I/O voltage domain. In one embodiment, different comparators may compare voltage on the disable pin to the reference voltages generated with the resistive divider to determine whether the voltage on the disable pin falls within one of the intermediate voltage windows. As such, if a particular comparator determines that the voltage on the disable pin falls within one of the intermediate voltage windows, a control signal may be generated to transition the NFC device into a corresponding operational mode.
    Type: Grant
    Filed: January 3, 2013
    Date of Patent: March 24, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Faramarz Sabouri, Haritha Eachempatti, Paul DenBoer
  • Publication number: 20150048863
    Abstract: A digital decoder, used in a reconfigurable circuit, for decoding digital pulses includes a phase indicator module having inputs coupled to a reference pulse input and a data pulse input. The phase indicator module has timing information outputs that provide logic values indicative of rising and falling edges of pulses occurring on the reference pulse input and the data pulse input. A phase decoder module has inputs coupled to the timing information outputs, and outputs decoded binary data values. In operation, the phase decoder module compares at least two of the logic values at the timing information outputs with a signal representative leading and trailing edges of a pulse applied to one of the phase inputs to determine a pulse arrival order sequence on the phase inputs and thereby provide the decoded binary data values.
    Type: Application
    Filed: May 14, 2014
    Publication date: February 19, 2015
    Inventors: Ling Wang, Huangsheng Ding, Shayan Zhang, Wanggen Zhang