With Test Facilitating Feature Patents (Class 326/16)
  • Patent number: 11037511
    Abstract: A display driver (10) includes a power supply circuit (60) that generates at least one power supply voltage, a drive circuit (20) that drives an electro-optical panel (150) based on the at least one power supply voltage, and a control circuit (50) that controls the power supply circuit (60) based on a control signal, a first monitoring circuit (M1) that monitors the control signal on the control circuit (50) side, and a second monitoring circuit (M2) that monitors the control signal on the power supply circuit (60) side.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: June 15, 2021
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Hironori Kobayashi
  • Patent number: 11023408
    Abstract: Systems, methods, and apparatus for communication over a serial bus in accordance with an I3C protocol are described that enable a slave device to request that a bus master device terminate a write transaction with the slave device. The serial bus may be operated according to an I3C single data rate protocol. In various aspects of the disclosure, a method performed at a master device coupled to a serial bus includes initiating a write transaction between the master device and a slave device, where the write transaction includes a plurality of data frames, and at least one data frame is configured with a transition bit in place of a parity bit. The method may include terminating the write transaction when the slave device drives a data line of the serial bus while receiving the transition bit.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: June 1, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Radu Pitigoi-Aron, Chandan Pramod Attarde, Richard Dominic Wietfeldt, Lalan Jee Mishra
  • Patent number: 11022639
    Abstract: An integrated circuit capable of on-chip jitter tolerance measurement includes a jitter generator circuit to produce a controlled amount of jitter that is injected into at least one clock signal, and a receive circuit to sample an input signal according to the at least one clock signal. The sampled data values output from the receiver are used to evaluate the integrated circuit's jitter tolerance.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: June 1, 2021
    Assignee: Rambus Inc.
    Inventors: Hae-Chang Lee, Jaeha Kim, Brian Leibowitz
  • Patent number: 11016928
    Abstract: A microcomputer is connected to a logic circuit. The microcomputer includes a monitoring unit monitoring the state of the logic circuit, a storage unit storing a plurality of information processing items executed by the microcomputer, and a processing unit executing a process on the basis of the state of the logic circuit and at least one information processing item selected from the plurality of information processing items on the basis of a communication frame inputted to the microcomputer.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: May 25, 2021
    Assignee: HITACHI AUTOMOTIVE SYSTEMS, LTD.
    Inventors: Satoshi Tsutsumi, Taisuke Ueta, Shuhei Kaneko, Kenichi Osada
  • Patent number: 10985739
    Abstract: A system comprises an electromagnetic pulse generation system that comprises a first pulse generation circuit, a second pulse generation circuit, and a mixing circuit. The electromagnetic pulse generation system is operable to output a first pulse generated by the first pulse generation circuit onto a first signal path, output a second pulse generated by the second pulse generation circuit onto the first signal path, generate a third pulse by mixing, via the mixing circuit, a fourth pulse generated by the first pulse generation circuit and a fifth pulse generated by the second pulse generation circuit, and output the third pulse on the first signal path.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: April 20, 2021
    Inventors: Yonatan Cohen, Nissim Ofek, Itamar Sivan
  • Patent number: 10921359
    Abstract: A provided impedance measuring semiconductor circuit can suppress the influence of sensors on the measurements of other sensors in the measurements of the sensors. According to an embodiment, an impedance measuring semiconductor circuit includes a first resistance element, an operational amplifier having a positive input terminal and an output terminal, the positive input terminal receiving a predetermined set voltage, the output terminal being coupled to one end of the first resistance element, a first output-side switch that electrically couples or decouples a first sensor and the other end of the first resistance element, a second output-side switch that electrically couples or decouples a second sensor and the other end of the first resistance element, a first input-side switch that electrically couples or decouples the first sensor and a negative input terminal, and a second input-side switch that electrically couples or decouples the second sensor and the negative input terminal.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: February 16, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Hiroto Suzuki
  • Patent number: 10861531
    Abstract: Apparatuses and methods for providing additional drive to multilevel signals representing data are described. An example apparatus includes a first driver section, a second driver section, and a third driver section. The first driver section is configured to drive an output terminal toward a first selected one of a first voltage and a second voltage. The second driver section configured to drive the output terminal toward a second selected one of the first voltage and the second voltage. The third driver section configured to drive the output terminal toward the first voltage when each of the first selected one and the second selected one is the first voltage. The third driver circuit is further configured to be in a high impedance state when the first selected one and the second selected one are different from each other.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: December 8, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Timothy M. Hollis, Dragos Dimitriu
  • Patent number: 10852353
    Abstract: An integrated circuit (IC) includes logic components and a scan test circuit coupled to the logic components. The IC also includes a scan input pin coupled to the scan test circuit. The IC also includes a scan input/output pin coupled to the scan test circuit. The scan test circuit includes a decoder coupled to at least one of the scan input pin and the scan input/output pin. The decoder includes storage elements configured to store different scan control signals and to output at least one of the different scan control signals in response to a master control signal.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: December 1, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Mudasir Shafat Kawoosa, Vishal Diwan
  • Patent number: 10847211
    Abstract: Various implementations described herein are directed to an integrated circuit having first latch circuitry with multiple first latches that latch multiple input data signals. The integrated circuit may include second latch circuitry having a single second latch that receives the latched multiple input data signals from the multiple first latches and outputs a single latched data signal based on the latched multiple input data signals. The integrated circuit may include intermediate logic circuitry that is coupled between the first latch circuitry and the second latch circuitry. The intermediate logic circuitry may receive and combine the multiple input data signals from the first latch circuitry into a single data signal that is provided to the single second latch of the second latch circuitry for output as the single latched data signal.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: November 24, 2020
    Assignee: Arm Limited
    Inventors: Andy Wangkun Chen, Teresa Louise McLaurin, Frank David Frederick, Richard Slobodnik, Yew Keong Chong
  • Patent number: 10848158
    Abstract: A configurable processor comprises at least an array of configurable computing elements (CCE's). Each CCE comprises at least a three-dimensional (3-D) memory (3D-M) array; an arithmetic logic circuit (ALC); and, a plurality of inter-storage-processor (ISP) connections. Not penetrating through any semiconductor substrate, the ISP-connections are short, small and numerous.
    Type: Grant
    Filed: November 24, 2019
    Date of Patent: November 24, 2020
    Assignees: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao Zhang
  • Patent number: 10825772
    Abstract: Some examples described herein relate to redundancy in a multi-chip stacked device. An example described herein is a multi-chip device. The multi-chip device includes a chip stack including vertically stacked chips. Neighboring pairs of the chips are directly connected together. Each of two or more of the chips includes a processing integrated circuit. The chip stack is configurable to operate a subset of functionality of the processing integrated circuits of the two or more of the chips when any portion of the processing integrated circuits is defective.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: November 3, 2020
    Inventors: Steven P. Young, Brian C. Gaide
  • Patent number: 10732654
    Abstract: An integrated circuit includes an input terminal, an input buffer circuit, an interface voltage control circuit, an output voltage selection circuit, an output driver circuit, and an output terminal. The input buffer circuit is coupled to the input terminal. The interface voltage control circuit is coupled to the input terminal. The output voltage selection circuit is coupled to the interface voltage control circuit. The output driver circuit is coupled to the output voltage selection circuit. The output terminal is coupled to the output driver circuit.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: August 4, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Richard Edwin Hubbard, Richard Sterling Broughton, Vijayalakshmi Devarajan
  • Patent number: 10734046
    Abstract: Apparatuses and methods for providing voltages to conductive lines between which clock signal lines are disposed are disclosed. Voltages provided to the conductive lines may provide voltage conditions for clock signals on the clock signal lines that are relatively the same for at least some of the clock edges of the clock signals. Having the same voltage conditions may mitigate variations in timing/phase between the clock signals due to different voltage influences when a clock signal transitions from a low clock level to a high clock level.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: August 4, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Katsuhiro Kitagawa, Akira Yamashita, Shuichi Murai, Kohei Nakamura
  • Patent number: 10673421
    Abstract: A level shifter device and an operation method thereof are provided. The level shifter device includes a buffer, a first level shifter and a dynamic voltage regulation circuit. The buffer includes an output terminal. The first level shifter has a first input terminal coupled to the output terminal of the buffer. The first level shifter has a reference voltage terminal coupled to an analog reference voltage. The dynamic voltage regulation circuit generates a dynamic voltage having a level varied according to a bounce of the analog reference voltage, and provides the dynamic voltage to at least one of the buffer as a power supply and the first level shifter as a bias voltage.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: June 2, 2020
    Assignee: Novatek Microelectronics Corp.
    Inventor: Yen-Cheng Cheng
  • Patent number: 10644892
    Abstract: The present disclosure relates to implementations of physically unclonable functions (PUFs) for cryptographic and authentication purposes. Specifically, the disclosure describes implementations of machine learning engines (MLEs) in conjunction with PUFs generating outputs having multiple states.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: May 5, 2020
    Assignee: ARIZONA BOARD OF REGENTS ON BEHALF OF NORTHERN ARIZONA UNIVERSITY
    Inventors: Fatemeh Afghah, Bertrand Francis Cambou
  • Patent number: 10469273
    Abstract: The present disclosure relates to implementations of physically unclonable functions (PUFs) for cryptographic and authentication purposes. Specifically, the disclosure describes implementations of machine learning engines (MLEs) in conjunction with PUFs generating outputs having multiple states.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: November 5, 2019
    Assignee: Arizona Board of Regents on Behalf of Northern Arizona University
    Inventors: Fatemeh Afghah, Bertrand Francis Cambou
  • Patent number: 10454477
    Abstract: A dynamic decode circuit for decoding a plurality of input signals to produce a positive output pulse one gate delay following a clock signal, wherein the output pulse indicates the plurality of signals were in a predetermined state, wherein the output pulse is active during an evaluation phase of a clock cycle and not active during a precharge phase of the clock cycle, wherein precharge is performed by nfet transistors.
    Type: Grant
    Filed: May 19, 2019
    Date of Patent: October 22, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Antonio Raffaele Pelella
  • Patent number: 10425081
    Abstract: To realize control of a system for which a high level of safety is demanded by one SRAM-type FPGA, it is to eliminate a possibility that an undesirable control signal is output to the outside of the FPGA because of influence of failure by a soft error and the like and a problem. To solve this problem, there is provided a hard macro having fixed circuitry structure, programmable logic arranged via an interval close to the hard macro and having a changeable circuitry structure, and an I/F circuit which is provided inside the programmable logic and outputs a processing result in the programmable logic to the hard macro. It is a characteristic that the I/F circuit monitors soundness of the programmable logic and stops output of the processing result to be transmitted to the hard macro on the basis of a monitoring result.
    Type: Grant
    Filed: January 28, 2015
    Date of Patent: September 24, 2019
    Assignee: Hitachi, Ltd.
    Inventors: Teruaki Sakata, Tsutomu Yamada, Teppei Hirotsu
  • Patent number: 10374604
    Abstract: A dynamic decode circuit for decoding a plurality of input signals to produce a positive output pulse one gate delay following a clock signal, wherein the output pulse indicates the plurality of signals were all positive, wherein the output pulse is active during an evaluation phase of a clock cycle and not active during a precharge phase of the clock cycle, wherein precharge is performed by nfet transistors.
    Type: Grant
    Filed: August 12, 2018
    Date of Patent: August 6, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Antonio Raffaele Pelella
  • Patent number: 10365328
    Abstract: A register array includes a plurality of groups of latches. Each of the groups of latches includes a first latch, a second latch, and a test latch connected to the first latch and the second latch. During functional operation the first latch and the second latch process data, in response to the same read/write clock signal supplied simultaneously to the first read/write clock input and the second read/write clock input. During test operation a skewed test clock signal of an original test clock signal is supplied at different timings to the first latch, the second latch, and the test latch, and a single scan signal is input to the first latch. The single scan signal cascades from the first latch through the test latch to the second latch, and is output by the second latch, within a single cycle of the original test clock signal.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: July 30, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jian Sun, Chao Meng, Xiaoxiao Li, Yinpeng Lu
  • Patent number: 10229081
    Abstract: An information handling system includes a receiver and a transmitter. A margin detector of the receiver derives an eye plot for signals received via a plurality of high speed serial lanes. A first control module of the receiver identifies a weakest lane of the high speed serial lanes, and compares eye plots for a signal on the weakest lane from one crosstalk minimization iteration to the next. A second control module of the transmitter receives a signal from the first control module indicating whether an eye plot of the signal has improved from one crosstalk minimization iteration to the next, and iteratively controls a phase shift of aggressor signals in the high speed serial lanes during each iteration until the eye plot of the signal remains the same from one iteration to the next. A phase shift module of the transmitter phase shifts the aggressor signals during each iteration.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: March 12, 2019
    Assignee: Dell Products, LP
    Inventors: Stuart Allen Berke, Bhyrav M. Mutnury, Vadhiraj Sankaranarayanan
  • Patent number: 10222417
    Abstract: Embodiments relate to providing security of scan mode access and data in an integrated circuit. In embodiments, one or both of two layers of security are provided. A first layer includes requiring a complex initialization sequence to be performed in order to access scan mode. A second layer includes scrambling the scan data before it is output from the circuit under test, which prevents unauthorized persons from extracting useful information from the output scan data. Further embodiments relate to methodologies for utilizing these protection layers after manufacture of the integrated circuit and incorporating these protection layers in an integrated circuit design flow.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: March 5, 2019
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Akhil Garg, Dale Meehl, Sahil Jain
  • Patent number: 10185633
    Abstract: This disclosure is directed to processor state integrity protection using hash verification. A device may comprise processing circuitry and memory circuitry. The processing circuity may be triggered to enter a secure mode. Prior to entering the secure mode, the processing circuitry may determine a processor state of the processing circuitry and a hash of the processor state, and store them in secured memory within the memory circuitry. Prior to exiting the secure mode, the processing circuitry may compute an updated hash of the stored processor state and compare it to the previously stored hash. If the updated hash and stored hash are determined to be the same, then the processing circuitry may restore the processor state and normal operation resumes. If the updated hash and stored hash are determined to be different, then the stored processor state may be compromised and the processing circuitry may perform at least one protective action.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: January 22, 2019
    Assignee: Intel Corporation
    Inventor: Rodrigo R. Branco
  • Patent number: 10101385
    Abstract: The disclosure describes a novel method and apparatus for improving interposers to include embedded monitoring instruments for real time monitoring digital signals, analog signals, voltage signals and temperature sensors located in the interposer. An embedded monitor trigger unit controls the starting and stopping of the real time monitoring operations. The embedded monitoring instruments are accessible via an 1149.1 TAP interface on the interposer.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: October 16, 2018
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 10097181
    Abstract: Apparatuses and methods for standby current control of a signal path in a semiconductor device are described. An example apparatus includes: first and second logic gates coupled in series; a first circuit coupled between the first logic gate and a power supply line that activates the first logic gate responsive to a first control signal; and a second circuit coupled between the second logic gate and the power supply line that activates the second logic gate responsive to a second control signal that is different from the first control signal.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: October 9, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Tetsuya Arai
  • Patent number: 10090060
    Abstract: According to one embodiment, a data communication system includes: a data transmitting device that transmits a test pattern; and a data receiving device that receives the test pattern. The data receiving device receives the test pattern with every change in a threshold for determining whether received data is High or Low, compares the test pattern to an expected value for the respective changed thresholds, and selects the threshold based on the result of comparison between the test pattern and the expected value.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: October 2, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Akihiro Fukushima, Shuji Matsumoto, Makoto Hara, Yasushi Yamakawa
  • Patent number: 10037259
    Abstract: Systems, methods, and apparatuses to perform an operation comprising receiving an indication of a first error in a processor, identifying a first control signal, of a plurality of control signals in a debug bus, associated with the error, wherein each of the plurality of control signals are coupled to one of a plurality of input ports of a multiplexer, and changing a configuration state of the multiplexer to output the first control signal to a trace array.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: July 31, 2018
    Assignee: International Business Machines Corporation
    Inventors: Khandker N. Adeeb, Steven J. Battle, Brandon R. Goddard, Dung Q. Nguyen, Tu-An T. Nguyen, Nicholas R. Orzol, Brian D. Victor, Brendan M. Wong
  • Patent number: 10001999
    Abstract: A new approach is proposed which contemplates system and method for configuring a plurality of configurable registers in a programmable digital processing engine of a network device. Under the proposed approach, one or more slave configuration controllers (SCC) are utilized to configure a large number of configurable registers in a programmable engine, wherein each SCC is used to configure a plurality of configurable registers, which are organized in multiple configuration groups. The configurable registers in each configuration group are connected in a looped one-way daisy chain. During its operation, each of the slave configuration controllers is configured to receive instructions from a user via a master configuration controller (MCC), performs read or write operations on the configurable registers of one of the configuration groups as designated by the instructions from the user.
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: June 19, 2018
    Assignee: Cavium, Inc.
    Inventors: Anh Tran, Gerald Schmidt, Harish Krishnamoorthy
  • Patent number: 9910676
    Abstract: Methods and apparatus are provided for controlling one or more memory devices connected to an input output (IO) circuit through a serial peripheral interface (SPI), to make any device which is in execute in place (XIP) mode exit XIP mode. An example method comprises driving an initial signal from the IO circuit onto the data pins for a first plurality of clock cycles, the initial signal causing any memory device not in XIP mode to treat subsequent signals as a dummy read, disabling a driving function of the IO circuit prior to a negative edge of a last one of the first plurality of clock cycles, stopping generation of clock signals for a transition waiting period after the first plurality of clock cycles, and activating a weak pull-up of the IO circuit to apply logic high on all of the data pins for a second plurality of clock cycles.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: March 6, 2018
    Assignee: MICROSEMI SOLUTIONS (U.S.), INC.
    Inventors: Unnikrishnan Sivaraman Nair, Sujaata Ramalingam
  • Patent number: 9899990
    Abstract: A semiconductor circuit includes a first circuit and a second circuit. The first circuit determines a logic level of a second node and a logic level of a third node, on the basis of a logic level of input data, a logic level of a clock signal, and a logic level of a first node. The second circuit determines the logic level of the first node, on the basis of the logic level of the clock signal, the logic level of the second node and the logic level of the third node. The first circuit comprises a sub-circuit and a first transistor. The first circuit determines the logic level of the second node, on the basis of the logic level of the input data and the logic level of the first node. The first transistor is gated to the logic level of the clock signal to connect the third node with the second node.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: February 20, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: San-Ha Kim, Min-Su Kim, Matthew Berzins
  • Patent number: 9851400
    Abstract: A system, apparatus, and method for testing blocks of a system on a chip (SOC) are described herein. An SOC, in accordance with various embodiments, may include a serial communication interface configured to multiplex, serialize, and/or parallelize signals streams from selected blocks of the SOC to an off-chip test unit through an off-chip serial communication interface. Other embodiments may be described and claimed.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: December 26, 2017
    Assignee: Marvell International Ltd.
    Inventors: Roger Longstreet, Vivek Raghunath Khanzode, Hongying Sheng
  • Patent number: 9825638
    Abstract: A virtual critical path (VCP) circuit is defined separate from an actual critical path circuit. The VCP operates in accordance with a special clock signal. The actual critical path circuit operates in accordance with a system clock signal. The VCP circuit has a signal timing characteristic substantially equal to that of the actual critical path circuit. The VCP circuit includes computational circuitry defined to compute an output value based on an input value, and comparison circuitry defined to compare the output value with an expected result value. A match between the output value computed by the VCP circuit and the expected result value indicates that a frequency of the special clock signal is acceptable. The VCP circuit is used to determine a maximum acceptable frequency of the special clock signal. A frequency of the system clock signal is then set to the maximum acceptable frequency of the special clock signal.
    Type: Grant
    Filed: March 5, 2014
    Date of Patent: November 21, 2017
    Assignee: Sandisk Technologies LLC
    Inventors: Yan Dumchin, Yair Baram, Michael Tomashev, Leonid Minz, Yevgeny Kaplan, Suzanna Zilberman
  • Patent number: 9817066
    Abstract: A circuit couples a test access port (TAP) having a JTAG interface to another port having a serial interface different from the JTAG interface. The circuit includes a forwarding circuit and a timing control circuit. The forward circuit is coupled to couple a test data in (TDI) terminal, a test data out (TDO) terminal, and a test clock (TCK) terminal of the TAP to an input terminal, an output terminal, and a clock terminal of the another port, respectively. The timing control circuit is coupled to drive a select terminal of the another port with a select signal that activates serial data transfer through the serial interface to a device. The timing control circuit delays assertion of the select signal by a configurable time period after assertion of a shift data state of a state machine of the TAP.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: November 14, 2017
    Assignee: XILINX, INC.
    Inventors: Randal M. Kuramoto, Stephanie Trapp, Matthew K. Nielson
  • Patent number: 9798842
    Abstract: An integrated circuit may include observable storage circuits and unobservable or non-observable storage circuits. Among values stored in the observable and the non-observable storage circuits, only the values stored in the observable storage circuits are accessible for read-back and/or write-back operations during hardware emulation. A computer system may receive a circuit design that includes a design-under-test and implement at least a portion of the circuit design in the integrated circuit. The computer system may insert observable storage circuits into the circuit design and couple the observable storage circuits to the non-observable storage circuits such that the data stored in the non-observable storage circuits may be accessed during read-back operations using the inserted observable storage circuits.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: October 24, 2017
    Assignee: Altera Corporation
    Inventor: Michael Hutton
  • Patent number: 9798599
    Abstract: An embodiment of a circuit includes a data latch and a plurality of cascaded latches, wherein a first of the plurality of cascaded latches is configured to receive a first signal from the data latch and each subsequent cascaded latch is configured to receive a data output signal of a preceding cascaded latch, and an error-detection circuit configured to receive the respective data output signals and detect error in operation of the cascaded latches based thereon.
    Type: Grant
    Filed: February 25, 2015
    Date of Patent: October 24, 2017
    Assignee: STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Chittoor Parthasarathy, Abhishek Jain
  • Patent number: 9793895
    Abstract: An electronic circuit includes: a first logic circuit coupled to a first input line and a first output line; a second logic circuit coupled to a second input line and a second output line; a first line pattern coupled to the first output line and including an input line different from the second input line; and a second line pattern coupled to the second output line and different from the first input line, wherein at least a part of the first output line, the first line pattern, the second output line, or the second line pattern has a folded shape or a circular shape.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: October 17, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Dai Yamamoto, Naoya Torii, Ikuya Morikawa
  • Patent number: 9729128
    Abstract: A multi-bit flip-flop (MBFF) includes a plurality of 1-bit flip-flops, each having an input data selection circuit that receives a data signal and a scan data signal. The MBFF also includes a local signal generation circuit that receives a global clock signal and a global scan enable signal, and in response, provides local control signals, wherein each of the local control signals is generated in response to both the global clock signal and the global scan enable signal. The local control signals are provided to the input data selection circuits, and exclusively control the input data selection circuits to route either the input data signal or the scan input data signal as a master data bit, reducing transistor requirements. Local clock signals may be generated by the local signal generation circuit in response to the global clock signal, and may exclusively control data transfer within the flip-flops, improving setup time.
    Type: Grant
    Filed: April 9, 2015
    Date of Patent: August 8, 2017
    Assignee: Synopsys, Inc.
    Inventors: Manish Srivastava, Basannagouda Somanath Reddy
  • Patent number: 9722615
    Abstract: In a multi-context PLD (dynamically reconfigurable circuit), at the time of rewriting configuration data on a non-selected context during circuit operation, configuration data is stably stored. At the time of rewriting configuration data on a non-selected context, writing to a row which is to be rewritten continues until input signals supplied to input terminals of routing switches in the row become “L” all that time or the input signals become “L” at least once. More specifically, a write selection signal for the row continues to be output. In addition, while the write selection signal is being output, loading of configuration data into a driver circuit is not conducted, or loading of configuration data into a driver circuit is conducted but storage thereof in a line buffer is not conducted.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: August 1, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yoshiyuki Kurokawa
  • Patent number: 9722612
    Abstract: Techniques are provided to permit a programmable logic device (PLD) to comply with a communication standard before the PLD is fully configured. In one example, a method includes programming a first portion of a programmable logic device (PLD) with first configuration data. After the first portion is programmed, the first portion is operated in accordance with a communication standard to exchange data with a host system while a second portion of the PLD is programmed with second configuration data.
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: August 1, 2017
    Assignee: Lattice Semiconductor Corporation
    Inventors: Umesh Ananthiah, Tramie Tran, Jamie Freed
  • Patent number: 9721626
    Abstract: A semiconductor apparatus includes a clock buffer and a reference voltage generation unit. The clock buffer generates an internal clock signal, based on first and second clock signals, in a first operation mode, and generates the internal clock signal, based on the first clock signal and a reference voltage, when a normal operation test is performed in a second operation mode. The reference voltage generation unit generates the reference voltage when the normal operation test is performed in the second operation mode.
    Type: Grant
    Filed: November 10, 2014
    Date of Patent: August 1, 2017
    Assignee: SK Hynix Inc.
    Inventor: Tae Jin Kang
  • Patent number: 9673789
    Abstract: A signal-generating circuit includes a first P-type transistor, a second P-type transistor, a first N-type transistor, a second N-type transistor, a first inverter, a second inverter, and a third inverter. The first P-type transistor supplies a supply voltage to a first node according to an input signal. Both of the second P-type transistor and the first N-type transistor couple the first node to a second node according to the input signal. The second N-type transistor couples the first node to a ground according to the input signal. The first inverter is coupled to the second node to generate a first signal. The second inverter is coupled between the first node and a third node. The third inverter is coupled to the third node to generate a second signal. The second signal and the first signal are the reverse of each other and synchronous.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: June 6, 2017
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
    Inventor: Jade Deng
  • Patent number: 9633156
    Abstract: In accordance with embodiments of the present disclosure, a multi-bit pulsed latch circuit for an integrated circuit design system may include a pulse generator and a plurality of latches. The pulse generator may be configured to generate pulses. The plurality of latches may operate as storage elements and are coupled to the pulse generator in a manner so that the multi-bit pulsed latch circuit provides functionality of at least two flip flop elements, wherein the multi-bit pulsed latch circuit can replace the at least two flip flop elements that normally would be used by the integrated circuit design system.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: April 25, 2017
    Assignee: Cirrus Logic, Inc.
    Inventors: Bhoodev Kumar, Saurabh Singh, Lei Zhu
  • Patent number: 9608567
    Abstract: A transceiver comprising a tank circuit, a variable differential conductance, VDC, coupled to the tank circuit, and a variable resistance coupled to the VDC is disclosed. The variable resistance is arranged to bias the VDC into a region of positive differential conductance during a first state of operation of the transceiver, and bias the VDC into a region of negative differential conductance during a second state of operation of the transceiver.
    Type: Grant
    Filed: May 30, 2011
    Date of Patent: March 28, 2017
    Assignee: Acconeer AB
    Inventors: Mikael Egard, Mats Ärlelid, Lars-Erik Wernersson
  • Patent number: 9557380
    Abstract: Scan flip-flop and associated method are provided. The scan flip-flop includes a data input terminal, a scan input terminal, a flip-flop circuit, a first transistor and a plurality of second transistors. A gate of the first transistor is coupled to the scan input terminal, gates of the second transistors are commonly coupled to an enabling signal, drains and sources of the first transistor and the second transistors are serially coupled to the flip-flop circuit, so as to increase a delay between the scan input terminal and the flip-flop circuit.
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: January 31, 2017
    Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sho-Mo Chen, Chien-Cheng Wu
  • Patent number: 9514817
    Abstract: A non-volatile memory device includes plural non-memory cells. Each non-volatile memory cell includes a first switch, a first memristor, a second switch, a second memristor and a third switch. The control terminal of the first switch is coupled to a word line. The first memristor is provided with a first impedance. The control terminal of the second switch is coupled to the word line. The second memristor is provided with a second impedance. The first switch, the first memristor, the second switch and the second memristor are serially connected between a bit line and an inverted bit line in an alternate manner. The third switch is used for configuring the first impedance and the second impedance. The non-volatile memory device provided by the disclosure has a characteristic of quick access and the data stored therein does not require a dynamic update.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: December 6, 2016
    Assignees: Ningbo Advanced Memory Technology Corporation, Being Advanced Memory Taiwan Limited
    Inventors: Jia-Hwang Chang, Jui-Jen Wu, Sheng-Tsai Huang, Fan-Yi Jien
  • Patent number: 9488973
    Abstract: Provided are a PLC device and a method for controlling the same. The method includes: receiving input data from an external; storing the received input data in an input area of a data input/output unit; reading the input data from the input area of the data input/output unit in order to perform a calculation operation; storing output data, which is a result of the calculation operation, in an output area of the data input/output unit; and transmitting the output data in the output area of the data input/output unit to an output circuit.
    Type: Grant
    Filed: September 4, 2012
    Date of Patent: November 8, 2016
    Assignee: LSIS CO., LTD.
    Inventor: Jo Dong Park
  • Patent number: 9417282
    Abstract: A method for managing operation of a logic component is provided, with the logic component including a majority vote circuit and an odd number of flip-flops equal to at least three. The method includes, following a normal operating mode of the logic component, placing a flip-flop in a test mode, and injecting a test signal into a test input of the flip-flop being tested while a logic state of the other flip-flops is frozen. A test signal output is analyzed. At the end of the test, the logic component is placed back in the normal operating mode. The majority vote circuit restores a value of the output signal from the logic component that existed prior to initiation of the test.
    Type: Grant
    Filed: March 19, 2015
    Date of Patent: August 16, 2016
    Assignee: STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Jean-Marc Daveau, Sylvain Clerc, Philippe Roche
  • Patent number: 9384122
    Abstract: Embodiments of the invention are directed toward systems and/or methods that buffer data from various sensors with a high sampling rate in a semiconductor processing system. Such sampling can provide better data about the processing for diagnosing the conditions leading up to a processing fault in the system.
    Type: Grant
    Filed: June 6, 2013
    Date of Patent: July 5, 2016
    Assignee: APPLIED MATERIALS, INC.
    Inventor: Simon Yavelberg
  • Patent number: 9374219
    Abstract: A method and apparatus are described securely testing an integrated circuit (IC). When the IC is powered on, a first bit stream including unencrypted data bits and encrypted data bits is received by the IC, a second bit stream is generated based on a pseudorandom pattern, a third bit stream is generated by convolving the first bit stream with the second bit stream, the third bit stream is fed to at least one selected test data register (TDR), (i.e., a shift register), in the IC, a fourth bit stream is generated by delaying the second bit stream, and a fifth bit stream is generated by convolving a sixth bit stream output by the at least one selected TDR with the fourth bit stream. The fifth bit stream includes the same unencrypted data bits and encrypted data bits as the first bit stream.
    Type: Grant
    Filed: November 24, 2014
    Date of Patent: June 21, 2016
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Jason Doege
  • Patent number: 9362337
    Abstract: A non-volatile storage device adopt memristors to store data and uses fewer transistors to realize the same circuit function, whereby to decrease the chip area and reduce the time and energy spent in initiating the device. Further, the non-volatile storage device disposes appropriate electronic elements in the spacing between adjacent memristors to meet the layout design rule and achieve high space efficiency in the chip lest the space between memristors be wasted.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: June 7, 2016
    Assignees: NINGBO ADVANCED MEMORY TECHNOLOGY CORP., BEING ADVANCED MEMORY TAIWAN LIMITED
    Inventors: Jui-Jen Wu, Jiah-Wang Chang, Sheng-Tsai Huang, Fan-Yi Jien