Abstract: Systems, methods, and apparatuses to perform an operation comprising receiving an indication of a first error in a processor, identifying a first control signal, of a plurality of control signals in a debug bus, associated with the error, wherein each of the plurality of control signals are coupled to one of a plurality of input ports of a multiplexer, and changing a configuration state of the multiplexer to output the first control signal to a trace array.

Abstract: A new approach is proposed which contemplates system and method for configuring a plurality of configurable registers in a programmable digital processing engine of a network device. Under the proposed approach, one or more slave configuration controllers (SCC) are utilized to configure a large number of configurable registers in a programmable engine, wherein each SCC is used to configure a plurality of configurable registers, which are organized in multiple configuration groups. The configurable registers in each configuration group are connected in a looped one-way daisy chain. During its operation, each of the slave configuration controllers is configured to receive instructions from a user via a master configuration controller (MCC), performs read or write operations on the configurable registers of one of the configuration groups as designated by the instructions from the user.

Abstract: Methods and apparatus are provided for controlling one or more memory devices connected to an input output (IO) circuit through a serial peripheral interface (SPI), to make any device which is in execute in place (XIP) mode exit XIP mode. An example method comprises driving an initial signal from the IO circuit onto the data pins for a first plurality of clock cycles, the initial signal causing any memory device not in XIP mode to treat subsequent signals as a dummy read, disabling a driving function of the IO circuit prior to a negative edge of a last one of the first plurality of clock cycles, stopping generation of clock signals for a transition waiting period after the first plurality of clock cycles, and activating a weak pull-up of the IO circuit to apply logic high on all of the data pins for a second plurality of clock cycles.

Abstract: A semiconductor circuit includes a first circuit and a second circuit. The first circuit determines a logic level of a second node and a logic level of a third node, on the basis of a logic level of input data, a logic level of a clock signal, and a logic level of a first node. The second circuit determines the logic level of the first node, on the basis of the logic level of the clock signal, the logic level of the second node and the logic level of the third node. The first circuit comprises a sub-circuit and a first transistor. The first circuit determines the logic level of the second node, on the basis of the logic level of the input data and the logic level of the first node. The first transistor is gated to the logic level of the clock signal to connect the third node with the second node.

Abstract: A system, apparatus, and method for testing blocks of a system on a chip (SOC) are described herein. An SOC, in accordance with various embodiments, may include a serial communication interface configured to multiplex, serialize, and/or parallelize signals streams from selected blocks of the SOC to an off-chip test unit through an off-chip serial communication interface. Other embodiments may be described and claimed.

Abstract: A virtual critical path (VCP) circuit is defined separate from an actual critical path circuit. The VCP operates in accordance with a special clock signal. The actual critical path circuit operates in accordance with a system clock signal. The VCP circuit has a signal timing characteristic substantially equal to that of the actual critical path circuit. The VCP circuit includes computational circuitry defined to compute an output value based on an input value, and comparison circuitry defined to compare the output value with an expected result value. A match between the output value computed by the VCP circuit and the expected result value indicates that a frequency of the special clock signal is acceptable. The VCP circuit is used to determine a maximum acceptable frequency of the special clock signal. A frequency of the system clock signal is then set to the maximum acceptable frequency of the special clock signal.

Abstract: A circuit couples a test access port (TAP) having a JTAG interface to another port having a serial interface different from the JTAG interface. The circuit includes a forwarding circuit and a timing control circuit. The forward circuit is coupled to couple a test data in (TDI) terminal, a test data out (TDO) terminal, and a test clock (TCK) terminal of the TAP to an input terminal, an output terminal, and a clock terminal of the another port, respectively. The timing control circuit is coupled to drive a select terminal of the another port with a select signal that activates serial data transfer through the serial interface to a device. The timing control circuit delays assertion of the select signal by a configurable time period after assertion of a shift data state of a state machine of the TAP.

Abstract: An embodiment of a circuit includes a data latch and a plurality of cascaded latches, wherein a first of the plurality of cascaded latches is configured to receive a first signal from the data latch and each subsequent cascaded latch is configured to receive a data output signal of a preceding cascaded latch, and an error-detection circuit configured to receive the respective data output signals and detect error in operation of the cascaded latches based thereon.

Abstract: An integrated circuit may include observable storage circuits and unobservable or non-observable storage circuits. Among values stored in the observable and the non-observable storage circuits, only the values stored in the observable storage circuits are accessible for read-back and/or write-back operations during hardware emulation. A computer system may receive a circuit design that includes a design-under-test and implement at least a portion of the circuit design in the integrated circuit. The computer system may insert observable storage circuits into the circuit design and couple the observable storage circuits to the non-observable storage circuits such that the data stored in the non-observable storage circuits may be accessed during read-back operations using the inserted observable storage circuits.

Abstract: An electronic circuit includes: a first logic circuit coupled to a first input line and a first output line; a second logic circuit coupled to a second input line and a second output line; a first line pattern coupled to the first output line and including an input line different from the second input line; and a second line pattern coupled to the second output line and different from the first input line, wherein at least a part of the first output line, the first line pattern, the second output line, or the second line pattern has a folded shape or a circular shape.

Abstract: A multi-bit flip-flop (MBFF) includes a plurality of 1-bit flip-flops, each having an input data selection circuit that receives a data signal and a scan data signal. The MBFF also includes a local signal generation circuit that receives a global clock signal and a global scan enable signal, and in response, provides local control signals, wherein each of the local control signals is generated in response to both the global clock signal and the global scan enable signal. The local control signals are provided to the input data selection circuits, and exclusively control the input data selection circuits to route either the input data signal or the scan input data signal as a master data bit, reducing transistor requirements. Local clock signals may be generated by the local signal generation circuit in response to the global clock signal, and may exclusively control data transfer within the flip-flops, improving setup time.

Abstract: In a multi-context PLD (dynamically reconfigurable circuit), at the time of rewriting configuration data on a non-selected context during circuit operation, configuration data is stably stored. At the time of rewriting configuration data on a non-selected context, writing to a row which is to be rewritten continues until input signals supplied to input terminals of routing switches in the row become “L” all that time or the input signals become “L” at least once. More specifically, a write selection signal for the row continues to be output. In addition, while the write selection signal is being output, loading of configuration data into a driver circuit is not conducted, or loading of configuration data into a driver circuit is conducted but storage thereof in a line buffer is not conducted.

Abstract: Techniques are provided to permit a programmable logic device (PLD) to comply with a communication standard before the PLD is fully configured. In one example, a method includes programming a first portion of a programmable logic device (PLD) with first configuration data. After the first portion is programmed, the first portion is operated in accordance with a communication standard to exchange data with a host system while a second portion of the PLD is programmed with second configuration data.

Abstract: A semiconductor apparatus includes a clock buffer and a reference voltage generation unit. The clock buffer generates an internal clock signal, based on first and second clock signals, in a first operation mode, and generates the internal clock signal, based on the first clock signal and a reference voltage, when a normal operation test is performed in a second operation mode. The reference voltage generation unit generates the reference voltage when the normal operation test is performed in the second operation mode.

Abstract: A signal-generating circuit includes a first P-type transistor, a second P-type transistor, a first N-type transistor, a second N-type transistor, a first inverter, a second inverter, and a third inverter. The first P-type transistor supplies a supply voltage to a first node according to an input signal. Both of the second P-type transistor and the first N-type transistor couple the first node to a second node according to the input signal. The second N-type transistor couples the first node to a ground according to the input signal. The first inverter is coupled to the second node to generate a first signal. The second inverter is coupled between the first node and a third node. The third inverter is coupled to the third node to generate a second signal. The second signal and the first signal are the reverse of each other and synchronous.

Abstract: In accordance with embodiments of the present disclosure, a multi-bit pulsed latch circuit for an integrated circuit design system may include a pulse generator and a plurality of latches. The pulse generator may be configured to generate pulses. The plurality of latches may operate as storage elements and are coupled to the pulse generator in a manner so that the multi-bit pulsed latch circuit provides functionality of at least two flip flop elements, wherein the multi-bit pulsed latch circuit can replace the at least two flip flop elements that normally would be used by the integrated circuit design system.

Abstract: A transceiver comprising a tank circuit, a variable differential conductance, VDC, coupled to the tank circuit, and a variable resistance coupled to the VDC is disclosed. The variable resistance is arranged to bias the VDC into a region of positive differential conductance during a first state of operation of the transceiver, and bias the VDC into a region of negative differential conductance during a second state of operation of the transceiver.

Abstract: Scan flip-flop and associated method are provided. The scan flip-flop includes a data input terminal, a scan input terminal, a flip-flop circuit, a first transistor and a plurality of second transistors. A gate of the first transistor is coupled to the scan input terminal, gates of the second transistors are commonly coupled to an enabling signal, drains and sources of the first transistor and the second transistors are serially coupled to the flip-flop circuit, so as to increase a delay between the scan input terminal and the flip-flop circuit.

Abstract: A non-volatile memory device includes plural non-memory cells. Each non-volatile memory cell includes a first switch, a first memristor, a second switch, a second memristor and a third switch. The control terminal of the first switch is coupled to a word line. The first memristor is provided with a first impedance. The control terminal of the second switch is coupled to the word line. The second memristor is provided with a second impedance. The first switch, the first memristor, the second switch and the second memristor are serially connected between a bit line and an inverted bit line in an alternate manner. The third switch is used for configuring the first impedance and the second impedance. The non-volatile memory device provided by the disclosure has a characteristic of quick access and the data stored therein does not require a dynamic update.

Abstract: Provided are a PLC device and a method for controlling the same. The method includes: receiving input data from an external; storing the received input data in an input area of a data input/output unit; reading the input data from the input area of the data input/output unit in order to perform a calculation operation; storing output data, which is a result of the calculation operation, in an output area of the data input/output unit; and transmitting the output data in the output area of the data input/output unit to an output circuit.

Abstract: A method for managing operation of a logic component is provided, with the logic component including a majority vote circuit and an odd number of flip-flops equal to at least three. The method includes, following a normal operating mode of the logic component, placing a flip-flop in a test mode, and injecting a test signal into a test input of the flip-flop being tested while a logic state of the other flip-flops is frozen. A test signal output is analyzed. At the end of the test, the logic component is placed back in the normal operating mode. The majority vote circuit restores a value of the output signal from the logic component that existed prior to initiation of the test.

Abstract: Embodiments of the invention are directed toward systems and/or methods that buffer data from various sensors with a high sampling rate in a semiconductor processing system. Such sampling can provide better data about the processing for diagnosing the conditions leading up to a processing fault in the system.

Abstract: A method and apparatus are described securely testing an integrated circuit (IC). When the IC is powered on, a first bit stream including unencrypted data bits and encrypted data bits is received by the IC, a second bit stream is generated based on a pseudorandom pattern, a third bit stream is generated by convolving the first bit stream with the second bit stream, the third bit stream is fed to at least one selected test data register (TDR), (i.e., a shift register), in the IC, a fourth bit stream is generated by delaying the second bit stream, and a fifth bit stream is generated by convolving a sixth bit stream output by the at least one selected TDR with the fourth bit stream. The fifth bit stream includes the same unencrypted data bits and encrypted data bits as the first bit stream.

Abstract: A non-volatile storage device adopt memristors to store data and uses fewer transistors to realize the same circuit function, whereby to decrease the chip area and reduce the time and energy spent in initiating the device. Further, the non-volatile storage device disposes appropriate electronic elements in the spacing between adjacent memristors to meet the layout design rule and achieve high space efficiency in the chip lest the space between memristors be wasted.

Abstract: A memory device includes a first memory block, a second memory block, a reception circuit configured to receiving a repair address and compression information, and a nonvolatile memory circuit including a first region for repairing the first memory block and a second region for repairing the second memory block, and configured to program the repair address in both the first region and the second region when the compression information represents high compression and program the repair address in either the first region or the second region when the compression information represents low compression.

Abstract: A test circuit of a semiconductor integrated circuit includes a through via, a voltage driving unit, and a determination unit. The through via is charged by receiving an input voltage. The voltage driving unit generates a test voltage by charging or discharging the through via in response to a test control signal. The determination unit compares levels of the input voltage and the test voltage and outputs a resultant signal.

Abstract: In accordance with embodiments of the present disclosure, a multi-bit pulsed latch circuit for an integrated circuit design system may include a pulse generator and a plurality of latches. The pulse generator may be configured to generate pulses. The plurality of latches may operate as storage elements and are coupled to the pulse generator in a manner so that the multi-bit pulsed latch circuit provides functionality of at least two flip flop elements, wherein the multi-bit pulsed latch circuit can replace the at least two flip flop elements that normally would be used by the integrated circuit design system.

Abstract: A semiconductor apparatus includes a clock enable signal buffer unit configured to receive an input clock enable signal, and generate an output clock enable signal; a buffer control unit configured to generate a buffer enable signal in response to the output clock enable signal and a test enable signal; an input/output buffer unit configured to receive input patterns and generate output patterns; and a compression test unit configured to test the output patterns and the output clock enable signal according to the test enable signal.

Abstract: In one embodiment, an integrated circuit includes a self calibration unit configured to iterate a test on a logic circuit in the integrated circuit at respectively lower supply voltage magnitudes until the test fails. A lowest supply voltage magnitude at which the test passes is used to generate a requested supply voltage magnitude for the integrated circuit. In an embodiment, an integrated circuit includes a series connection of logic gates physically distributed over an area of the integrated circuit, and a measurement unit configured to launch a logical transition into the series and detect a corresponding transition at the output of the series. The amount of time between the launch and the detection is used to request a supply voltage magnitude for the integrated circuit.

Abstract: An integrated circuit receives a DDR (Double Data Rate) data signal and an associated DDR clock signal, and communicates those signals from integrated circuit input terminals a substantial distance across the integrated circuit to a subcircuit that then receives and uses the DDR data. Within the integrated circuit, a DDR retiming circuit receives the DDR data signal and the associated DDR clock signal from the terminals. The DDR retiming circuit splits the DDR data signal into two components, and then transmits those two components over the substantial distance toward the subcircuit. The subcircuit then recombines the two components back into a single DDR data signal and supplies the DDR data signal and the DDR clock signal to the subcircuit. The DDR data signal and the DDR clock signal are supplied to the subcircuit in such a way that setup and hold time requirements of the subcircuit are met.

Abstract: Various embodiments comprise apparatuses and methods for testing and repairing through-substrate vias in a stack of interconnected dice. In various embodiments, an apparatus is provided that includes a number of through-substrate vias to couple to one or more devices, at least one redundant through-substrate via to allow a repair of the apparatus, and a pair of pull-up devices coupled to the through-substrate vias and the redundant through-substrate via to provide a high-data value to the first end of the respective through-substrate vias. A test register is coupled the second end of each of the through-substrate vias and the redundant through-substrate via to store a received version of the high-data value. A comparator compares the high-data value with the received version of the high-data value to test the through-substrate vias for short-circuit connections.

Abstract: A design-for-test (DFT) circuitry is disclosed. The DFT circuitry includes a first multiplexer operable to transfer one of a clock signal or an inverted clock signal based on a clock polarity control signal. The DFT circuitry also includes a burst counter coupled to the first multiplexer. The burst counter is operable to output a signal at a first logic state for a predefined pulse count. The DFT circuitry also includes a second multiplexer that is operable to output one of the clock polarity control signal or the clock signal according to a signal output from the burst counter. The DFT circuitry may also include a third multiplexer that forwards control signals identifying the predefined pulse count to the burst counter from different sources such as an external pin, a programmable interconnect, and a memory element.

Abstract: Provided is a time series data processing device with which it is possible to change to a new process during the execution of an old process, and to control the selection and the output sequence of output data when processes are switched. A first processing unit executes a first process and generates first results data, and a second processing unit executes a second process and generates second results data. When an instruction to change processes is received from the outside, the first process in the first processing unit is stopped, and output of the first results data is prohibited. Then, the process in the first processing unit is changed from the first process to a third process and is started, and output of third results data is enabled.

Abstract: Embedded logic is implemented in a partially reconfigurable programmable logic device (PLD), thus allowing debugging of implemented instantiations of logic after partial reconfiguration. Several instantiations of logic are received at the PLD. One instantiation of logic is implemented in a reconfigurable region of logic within the PLD. The instantiation of logic includes a port that provides a constant interface between the reconfigurable region of logic and a fixed region of logic within the PLD. The port may receive signals from probe points implemented within the reconfigurable region of logic. The port may provide the signals to a signal interface implemented within a fixed region of logic. Furthermore, an embedded logic analyzer may be implemented in either the reconfigurable region of logic or the fixed region of logic. The embedded logic analyzer receives signals from the probe points and provides signal visibility to an external computing system.

Abstract: The disclosure relates generally to sequential state elements (SSEs), triple-mode redundant state machines (TMRSMs), and methods and systems for testing triple-mode redundant pipeline stages (TMRPSs) within the TMRSMs using triple-mode redundant SSEs (TMRSSEs). The SSEs, TMRSMs, TMRPSs, and TMRSSEs may be formed as integrated circuits on a semiconductor substrate. Of particular focus in this disclosure are SSEs used to sample and hold bit states. Embodiments of the SSEs have a self-correcting mechanism to protect against radiation-induced soft errors. The SSE may be provided in a pipeline circuit of a TMRSM to receive and store a bit state of a bit signal generated by combinational circuits within the pipeline circuit. More specifically, the SSEs may be provided in a TMRSSE configured to perform self-correction. Also disclosed are methods for using the TMRSSE to test redundant pipeline stages of the TMRSM.

Abstract: A novel configurable integrated circuit (IC) that has several configurable circuits for configurably performing different operations is provided. During the operation of the IC, each particular configurable circuit performs a particular operation that is specified by a particular configuration data set for the particular configurable circuit. While the IC operates and a first set of configurable circuits performs a first set of operations, configuration data is loaded from the outside of the IC for configuring a second set of configurable circuits. The configurable IC includes a configuration network for rapid loading configuration data in the IC from outside of the IC. The configuration network is a pipelined network.

Abstract: Hardware interrupt functionality associated with a disable pin may be used to place a near-field communication (NFC) device into various operational modes. For example, various intermediate voltage windows may be defined within an I/O voltage domain and a resistive divider running off an I/O rail may generate multiple reference voltages within the I/O voltage domain. In one embodiment, different comparators may compare voltage on the disable pin to the reference voltages generated with the resistive divider to determine whether the voltage on the disable pin falls within one of the intermediate voltage windows. As such, if a particular comparator determines that the voltage on the disable pin falls within one of the intermediate voltage windows, a control signal may be generated to transition the NFC device into a corresponding operational mode.

Abstract: A digital decoder, used in a reconfigurable circuit, for decoding digital pulses includes a phase indicator module having inputs coupled to a reference pulse input and a data pulse input. The phase indicator module has timing information outputs that provide logic values indicative of rising and falling edges of pulses occurring on the reference pulse input and the data pulse input. A phase decoder module has inputs coupled to the timing information outputs, and outputs decoded binary data values. In operation, the phase decoder module compares at least two of the logic values at the timing information outputs with a signal representative leading and trailing edges of a pulse applied to one of the phase inputs to determine a pulse arrival order sequence on the phase inputs and thereby provide the decoded binary data values.

Abstract: A semiconductor device capable of reconfiguration, including: a plurality of logic units which configure an array and are connected to each other, wherein each logic unit includes a pair of a first and a second memory cell units, each of the first and the second memory cell units operates as a logic element when truth value table data is written in, which is configured so that a logic calculation of an input value specified by a plurality of addresses is output to a data line, and/or operates as a connection element when truth value table data is written in, which is configured so that an input value specified by a certain address is output to a data line to be connected to an address of another memory cell unit, a latter stage of the first memory cell unit includes a sequential circuit which synchronizes with a clock, and the logic units include, for each pair of the first and the second memory cell units, a selection unit which selectively outputs an address to the first or the second memory cell unit in ac

Abstract: An integrated circuit device includes a first signal line for distributing a first signal. The first signal line includes a plurality of branch lines, and a leaf node is defined at an end of each branch line. First logic is coupled to the leaf nodes and operable to generate a first status signal indicative of a collective first logic state of the leaf nodes of the signal line corresponding to the first signal.

Abstract: Selective blocking is applied to discrete segments of scan chains in the integrated circuit device. In some implementations, locking components associated with the scan segments are selectively activated according to blocking data incorporated in test pattern data. In other implementations, selective blocking is applied to the scan cells identified as causing the highest power consumption. Selective incorporation of blocking components in an integrated circuit device is based on statistical estimation of scan cell transition rates. When the blocking components are enabled, pre-selected signal values are presented to the functional logic of the integrated circuit device. At the same time, propagation of output value transitions that may take place in the scan cells is prevented.

Abstract: What is disclosed is a wireless push button device. The wireless push button device includes a user interface configured to receive user input to control a process of a machine system. The wireless push button device also includes a first transceiver coupled to the user interface and configured to wirelessly receive input power from a second transceiver, provide user power to the user interface, and wirelessly transfer communications related to the user input to the second transceiver. The wireless push button device also includes a processing system configured to determine when a power transfer problem exists between the second transceiver and the first transceiver, and transfer an alert in response to the power transfer problem.

Abstract: A semiconductor integrated circuit capable of testing power control operation in the semiconductor integrated circuit includes a power controllable region. Power control switches have switch series each constituted by a plurality of switch cells. A power controllable region includes output nodes in the switch series. The output nodes output power control signals that have passed through final stages of the respective switch series of the power control switches to outside the power controllable region. A chip on which the semiconductor integrated circuit is mounted has output terminals that output outputs of the output nodes to outside of the chip. When inserting a scan path test, observation flip-flops that load the outputs of the output nodes to data terminals, and load scan data to scan-in terminals are disposed in correspondence with the respective output nodes. Those observation flip-flops are connected to constitute a scan path chain.

Abstract: A dual flip-flop circuit combines two or more flip-flip sub-circuits into a single circuit. The flip-flop circuit comprises a first flip-flop sub-circuit and a second flip-flop sub-circuit. The first flip-flop sub-circuit comprises a first storage sub-circuit configured to store a first selected input signal and transfer the first selected input signal to a first output signal when a buffered clock signal transitions between two different logic levels and a dock driver configured to receive a clock input signal, generate an inverted clock signal, and generate the buffered clock signal. The second flip-flop sub-circuit is coupled to the clock driver and configured to receive the inverted clock signal and the buffered clock signal. The second flip-flop sub-circuit comprises a second storage sub-circuit configured to store a second selected input signal and transfer the second selected input signal to a second output signal when the buffered clock signal transitions.

Abstract: A system for scalable voltage ramp control for power supply systems. A system may comprise at least power supply circuitry, digital-to-analog (D/A) converter circuitry and a controller. The power supply circuitry may be configured to output a voltage to a load based on an input voltage provided by the D/A converter. The controller may be configured to control the D/A converter (e.g., to cause the D/A converter to provide the input voltage to the power supply circuitry) using a large range voltage ramp-up or a small range voltage ramp-up. Utilization of the large range voltage ramp-up or the small range voltage ramp-up by the controller may be based on, for example, a threshold voltage.

Abstract: A circuit and method of directly measuring the Single Event Transient (SET) performance of a combinatorial circuit includes a measurement chain. The measurement chain includes a plurality of cells, each in turn including a pair of SR latches, a dual-input inverter, and a target. During measurement and testing, the targets are irradiated, and a pulse signal caused by an SET event is allowed to propagate through the measurement chain only if the pair of SR latches are active at the same time. The pulse signal is latched by the measurement chain, thus allowing the presence of an SET event to be detected.

Abstract: Providing for a field programmable gate array (FPGA) utilizing resistive random access memory (RRAM) technology is described herein. By way of example, the FPGA can comprise a switching block interconnect having parallel signal input lines crossed by perpendicular signal output lines. RRAM memory cells can be formed at respective intersections of the signal input lines and signal output lines. The RRAM memory cell can include a voltage divider comprising multiple programmable resistive elements arranged electrically in series across a VCC and VSS of the FPGA. A common node of the voltage divider drives a gate of a pass gate transistor configured to activate or deactivate the intersection. The disclosed RRAM memory can provide high transistor density, high logic utilization, fast programming speed, radiation immunity, fast power up and significant benefits for FPGA technology.

Abstract: A method for testing a set of circuitry in an integrated circuit (IC) is described. The IC includes multiple configurable circuits for configurably performing multiple operations. The method configures the IC to operate in a user mode with a set of test paths that satisfies a set of evaluation criteria. Each test path includes a controllable storage element for controllably storing a signal that the storage element receives. The method operates the IC in user mode. The method reads the values stored in the storage elements to determine whether the set of circuitry is operating within specified performance limits.

Abstract: The disclosure relates generally to triple-redundant sequential state (TRSS) machines formed as integrated circuits on a semiconductor substrate, such as CMOS, and computerized methods and systems of designing the triple-redundant sequential state machines. Of particular focus in this disclosure are sequential state elements (SSEs) used to sample and hold bit states. The sampling and holding of bits states are synchronized by a clock signal thereby allowing for pipelining in the TRSS machines. In particular, the clock signal may oscillate between a first clock state and a second clock state to synchronize the operation of the SSE according to the timing provided by the clock states. The SSEs have a self-correcting mechanism to protect against radiation induced soft errors. The SSE may be provided in a pipeline circuit of a TRSS machine to receive and store a bit state of bit signal generated by combinational circuits within the pipeline circuit.

Abstract: An integrated circuit having a monitor circuit for monitoring timing in a critical path having a target timing margin is disclosed. The monitor circuit has two shift registers, one of which includes a delay element that applies a delay value to a received signal. The inputs to the two shift registers form a signal input node capable of receiving an input signal. The monitor circuit also has a logic gate having an output and at least two inputs, each input connected to a corresponding one of the outputs of the two shift registers. The output of the logic gate indicates whether the target timing margin is satisfied or not satisfied.