Abstract: According to a first aspect of the present invention there is provided a digital signal processing circuit, one or more switches of the circuit being provided by an ion sensitive field effect transistor.

Abstract: A disclosed semiconductor integrated circuit device includes a logic circuit, a memory circuit to which data are written by the logic circuit and from which the data are read by the logic circuit, a register circuit holding the data when the logic circuit writes the data to the memory circuit, and a selector circuit selecting one of data output from the register circuit and data output from the memory circuit, and outputting the selected data to the logic circuit. Further in the semiconductor integrated circuit device, in an operational test of the logic circuit, the selector circuit selects the data output from the register circuit and outputs the selected data to the logic circuit.

Abstract: An improved configuration for a programmable logic device and an improved method for configuration of a programmable logic device are provided. A programmable logic device such as field programmable logic device is configured to include an application logic, an embedded test logic that monitors the application logic, and an access control logic that grants access to an external device to embedded test data provided that an access control requirement is met that is based upon a key stored in a memory and information received from the external device.

Abstract: A Programmable Logic Device (PLD) structure using third dimensional memory is disclosed. The PLD structure includes a switch configured to couple a polarity of a signal (e.g., an input signal applied to an input) to a routing line and a non-volatile register configured to control the switch. The non-volatile register may include a non-volatile memory element, such as a third dimension memory element. The non-volatile memory element may be a two-terminal memory element that retains stored data in the absence of power and stores data as a plurality of conductivity profiles that can be non-destructively sensed by applying a read voltage across the two terminals. New data can be written to the two-terminal memory element by applying a write voltage across the two terminals. Logic and other active circuitry can be positioned in a substrate and the non-volatile memory element can be positioned on top of the substrate.

Abstract: Some embodiments of the invention provide a configurable integrated circuit (IC) that includes several configurable circuits grouped in several tiles. The configurable IC also includes a configuration network for loading configuration data into the IC, where the configuration data is for configuring several of the configurable circuit. In some embodiments, the configuration network includes several registers at several boundaries between the tiles, where the registers allow multiple configuration data sets to be routed to multiple tiles concurrently. The configuration network in some embodiments includes several address counters at several tiles, where each address counter allows one address to be loaded for a tile and then to be successively incremented based on increment instructions sent over the configuration network. At least, two different addresses specified by an address counter of a particular tile identify two different resources within the particular tile.

Abstract: Embodiments of the invention include an electrical circuit arrangement including a switchably removable bond pad extension test pad that allows improved testing of a corresponding electrical circuit device via enhanced placement of testing probes. The bond pad extension test pad is removably coupled to one of the electrical circuit device's electrical components, e.g., a bond pad. Because the bond pad extension test pad can be disconnected from the electrical component when not testing, the bond pad extension test pad does not contribute additional parasitic effects to the corresponding electrical circuit device. The electrical circuit arrangement automatically detects when a testing voltage is applied to the bond pad extension test pad, then connects the bond pad extension test pad in response to the detection of the applied testing voltage.

Abstract: In a semiconductor device, when a voltage regulator is halted from operating and a test supply voltage is supplied to second logics, the device is initialized by a reset signal. A register included in the device is then reset by an input signal via first logics. The voltage regulator is halted by a power-down signal. Testing is then carried out as the test supply voltage is applied to the second logics. When plural test items are executed successively, a test reset signal is applied to a test reset terminal for each item. As the initialized state of the register is canceled, the first and second logics are initialized.

Abstract: A method and eFuse circuit for implementing enhanced security features using eFuses, such as disabling selected predefined test, debug, and mission security functions used in application-specific integrated circuits (ASICs), and a design structure on which the subject circuit resides are provided. The eFuse circuit includes a plurality of eFuses, a sense amplifier coupled to the plurality of eFuses, and a plurality of sense output latches coupled to the sense amplifier. The plurality of sense output latches is arranged to have a bias to power up to a known value. Control logic coupled to the plurality of sense output latches provides at least one predefined control signal responsive to the known value of the plurality of sense output latches, which enables a selected predefined security function. The plurality of eFuses is sensed and the ASIC is configured to a predefined state responsive to an applied POR/Sense control signal.

Abstract: A semiconductor device includes a plurality of pads configured to receive a plurality of external signals, an internal circuit configured to perform a predetermined internal operation in response to one of the external signals that is inputted through one of the plurality of pads, and a signal transferring unit configured to receive the external signal, output the external signal to an internal circuit an output signal during a normal mode, and output a fixed signal regardless of changes in the external signal to the internal circuit in a test mode.

Abstract: An apparatus for controlling an active cycle of semiconductor memory that supports a synchronous mode and an asynchronous mode is provided. The apparatus includes an operational mode control unit that determines the operational mode of the semiconductor memory on the basis of a clock signal for a predetermined time and outputs an operational mode determination signal, and an active control unit that controls the output of an active signal for executing an active cycle of the corresponding operational mode on the basis of the operational mode determination signal.

Abstract: An impedance matching circuit of a semiconductor memory device performs a ZQ calibration with initial values that reflect an offset error according to variations in a manufacturing process. The impedance matching circuit includes a first pull-down resistance unit, a first pull-up resistance unit, and a code generation unit. The first pull-down resistance unit supplies a ground voltage to a first node, thereby determining an initial pull-down code. The first pull-up resistance unit supplies a supply voltage to the first node, thereby determining an initial pull-up code or a voltage level on the first node. The code generation unit generates pull-down and pull-up calibration codes using the initial pull-down and pull-up codes as respective initial values.

Abstract: A semiconductor integrated circuit having an internal circuit which is tested based on a scanning method is provided. The internal circuit has: memory elements including a first memory element and a second memory element; combinational circuits including a first combinational circuit receiving an external input data, a second combinational circuit outputting an external output data and a third combinational circuit; a first selection circuit; and a second selection circuit. The first selection circuit receives the external input data and a stored data held by the first memory element, and outputs any of them to the first combinational circuit. The second selection circuit receives the external output data output from the second combinational circuit and an operation result data output from the third combinational circuit, and outputs any of them to the second memory element.

Abstract: Electronic apparatus, systems, and methods of operating and constructing the electronic apparatus and/or systems include an embedded processor disposed in a logic chip to direct, among other functions, self-testing of an electronic device structure in conjunction with a pattern buffer disposed in the logic chip, when the electronic device structure is coupled to the logic chip. Additional apparatus, systems, and methods are disclosed.

Abstract: The invention relates to a testable integrated circuit. In order to replace ground and VDD in certain points of such a circuit, the circuit comprises a cell (34) which comprises a flipflop (11) and means (31) able to set the output voltage of the cell when the circuit is in the operation mode. These means for setting the output voltage are controlled by a control signal (15) which depends on the mode signal that indicates whether the signal is in the test mode or in the operation mode.

Abstract: The invention concerns a process and a circuit designed to improve the life duration of electronic field-effect integrated circuit transistors and in particular those with a thin film gate dielectric. According to the invention, an aging measurement tS is supplied by measuring the charge or discharge time at a reference voltage VREF of the gate of a field effect transistor T1, previously pre-charged to a predefined test voltage VP, and brought to high impedance. Depending on the aging measurement obtained, the operational voltage measurement conditions of the transistor can be maintained or modified to reduce the stress applied to the dielectric.

Abstract: A method of testing a die having a non-testable circuit, where the non-testable circuit is logically incomplete and forms part of a logically complete multiple tier circuit. The method includes reconfiguring a tier-to-tier input point or tier-to-tier output point associated with a primary path of the non-testable circuit to create a logically complete secondary path for the tier-to-tier point such that the non-testable circuit can be tested. Testable dies and methods of preparing such dies are also provided.

Abstract: A semiconductor integrated circuit device includes a column of first logic circuit cells arranged along a first side of a chip and a column of second logic circuit cells arranged along a second side orthogonal to the first side. At a corner part where the first side crosses the second side, a first test logic circuit cell is arranged to have its long side faced with a side of a cell at an end portion of the column of the first logic circuit cells and a second logic circuit cell is arranged to have its long side faced with a side of a cell at an end portion of the column of the second logic circuit cells. The first and the second test logic circuit cells are arranged so a that planar shapes thereof are symmetrical (mirror symmetrical) to each other with respect to a virtual line intermediate between the oblique sides arranged opposite to each other.

Abstract: An integrated circuit, or combination of integrated circuits, has a primary interconnect, a redundant interconnect, and circuitry connecting the primary and redundant interconnects allowing selection of the redundant interconnect to bypass the primary interconnect.

Abstract: An FPGA architecture includes multiplexers having non-volatile switches having control gates coupled to word lines W, each word line associated with a row, the switches connecting to wiring tracks through buffers having a controllable ground connection NGND, at least some of the switches being a tie-off switch coupleable to one of a plurality of bitlines B, each bitline associated with column.

Abstract: A semiconductor device includes a first pad, a second pad and a third pad. The first pad and the third pad are electrically connected to each other. The first pad and the second pad are used for bonding. The second pad and the third pad are used for probing. According to this structure, Small size semiconductor device having high reliability even after a probing test can be provided.

Abstract: An integrated circuit apparatus includes a switching circuit that provides respective signal paths to permit a mission signal, a test signal, and a boundary scan test signal to share an output terminal. The signal path associated with the mission signal imposes a smaller switching delay than do the signal paths associated with the test and boundary scan test signals.

Abstract: Provided is a semiconductor integrated circuit including: a first path that includes a first logic circuit; a second path that includes a second logic circuit; and a subsequent-stage circuit that is connected to an output of the first path and is connected to an output of the second path, in which the second path further includes a first internal path that is selected as a propagation path during a normal operation period; and a second internal path that is selected as a propagation path during a test operation period and includes a delay circuit having a delay amount larger than a delay amount of the first internal path.

Abstract: A method of testing a tristate element by applying a given value to the tristate, applying an opposite value to a keeper element connected at an output of the tristate, capturing a first value at a downstream position of the tristate, evaluating a second value at the output of the tristate using the first value, comparing the second value to the opposite value, and producing a failure code for the tristate when the second value is not equal to the opposite value. Then, applying the opposite value to the tristate, applying the given value to the keeper element, capturing the first value, evaluating the second value using the first value, comparing the second value to the given value, and producing a failure code for the tristate when the second value is not equal to the given value. A passing code for the tristate is produced when a failure code has not been produced.

Abstract: A semiconductor, which includes a first phase detecting unit configured to detect a phase of a second clock on the basis of a phase of a first clock, and generate a first detection signal corresponding to a result of the detection, a second phase detecting unit configured to detect a phase of a delayed clock, which is generated by delaying the second clock by a predetermined time, on the basis of the phase of the first clock, and generate a second detection signal corresponding to a result of the detection, and a logic level determining unit configured to determine a logic level of a feedback output signal according to the first detection signal, the second detection signal and the feedback output signal.

Abstract: A method of preventing current leakage in logic circuits within level sensitive scan design (LSSD) latch circuits in an application specific integrated circuit (ASIC). When the ASIC is in a manufacturing test mode, a gating signal at an input terminal of a power gating circuit is set to exceed a threshold voltage of transistors within the power gating circuit. The gating signal thus causes the power gating circuit to enable electrical current to reach the LSSD latch circuits. When the ASIC is in a normal functional mode, the gating signal is set below the threshold voltage. The gating signal thus causes the power gating circuit to prevent electrical current from reaching particular logic circuits (e.g., scan logic) within the LSSD latch circuits, thereby conserving power within the ASIC by preventing current leakage and heat generation in the LSSD latch circuit.

Abstract: A integrated circuit comprises a circuit part to be protected and protective lines located at least one wiring level of the integrated circuit. In addition, the integrated circuit comprises logical gates coupled to the protective lines, whereby a logic circuit is formed, and a processing unit implemented to detect a manipulation of the integrated circuit by applying test patterns to the logic circuit and verifying a logic output value of the logic circuit responsive to the test patterns.

Abstract: A semiconductor integrated circuit having a test circuit for inspecting states of connections between a plurality of pads and respective external terminals by bonding wires. The test circuit comprises, for each of a plurality of pads, a control terminal provided to receive a control signal of a logic level equal to the logic level of a signal applied to a corresponding one of the external terminals, an inverter which inverts the logic level on the control terminal, an inverted output terminal of the inverter being connected to the pad via a connection line; and an exclusive-NOR gate which outputs an exclusive NOR of the logic level on the connection line and the logic level on the control terminal.

Abstract: Testing of memories that decode a serial stream of address data to access the memory may be performed by either successively halving the number of selected word lines as each address bit is acquired, until a single word line is selected, or by rotating the selection bits in its shift register to select a new set of address lines. As such, a combination of incomplete addressing and rotation can efficiently test large memories by reading and/or writing groups of words. Similar techniques may also be applied to non-memory devices.

Abstract: The present test apparatus avoids proximity restriction violation of an edge and surely generates a test signal. There is provided a test apparatus that tests a device under test. The test apparatus includes a test pattern generating section that generates a test pattern to test the device under test every test period, a plurality of edge generators that respectively generate an edge of a test signal to be supplied to the device under test based on the test pattern every cycle period of a reference clock that is used as a reference for an operation of this test apparatus, a selecting section that selects which edge generator generates each edge of a test signal to be output during the next cycle period based on a pattern of the edge generated during the current cycle period, and a test signal supplying section that supplies the test signal according to each edge generated from the selected edge generator to the device under test.

Abstract: Stable testing is performed on an input and output circuit. An output stage outputting output signal to input/output terminal DQ comprises: a differential pair formed from an Nch transistor N1, having as load a Pch transistor P1 and resistance element R1, and an Nch transistor N2, having as load a Pch transistor P2 and resistance element R2; and an Nch transistor N3 supplying operating current to the differential pair. The input/output terminal DQ is connected to the drain of the Nch transistor N1. The output stage is operated as differential pair, in the normal operation mode (TM=L), wherein the Pch transistors P1, P2 are ON, a read-data signal RD is supplied to the differential pair, and a specified voltage CC is supplied to the gate of the Nch transistor N3; and in the test mode (TM=H), a CMOS circuit is established wherein a read-data signal RD is supplied to the gate of the Pch transistor P1 and the gate of the Nch transistor N3, turning the Nch transistor N1 ON.

Abstract: The invention relates to a circuit for comparing two n-digit binary data words x[1](t), . . . , x[n](t) and x?[1](t), . . . , x?[n](t), which in the error-free case are either identical or inverted bit-by-bit with respect to each other, with a series connection of a combinatorial circuit for implementing a first combinatorial function, a controllable register and a combinatorial circuit for implementing another combinatorial function.

Abstract: A circuit having a local power block for leakage reduction is disclosed. The circuit has a first portion and a second portion. The first portion is configured to operate at a substantially greater operating frequency than the operating frequency of the second portion. The second portion has a local power block configured to decouple the second portion if the second portion is inactive to reduce leakage current associated with the second portion without sacrificing performance of the first portion.

Abstract: A test circuit according to the present invention performs a test of a first tri-state device and a second tri-state device having their outputs connected to the same node, and includes: a test output terminal; and a test unit operable to output a first logical value or a second logical value to the test output terminal according to whether the voltage of the node is higher or lower than a threshold value, and the test unit converts the intermediate potential occurring at the node into the first logical value and outputs the first logical value to the test output terminal when the first tri-state device outputs a high level signal to the node and the second tri-state device outputs a low level signal to the node.

Abstract: An integrated circuit is provided having a memory storing first and second strings of bit values, each bit value in the second string being the logical inverse of a bit value at a corresponding bit position in the first string, and a processor configured to test whether the bit values of the second string are the inverse of the bit values at respective corresponding bit positions of the first string by combining the corresponding bits of the first and second strings.

Abstract: An integrated circuit (IC) includes self-calibrating programmable digital logic circuitry. The IC includes at least one programmable digital logic cell, wherein the first programmable digital logic cell provides (i) a plurality of different accessible circuit configurations or (ii) a voltage level controller. A self-calibration system is provided that includes at least one reference device, a measurement device for measuring at least one electrical performance parameter that can affect a processing speed of the first programmable digital logic cell or at least one parameter that can affect the electrical performance parameter using the reference device to obtain calibration data. A processing device maps the calibration data or a parameter derived therefrom to generate a control signal that is operable to select from the plurality of different accessible circuit configurations or a voltage level output to change the processing speed of the programmable digital logic cell.

Abstract: A device and a method for testing a resistance value of an on-die-termination (ODT) device and a semiconductor device having the same are presented. The device can include a comparator, a storage unit and and an output unit. When in an ODT test operation mode, the comparator compares a reference voltage against an input data input to a pad to determine the resistance value of the ODT device and outputs a determination data on the resistance value of the ODT device corresponding to the determination results. The storage unit stores the output of the comparator in synchronization with a clock signal. When in the ODT test operation mode, the output unit outputs the determination data on the resistance value of the ODT device stored in the storage unit to the pad. Thereby not only is the device configured to determine whether or not a defect of the resistance value of the ODT device exists but the device and the method are able to achieve this task in a substantially shorter testing time period.

Abstract: A detecting device for detecting an operating mode is disclosed. The detecting device includes a pulse generator and a hold-up unit. The pulse generator is disposed for issuing a one-shot pulse signal in response to each of button signals respectively. The hold-up unit is disposed for receiving the button signals to respectively generate delayed button signals by way of clock delay determined by a clock signal. The one-shot pulse signal and the delayed button signals are used to determine an operating mode of a system.

Abstract: A semiconductor integrated circuit device includes: a first large scale integrated circuit including a plurality of first logical blocks; a programmable second large scale integrated circuit connected the first large scale integrated circuit and including a second logical block; a memory storing data for achieving the purposes of the first logical blocks; and a control unit that, when a failure is detected in any of the first logical blocks during the operation of the first large scale integrated circuit, writes the data for the faulty first logical block stored in the memory to the second logical block, and uses the second logical block in place of the faulty first logical block.

Abstract: An on die termination controls a terminal resistance value in accordance with a test signal. The one die termination device comprises an on die termination control unit and an on die termination resistor unit and can change the terminal resistance value in accordance with the test signal, so that the terminal resistance can be easily analyzed. The one die termination control unit comprises a resistance control enable signal generating unit and a resistance control signal generating unit and generates at least one resistance increment signal and at least one resistance decrement signal. The on die termination resistor unit comprises a resistor and a plurality of switch units that are connected in parallel and is driven by a driving signal and uses the resistance increment signal and resistance decrement signal to control the on die termination resistance value.

Abstract: A method, an integrated circuit structure, and an associated design structure for the integrated circuit structure have a plurality of logic blocks, at least one of which is a redundant logic block. In addition, the structure includes a logic built-in self test device (LBIST) operatively connected to the logic blocks that determines the functionality of each of the logic blocks. An array of memory elements is included within the structure and is operatively connected to the logic blocks. At least one of the memory elements comprises a redundant memory element. The structure also includes an array built-in self test device (ABIST) operatively connected to the array of memory elements that determines the functionality of each of the memory elements. One feature is the use of a single controller operatively connected to the register, the logic blocks, and the memory elements.

Abstract: In a semiconductor device, when a voltage regulator is halted from operating and a test supply voltage is supplied to second logics, the device is initialized by a reset signal. A register included in the device is then reset by an input signal via first logics. The voltage regulator is halted by a power-down signal. Testing is then carried out as the test supply voltage is applied to the second logics. When plural test items are executed successively, a test reset signal is applied to a test reset terminal for each item. As the initialized state of the register is canceled, the first and second logics are initialized.

Abstract: A flip-flop has a first latch and a second latch. The first latch has a first feedback circuit and a first selecting circuit which selects one of a first data input signal and an output signal of the first feedback circuit, based on the logic level of a first clock signal. The second latch has a second feedback circuit and a second selecting circuit which selects an output signal of the first latch and an output signal of the second feedback circuit based on the inverted logic level in case of the first latch. The first feedback circuit has a third selecting circuit which selects one of an output signal of the first latch and a second data input signal based on the logic level of a second clock signal, and outputs a signal selected by the third selecting circuit to the first selecting circuit.

Abstract: A test circuit that compares test results between two tests with different local supply voltages is provided. The output of each stage of the logic circuits is stored in a first register of each test circuit. Each test is performed with a critical test vector and a local supply voltage that decreases from test to test. The outputs of successive tests are compared in each test circuit. The tests are performed iteratively with successive reduction in the value of the local supply voltage until at least one stage of the logic circuits produces non-matching results between the first and second register. The voltage immediately before producing such non-matching results is the minimum operational voltage for the local voltage island.

Abstract: Some embodiments provide a configurable integrated circuit (IC). The IC has configurable logic circuits for performing logical operations, configurable routing circuits for routing signals between the configurable logic circuits, and a network for monitoring data. In some embodiments a method uses at least a subset of the configurable logic circuits and a first subset of the configurable routing circuits to implement a user design circuit on the configurable IC. The method uses a second subset of the configurable routing circuits to pass signals to the network.

Abstract: An integrated circuit including an array of memory cells, a control circuit, and an output circuit. The array of memory cells is configured to provide a group of data bits. The control circuit is configured to provide a test mode signal. The output circuit is configured to receive the test mode signal and the group of data bits, where the output circuit selectively outputs smaller subsets of the group of data bits based on the test mode signal.

Abstract: A method and apparatus is provided to significantly increase the flexibility of readback capture mechanisms, the apparatus being an integrated circuit device, comprising a configuration data router coupled to receive at least one configuration data frame from a configuration interface, a configuration memory space coupled to the configuration data router and adapted to receive the configuration data frame to define a user logic block and a capture block within the programmable logic device, the user logic block including, a monitor control block coupled to the capture block and adapted to report activity within the user logic block to the capture block, and a configuration control logic block coupled to the capture block that is adapted to assert the capture signal in response to the asserted alert signal.

Abstract: An apparatus for measuring an on-die termination (ODT) resistance includes an ODT controller and a driver. The ODT controller receives a plurality of decoding signals, a first test mode signal, and a second test mode signal to generate a plurality of pull-up signals and a plurality of pull-down signals. The pull-up signals are enabled in response to the decoding signals and the first test mode signal, and the pull-down signals are enabled in response to the decoding signals and the second test mode signal. The driver receives the pull-up signals and the pull-down signals to drive a data terminal. At least one of the decoding signals is enabled by a mode register set (MRS) for setting an ODT mode.

Abstract: A high voltage stress test circuit includes an internal data generation unit for generating internal data and inverted internal data, and a level shifter for receiving the internal data and the inverted internal data and for generating digital data and inverted digital data. In a normal mode, the internal data and the inverted internal data have logic states corresponding to input data, while the digital data and the inverted digital data have logic states corresponding to the internal data and the inverted internal data. In a high voltage stress test mode, the internal data and the inverted internal data have predetermined logic states regardless of a logic state of the input data, while the digital data and the inverted digital data have predetermined logic states regardless of logic states of the internal data and the inverted internal data.

Abstract: A capacitor circuit and method to reduce layout area, leakage current, and to improve yield is disclosed. The circuit includes an output terminal (100), a plurality of circuit elements (322, 326, 330), and a plurality of transistors (320, 324, 328). Each transistor has a control terminal (314, 316, 318) and a current path coupled between the output terminal and a respective circuit element of the plurality of circuit elements. A control circuit (300) has a plurality of output terminals (314, 316, 318). Each output terminal is coupled to the control terminal of a respective transistor of the plurality of transistors. The control circuit produces control signals at respective output terminals to selectively turn off at least one transistor and turn on at least other transistors of the plurality of transistors at a first time.

Abstract: In a semiconductor device, when a voltage regulator is halted from operating and a test supply voltage is supplied to second logics, the device is initialized by a reset signal. A register included in the device is then reset by an input signal via first logics. The voltage regulator is halted by a power-down signal. Testing is then carried out as the test supply voltage is applied to the second logics. When plural test items are executed successively, a test reset signal is applied to a test reset terminal for each item. As the initialized state of the register is canceled, the first and second logics are initialized.