Abstract: An embodiment of a buffer for a transmission line, a circuit including such a buffer, a high-speed data link, and a low-voltage differential signaling (LVDS) system.

Abstract: A semiconductor device includes a core circuit including an integrated circuit; output drivers, each including sub-drivers to output digital data transferred from the core circuit, as output data; and a selector that selects a sub-driver to be driven from among the plurality of sub-drivers. Each of the sub-drivers includes: an output transistor connected between a first power supply and an output wiring line to allow the output data to rise or fall according to the digital data; and a switching transistor and a slew-rate control transistor which are connected in series between a gate of the output transistor and a second power supply. The switching transistor turns on or off the output transistor according to the digital data. A gate potential adjusted to determine a slew rate for rise or fall of the output data is selectively provided by the selector to each slew-rate control transistor.

Abstract: A circuit, including a first impedance unit having an impedance value based on a first impedance code and configured to drive a first node coupled with a resistor with a first voltage, a first code generation unit configured to generate the first impedance code so that an impedance value of the first impedance unit and an impedance value of the resistor are at a ratio of X:Y, dummy impedance units that receive the first impedance code and drive a second node with the first voltage, a second impedance unit having an impedance value based on a second impedance code and configured to drive the second node with a second voltage, and a second code generation unit configured to generate the second impedance code so that an overall impedance value of the dummy impedance units and an impedance value of the second impedance unit are at a ratio of X:Y.

Abstract: A system and method for implementing a differential signaling driver with a common-mode voltage not equal to one half the power supply voltage using voltage-mode techniques. Embodiments of the present invention maintain balanced impedance at the signal output. In an embodiment, a driver may have multiple operating modes for each potential supply voltage or common-mode voltage. In an embodiment, each potential mode may involve configuring the driver by activating or deactivating switches or resistors in the driver and each potential mode may have different resistor values.

Abstract: An impedance code generation circuit includes an impedance code generation unit configured to generate an impedance code, a set value generation unit configured to generate a set value by counting an external signal, and an impedance code modification unit configured to generate a modified impedance code by performing a logic operation on the set value and the impedance code.

Abstract: A package includes a master chip including a storage circuit configured to store an impedance setting of the master chip and an impedance setting of a slave chip, and a termination circuit for an impedance matching with an outside of the package, and the slave chip connected to the master chip, wherein if a termination operation for the slave chip is activated, the termination circuit of the master chip performs an impedance matching operation using the impedance setting for the slave chip.

Abstract: A termination circuit includes: a pull-up termination unit configured to pull-up terminate an interface node in response to a pull-up signal; a pull-down termination unit configured to pull-down terminate the interface node in response to a pull-down signal; one or more pull-up resistors connected to the interface node and enabled to affect termination resistance in response to a pull-up setting value when a termination signal is activated; and one or more pull-down resistors connected to the interface node and enabled to affect termination resistance in response to a pull-down setting value when the termination signal is activated.

Abstract: In a semiconductor device having a terminal connected to an internal portion, a termination circuit for providing on-die termination for the terminal of the device. The termination circuit comprises a plurality of transistors, including at least one NMOS transistor and at least one PMOS transistor, connected between the terminal and a power supply; and control circuitry for driving a gate of each of NMOS transistor with a corresponding NMOS gate voltage and for driving a gate of each PMOS transistor with a corresponding PMOS gate voltage, the control circuitry being configured to control the NMOS and PMOS gate voltages so as to place the transistors in an ohmic region of operation when on-die termination is enabled. The power supply supplies a voltage that is less than each said NMOS gate voltage and greater than each said PMOS gate voltage.

Abstract: An integrated circuit includes a first ODT unit and an input buffer. The first ODT unit is configured to receive at least one pull-up code and at least one pull-down code for impedance matching of a first line through which data is transferred, and adjust a resistance value. The input buffer is configured to drive input data by buffering the data in response to a level of a reference voltage, wherein the driving of the input data is adjusted in response to the pull-up code and the pull-down code.

Abstract: Described are integrated-circuit die with differential receivers, the inputs of which are coupled to external signal pads. Termination legs coupled to the signal pads support multiple termination topologies. These termination legs can support adjustable impedances, capacitances, or both, which may be controlled using an integrated memory.

Abstract: A system for receiving data is provided the system includes an inductive data device, such as a device that receives high-speed data over an inductive coupling. An adjustable impedance is coupled to the inductive data device, where the adjustable impedance is used for dynamically controlling ringing in the inductive data device, such as by damping ringing signals generated by circuit inductances or capacitances.

Abstract: To include an output terminal, unit buffers, and plural output-wiring paths that respectively connect the unit buffers and the output terminal. The output wiring paths have individual output wiring sections individually allocated to corresponding unit buffers. Unit buffers corresponding to these output wiring paths are common output wiring sections shared by the output wiring paths, and are connected to the output terminal without via a common output wiring section having a higher resistance value than those of the individual output wiring sections. Accordingly, an deviation of impedance due to a parasitic resistance between the output terminal and the unit buffers is suppressed.

Abstract: A receiving circuit includes: a terminating resistor to set a terminating level of a transmission line for transmitting a reception signal including a signal having a first level indicating a preamble; a detection circuit to detect whether a level of the transmission line is the first level or a second level; and an adjustment circuit to adjust a resistance of the terminating resistor, the adjustment circuit adjusting the resistance of the terminating resistor to a value such that the detection circuit detects the level of the transmission line as the second level when a data request is output to a transmitting side.

Abstract: A chip comprising a signal transmitting circuit, a communication system between multiple chips and a method for configuring the communication system between multiple chips are provided. The signal transmitting circuit of the chip comprises a multi-route selector, a first bias resistor and a second bias resistor, a first signal line and a second signal line, and a signal transmitting end; wherein the multi-route selector comprises a first input end, a second input end, a selection input end and an output end, wherein the first input end is grounded, the second input end is connected to a DC bias voltage and the selection input end receives a selection signal; wherein the multi-route selector selects the first input end when the selection signal is a first selection signal, and the multi-route selector selects the second input end when the selection signal is a second selection signal.

Abstract: First and second devices may simultaneously communicate bidirectionally with each other using only a single pair of LVDS signal paths. Each device includes an input circuit and a differential output driver connected to the single pair of LVDS signal paths. An input to the input circuit is also connected to the input of the driver. The input circuit may also receive an offset voltage. In response to its inputs, the input circuit in each device can use comparators, gates and a multiplexer to determine the logic state being transmitted over the pair of LVDS signal paths from the other device. This advantageously reduces the number of required interconnects between the first and second devices by one half.

Abstract: To discriminate whether a cable in conformity with a conventional standard or a cable in conformity with a new standard is connected. An HPD signal line (902) has, on an expanded HDMI sink apparatus (402) side circuit, a pull-up resistor (911) between the HPD signal line (902) and a voltage supply and a pull-down resistor (913) between the HPD signal line (902) and the ground, and a reserved line (903) has, on the expanded HDMI sink apparatus (402) side circuit, a pull-down resistor (914) between the reserved line (903) and a ground, and within a new HDMI cable (901), a pull-up resistor (912) between the reserved line (903) and a voltage supply of an expanded HDMI source apparatus (401). The expanded HDMI sink apparatus compares a voltage at a test point (19) on the reserved line (903) on the expanded HDMI sink apparatus (402) side with a reference voltage by using a voltage comparator (916).

Abstract: A multi-mode differential termination circuit has a pair of differential input terminals for receiving external differential signals, a pair of series-connected load elements coupled between said differential input terminals, and an analog interface terminal coupled a common junction point of said load elements. A bias circuit is coupled to the common junction point of the load elements for selectively applying a bias voltage thereto in response to a digital control signal. A control input receives the digital control signal to activate the bias circuit.

Abstract: An inverter-type high speed driver circuit having a first inverter branch and a second inverter branch wherein each of the inverter branches comprising a parallel circuit of a serial connection of a first impedance tuning unit and a respective first clocking transistor and a serial connection of a second impedance tuning unit and a respective second clocking transistor. The impedance tuning units are configured to adapt the conductivity of the respective inverter branch to set the output impedance of the driver circuit and each of the impedance tuning units is controlled in accordance with a data stream.

Abstract: A method for calibrating resistors on an integrated circuit chip via a daisy chain scheme. The method comprises the step of configuring one or more links of the daisy chain scheme, wherein each of the one or more links comprises one or more master resistors and one or more slave resistors. The method further comprises the steps of calibrating at least one on-chip reference resistor, the one or more master resistors, and the one or more slave resistors via the daisy chain scheme. The method using the daisy chain scheme enables resistance of at least one off-chip reference resistor to be duplicated to multiple distant locations while maintaining a low mismatch error.

Abstract: Apparatuses including termination for complementary signals are described, along with methods for terminating complementary signals. One such apparatus includes a termination transistor including a first node configured to receive a first complementary signal and a second node configured to receive a second complementary signal. A regulation circuit can generate a regulated voltage to render the termination transistor conductive with a substantially constant resistance. In one such method, a first complementary signal is received at a drain of a termination transistor and a second complementary signal is received at a source of the termination transistor. Energy of the complimentary signals can be absorbed when the termination transistor is rendered conductive. Additional embodiments are also described.

Abstract: A system for controlling the termination impedance of memory device data bus terminals is fabricated on the same die as the memory device. The system includes a termination resistor connected to each data bus terminal, which is connected in parallel with several transistors that are selectively turned on to adjust the termination impedance. The transistors are controlled by a circuit that determines the resistance of the termination resistor and turns on the correct number of transistor to properly set the termination impedance. In one example, the resistance of the termination resistor is determined by directly measuring a resistor of the same type as the termination resistor. In another example, the resistance of the termination resistor is determined indirectly by measuring parameters that affect the resistance of the termination resistor. In either case, the system can maintain the termination impedance of the data bus terminals constant despite changes in the termination resistor.

Abstract: An embodiment of an impedance adjustment apparatus is disclosed. For this embodiment of an impedance adjustment apparatus, a differential driver circuit has an input port, a first output port, a second output port, a first bias node, and a second bias node. A first impedance-voltage device is coupled to provide a first bias voltage to the first bias node. A second impedance-voltage device is coupled to provide a second bias voltage to the second bias node. A first analog voltage source is coupled to provide a first analog voltage to the first impedance-voltage device, and a second analog voltage source is coupled to provide a second analog voltage to the second impedance-voltage device.

Abstract: A transmitter configured for pre-emphasis is described. The transmitter includes a voltage-driven single-ended-termination driver circuitry. The voltage-driven single-ended-termination driver circuitry includes a first termination point and a second termination point. The transmitter also includes a pre-emphasis encoder circuitry. The pre-emphasis encoder circuitry receives a pre-emphasis signal. The transmitter may reduce signal loss in transmission lines by detecting a transition in a data stream, adjusting a source determination resistance and obtaining a gain from the adjusted source determination resistance.

Abstract: An adjustable gain line driver receives an input signal and a gain control signal and outputs a signal with a swing, and the swing is measured to generate a swing measurement signal. A target swing signal is generated having a target swing, and the target swing signal is measured to generate a target swing reference signal. The swing measurement signal is compared to the target swing reference control signal and a counter generating the gain control signal is incremented until the measurement signal meets the target swing reference signal. Optionally a reset signal resets the counter, and the gain control signal, at predetermined events.

Abstract: A data strobe signal output driver includes a trigger block, a predriver block, and a main driver block. The trigger block is configured to receive a first signal, a second signal, a first clock and a second clock, and to output a predrive signal based thereon. The predriver block is configured to receive the predrive signal, a driver off signal and a termination enable signal, and to output a first main drive signal and a second main drive signal based thereon. The main driver block is configured to output a data strobe signal based on the first and second main drive signals.

Abstract: An integrated circuit includes a first ODT (On Die Termination) unit and an input buffer. The first ODT unit is configured to receive at least one pull-up code and at least one pull-down code and calibrate a resistance value for impedance matching of a first line transferring data. The input buffer is configured to buffer the data in response to a reference voltage level and drive input data. Herein, the driving of the input data is controlled in response to the pull-up code and the pull-down code.

Abstract: An integrated circuit includes: an on-die-termination (ODT) circuit configured to drive an input signal with drivability adjusted according to an impedance calibration code and a reference voltage; and an input buffer configured to buffer the input signal in response to the reference voltage and generate an output signal.

Abstract: Described are digital communication systems that transmit and receive parallel sets of data symbols. Differences between successive sets of symbols induce changes in the current used to express the symbol sets, and thus introduce supply ripple. A receiver adds compensation current to reduce supply ripple. The compensation current is calculated based upon prior data samples rather than the current symbols, and consequently increases the maximum instantaneous current fluctuations between adjacent symbol sets as compared with circuits that do not include the compensation. The frequency response of the power-distribution network filters out the increased data dependence of the local supply current, however, and consequently reduces the fluctuations of total supply current. Some embodiments provide compensation currents for both transmitted and received symbols.

Abstract: A differential buffer circuit having increased output voltage swing includes a differential input stage including at least first and second transistors, the first and second transistors being operative to receive first and second signals, respectively. The buffer circuit further includes a bias stage connected between the differential input stage and a first voltage source. The bias stage is operative to generate a quiescent current as a function of a third signal supplied to the bias stage. A load circuit is connected between a second voltage source and the differential input stage, first and second differential outputs of the buffer circuit being generated at a junction between the load circuit and the differential input stage. The load circuit includes first and second switching elements coupled with the first and second transistors, respectively.

Abstract: A termination circuit for a plurality of memories controlled by a controller is provided. The termination circuit includes a plurality of drivers, a plurality of resistors and a plurality of capacitors. Each of the drivers is coupled to the memories via a transmission line. Each of the resistors is coupled to the corresponding driver via the corresponding transmission line. Each of the capacitors is coupled between the corresponding resistor and a reference voltage. The controller is coupled to the memories via the drivers, and the controller provides a specific code to one of the drivers when a quantity of logic “0” and a quantity of logic “1” transmitted to the memories via the transmission line corresponding to the one of the drivers are unbalanced, so as to adjust a termination voltage of the capacitor corresponding to the one of the drivers.

Abstract: An impedance control circuit includes a first impedance unit configured to terminate an impedance node using an impedance value that is determined by an impedance control code, a second impedance unit configured to terminate the impedance node using an impedance value that is determined by an impedance control voltage, a comparison circuit configured to compare a voltage level of the impedance node and a voltage level of a reference voltage, generate an up/down signal indicating whether the voltage at the impedance node is greater than the reference voltage, and generate the impedance control voltage that has a voltage level corresponding to a difference between the voltage at the impedance node and the reference voltage, and a counter unit configured to increase or decrease a value of the impedance control code in response to the up/down signal.

Abstract: An impedance control circuit includes a pull-up code generator configured to generate pull-up impedance control codes using a voltage of a first node, a pull-up impedance unit configured to pull-up-drive the first node in response to the pull-up impedance control codes, a plurality of dummy impedance units enabled in response to respective select signals and each configured to pull-up-drive a second node in response to the pull-up impedance control codes, a pull-down code generator configured to generate pull-down impedance control codes using a voltage of the second node, and a plurality of pull-down impedance units enabled in response to the respective select signals and each configured to pull-down-drive the second node in response to the pull-down impedance control codes.

Abstract: Various embodiments of an on-die termination (ODT) signal generating circuit are disclosed. In one exemplary embodiment, the ODT signal generating circuit includes a latency unit and an ODT control signal generating unit. The latency unit is configured to receive a clock signal and an ODT signal. The latency unit is configured to delay the ODT signal by a predetermined time to generate a first ODT signal. The latency unit is also configured to delay the ODT signal by less than the predetermined time to generate a second ODT signal. The ODT control signal generating unit is configured to provide either one of the first and second ODT signals as an ODT control signal in response to a control signal.

Abstract: An integrated circuit device includes an input/output (IO) pad, and a programmable termination capacitance circuit coupled to the IO pad, the programmable termination capacitance circuit comprising at least one compensation bank, wherein each of the at least one compensation bank includes a compensation capacitor coupled to a reference voltage through a compensation pass gate.

Abstract: In accordance with this invention the above and other problems are solved by a switching apparatus and method that uses a switching circuit having a pair of parallel solid-state diodes (e.g., PN diodes), one of which is connected to a transistor (e.g., power MOSFET or IGBT), to switch a capacitor in or out of a variable capacitance element of an impedance matching network. Charging a body capacitance of the transistor reverse biases one of the two diodes so as to isolate the transistor from the RF signal enabling a low-cost high capacitance transistor to be used. Multiple such switching circuits and capacitors are connected in parallel to provide variable impedance for the purpose of impedance matching.

Abstract: The present invention significantly reduces the chip size of a metal-oxide-semiconductor (MOS) field-effect transistor, which serves as a driver for output impedance drivers, such as, but not limited to, double data rate (DDR2) synchronous dynamic random access memory (SDRAM). In an embodiment of the invention, a voltage drop across the driver is a decreased ratio of the supply voltage, e.g., three-tenths of the supply voltage, lower than half of the supply voltage. A smaller voltage drop allows a lower current and a higher impedance to be used in the driver. By having a higher impedance across the driver, the physical area needed for the DDR2 driver is reduced because a transistor with a smaller physical width can be used. A DDR2 driver operating at the decreased ratio is the functional equivalent of the driver operating with the supply voltage or half of the supply voltage, with the added advantage of the reduced area.

Abstract: A USB-based isolator system conveys USB signals between a pair of galvanically isolated circuit systems and supports controlled enumeration by a downstream device on upstream USB signal lines. The isolator system provides a multi-mode voltage regulator to support multiple voltage supply configurations. The isolator system further provides control systems for each of the isolated circuit systems and provides robust control in a variety of start up conditions. Additionally, the isolator system includes refresh timers and watchdog mechanisms to support persistent operation but manage possible communication errors that can arise between the isolated circuit systems.

Abstract: A termination device and a system and a method terminate a peripheral device of an alarm system. The termination device connects to wiring extending from the peripheral device. The termination device may have a resistor, a diode and/or a similar component which provides electrical resistance. The termination device may have a potentiometer which may enable a user to adjust the electrical resistance. The termination device may have a blade which cuts the wiring.

Abstract: Receiver circuits for differential and single-ended signals are disclosed. A receiver may include a differential amplifier configured to receive a first signal of a differential pair at a first input and a second signal of the differential pair at a second input when operating in differential mode, and a single-ended signal at the first input and a reference signal at a third input when operating in single-ended mode. The receiver may also include an inverter coupled to the differential amplifier. The inverter may be configured to provide a first beta ratio in differential mode and a second beta ratio in single-ended mode. Several receivers may be used, for example, to process a differential clock signal and one or more single-ended data signals referenced to the clock signal and/or differential data signals referenced to a single-ended clock signal. The rise/fall delays of each signal through each respective receiver may be independently adjusted.

Abstract: An element substrate includes a plurality of terminals, a first receiving circuit and a second receiving circuit each receiving a differential signal via one of the terminals included in the plurality of terminals, a driving circuit including a first input unit for inputting a first signal and a second input unit for inputting a second signal and driving a driving element based on the first signal and the second signal, and a setting circuit for setting a first connection state of connecting an output from the first receiving circuit to the first input unit and connecting an output from the second receiving circuit to the second input unit, and a second connection state of connecting an output from the first receiving circuit to the second input unit and connecting an output from the second receiving circuit to the first input unit based on an externally input signal.

Abstract: Methods of adjusting a centerline voltage of a data signal are described, along with apparatuses to adjust the centerline voltage. In one such method, portions of a termination circuit coupled to a node are selectively programmed to adjust an impedance of the termination circuit to adjust the centerline voltage of the data signal driven to the node. One such apparatus includes pull-up impedances and pull-down impedances that can be programmed to adjust the centerline voltage of the data signal. Additional embodiments are also described.

Abstract: This disclosure is directed to techniques for generating a reference current based on a combinational logic function that is to be performed by a magnetic logic device. A comparator circuit may compare an amplitude of a read current that flows through the magnetic logic device and the reference current to generate a logic output value that corresponds to the logic output value when combinational logic function is applied to the input values. By selecting appropriate amplitudes for the reference current the magnetic logic device may be caused to implement different combinational logic functions.

Abstract: Calibration circuitry 42 for an off-chip driver circuit 4 and/or an on-die termination circuit 8 is provided using a parallel network of main transistors controlled by a N-bit calibration value. During the calibration operation, the N-bit calibration value is varied until a threshold impedance value is crossed by the combination of the main transistors. A rounding transistor 52 is then used to determine which of the N-bit calibration values produces a combined impedance closest to the designed threshold impedance.

Abstract: A termination device system is provided that includes a device required to be terminated with a resistor and a termination circuit. The termination circuit includes a termination resistor circuit and a judgment circuit connected to the termination resistor circuit. The termination resistor circuit includes at least one controlled termination unit. Each controlled termination unit includes a termination connecting end for connecting the device required to be terminated with a resistor, a controlled switch and a resistor, and provides, based on on/off of the controlled switch, a termination resistor for the device connected to the termination connecting end. The judgment circuit judges whether the device is required to be connected to the termination resistor based on a control instruction of a control device controlling the device connected to the termination connecting end, to output an on/off control signal to the controlled switch of the termination resistor circuit to control on/off.

Abstract: A semiconductor device capable of achieving desirable communication behavior through a bus regardless of whether or not a pull-up resistor is connected on a bus line. The semiconductor device includes external pull-up determination unit and internal pull-up setting unit. The external pull-up determination unit applies a pull-down voltage through an internal pull-down resistor to the bus line, and determines whether an external pull-up resistor external to the semiconductor device is connected on the bus line on the basis of the voltage level of the bus line when the pull-down voltage is applied to the bus line. The internal pull-up setting unit stops application of the pull-down voltage, and applies a pull-up voltage through an internal pull-up resistor to the bus line if it is determined that no external pull-up resistor is connected on the bus line.

Abstract: A semiconductor chip including a termination resistance and a semiconductor module including the semiconductor chip.

Abstract: Disclosed herein is a semiconductor device that includes a first transistor unit coupled to the data terminal, and a plurality of second transistor units coupled to the calibration terminal. The first transistor unit includes a plurality of first transistors having a first conductivity type connected in parallel to each other so that an impedance of the first transistor unit is adjustable. Each of the second transistor units includes a plurality of second transistors having the first conductivity type connected in parallel to each other so that an impedance of each of the second transistor units is adjustable. The semiconductor device further includes an impedance control circuit that reflects the impedance of each of the second transistor units to the first transistor unit.

Abstract: The semiconductor device comprises an output circuit that includes a plurality of unit buffer circuits each of which has an adjustable impedance, a control circuit that selectively activates one or ones of the unit buffer circuits, and an impedance adjustment unit that adjusts the impedances of the unit buffer circuits and includes a power line, a replica circuit, which has a replica impedance that is substantially equal to the adjustable impedance of each of the unit buffer circuits, and a load current generation circuit, which changes current flowing therethrough in accordance with the number of activated the one or ones of the unit buffer circuits. The replica circuit and the load current generation circuit are connected in common to the power line.

Abstract: A transceiving circuit resistance calibrating method, which is applied to a transceiving circuit. The method includes: inputting a first current to a transmitter to generate a first output voltage, wherein the first current is generated according to a ratio between a predetermined voltage and an inner resistor of a chip; inputting a second current to a transmitter to generate a second output voltage, wherein the first current is generated according to a ratio between the predetermined voltage and a predetermined resistor; and adjusting a first adjustable resistance module according to a difference between the first output voltage and the second output voltage.

Abstract: Input structures and topologies are provided for coupling a differential input into a first stage of a circuit, topology, or device. An input pin is coupled to an impedance divider that translates an input voltage to accommodate low input voltage levels, while not saturating an input differential pair. A termination pair with a center tap pin is further coupled to the input pins. The center tap facilitates coupling different termination configurations to the input signal. The topologies accommodate packaged devices that have at least three external pins, two pins for the coupling of a differential input signal, and a pin for the termination pair center tap.