Abstract: An input port (2) of an electronic computer (4) of a motor vehicle includes: i) a plurality of pull-up loads (230a), each pull-up load being coupled to a power supply line (21) and to an input line (20) and including at least one transistor (231a) forming a current mirror with a first current reference module (232a), and ii) a plurality of pull-down loads (230b), each pull-down load being coupled to a ground line (22) and to the input line (20) and including at least one transistor (231b) forming a current mirror with a second current reference module (232b). Each pull-up load and each pull-down load includes a switch (233a, 233b) and the input port is configurable by ordering the closure or opening of each switch. An input circuit (3) including at least one input port and an electronic computer of a motor vehicle including the input circuit are described.

Abstract: A system includes an input/output channel and a plurality of chips coupled to the input/output channel, wherein only one chip of the plurality of chips performs a termination operation for impedance matching of the input/output channel.

Abstract: A bus system that includes a plurality of signal driving devices coupled to a common signal bus, a bus controlled circuit coupled to the common signal bus, and a compare circuit. The plurality of signal driving devices include a first signal driving device and a second signal driving device. The bus controller includes delay compensation circuitry with a configurable delay for each of the signal driving devices. The delay compensation circuitry has a current delay chain configuration associated with the first signal driving device. The compare circuit is configured to compare a first configurable delay associated with a first signal driving device to a second configurable delay associated with a second signal driving device of the plurality of signal driving devices, and for generating an output responsive to the comparing that indicates if the current delay chain configuration can be used by the second signal driving device.

Abstract: An electronic apparatus is provided. A PCB has first and second signal paths therein. First and second fingers are disposed on the first and second signal paths, respectively. A controller is coupled to a first memory via the first finger and a second memory via the second finger, and accesses the first and second memories through the first and second signal paths, respectively. The first and second signal paths share a common segment between the controller and a branch point. First and second components are disposed between the first finger and the branch point and between the second finger and the branch point, respectively. The distances between the first component and the branch point and between the second component and the branch point are smaller than or equal to the distance between the first component and the first finger and between the second component and the second finger, respectively.

Abstract: For one disclosed embodiment, an integrated circuit may comprise an internal transmission line in one or more layers of the integrated circuit. The internal transmission line may be coupled to receive a signal from an external transmission line at a first end of the internal transmission line without use of termination circuitry. The internal transmission line may transmit the signal passively to a second end of the internal transmission line. The integrated circuit may also comprise first circuitry having an input coupled to the internal transmission line at a first location of the internal transmission line to receive the signal and second circuitry having an input coupled to the internal transmission line at a second location of the internal transmission line to receive the signal. The second location may be different from the first location. Other embodiments are also disclosed.

Abstract: A voltage-mode driver circuit supporting pre-emphasis is implemented to include a driver arm and a correction arm. The driver arm receives an input signal, and is operable, in pre-emphasis intervals as well as steady-state intervals, to connect a first impedance between an output terminal of the driver circuit and a constant reference potential. The correction arm is operable to connect a correction impedance in parallel with the first impedance in pre-emphasis intervals, and to decouple the correction impedance from the first impedance in steady-state intervals. The parallel connection of the first impedance and the correction impedance in pre-emphasis intervals increases the voltage level of the output signal of the driver circuit in pre-emphasis intervals. The use of the correction arm compensates for the effect of parasitic capacitance at one or more nodes of the driver circuit, thereby reducing the settling time of the output signal and enabling high-speed operation.

Abstract: A second output transmission signal (“TX2”) added to a line driver is a scaled version of the main output transmission signal (“TX1”). TX2 is scaled from TX1 by a variable scale factor K. An adaptive hybrid circuit subtracts TX1 and TX2 from a line signal carrying both a line transmission signal and a line received signal (“RX”). A programmable impedance Ztune is coupled between the TX2 output of the line driver and the RX output of the adaptive hybrid circuit. A transmission echo in the output RX signal is measured. K and Ztune are then adaptively tuned to minimize the transmission echo. The hybrid in this case becomes a 4-port network, one port specifically added to adaptively cancel the transmission echo in the RX output of the adaptive hybrid circuit. Alternatively, the hybrid may be a 3-port hybrid including variable impedances to cancel the line transmission signal.

Abstract: In a semiconductor device, a selector selects a different reference voltage depending on whether the impedance of a transmitter or of a receiver is to be adjusted, and causes a reference voltage generator to generate the selected reference voltage. The reference voltage generator generates the reference voltage selected by the selector and applies the generated reference voltage to an impedance adjuster. The impedance adjuster adjusts the impedance of the transmitter and the impedance of the receiver, separately from each other, in accordance with the input reference voltage.

Abstract: An integrated circuit includes a first ODT (On Die Termination) unit and an input buffer. The first ODT unit is configured to receive at least one pull-up code and at least one pull-down code and calibrate a resistance value for impedance matching of a first line transferring data. The input buffer is configured to buffer the data in response to a reference voltage level and drive input data. Herein, the driving of the input data is controlled in response to the pull-up code and the pull-down code.

Abstract: A transmitter configured for pre-emphasis is described. The transmitter includes a voltage-driven single-ended-termination driver circuitry. The voltage-driven single-ended-termination driver circuitry includes a first termination point and a second termination point. The transmitter also includes a pre-emphasis encoder circuitry. The pre-emphasis encoder circuitry receives a pre-emphasis signal. The transmitter may reduce signal loss in transmission lines by detecting a transition in a data stream, adjusting a source determination resistance and obtaining a gain from the adjusted source determination resistance.

Abstract: A voltage-mode driver circuit supporting pre-emphasis is implemented to include a driver arm and a correction arm. The driver arm receives an input signal, and is operable, in pre-emphasis intervals as well as steady-state intervals, to connect a first impedance between an output terminal of the driver circuit and a constant reference potential. The correction arm is operable to connect a correction impedance in parallel with the first impedance in pre-emphasis intervals, and to decouple the correction impedance from the first impedance in steady-state intervals. The parallel connection of the first impedance and the correction impedance in pre-emphasis intervals increases the voltage level of the output signal of the driver circuit in pre-emphasis intervals. The use of the correction arm compensates for the effect of parasitic capacitance at one or more nodes of the driver circuit, thereby reducing the settling time of the output signal and enabling high-speed operation.

Abstract: To decrease the circuit scale necessary for the calibration of the output circuit and to decrease the time required for the calibration operation. The invention includes a first output buffer and a second output buffer that are connected to a data pin, and a calibration circuit that is connected to a calibration pin. The first output buffer and the second output buffer include plural unit buffers. The unit buffers have mutually the same circuit structures. With this arrangement, the impedances of the first output buffer and the second output buffer can be set in common, based on the calibration operation using the calibration circuit. Consequently, both the circuit scale necessary for the calibration operation and the time required for the calibration operation can be decreased.

Abstract: A bus system includes a plurality of stubs; a plurality of connectors, each of which is serially coupled between a corresponding one of the stubs and a corresponding one of memory modules; a plurality of first serial loads, each of which is serially coupled to a corresponding one of the connectors; and a plurality of second serial loads, each of which is serially coupled to characteristic impedance of a transmission line of a corresponding one of the stubs, wherein the first and the second serial loads are determined to be impedance matched at each transmission line terminal of the stubs.

Abstract: A semiconductor device includes a plurality of first input units configured to receive a command, a second input unit configured to receive a termination command, a termination control unit configured to be enabled by the termination command and decode the command to control a termination operation, and a termination unit configured to be controlled by the termination control unit and terminate an interface pad.

Abstract: A control component outputs to an integrated circuit device an indication to apply one of a plurality of controllable termination impedance configurations at a data input of the integrated circuit device. The indication causes the integrated circuit device to apply a first of the controllable termination impedance configurations at the data input during a first internal state of the integrated circuit device corresponding to the reception of write data on the data input, and causes the integrated circuit device to apply a second of the controllable termination impedance configurations at the data input during a second internal state of the integrated circuit device that follows the first internal state.

Abstract: Systems and methods for operating of one or more devices before, during, and/or after a power-save mode are provided. The system may include a transmitter device that configures the differential signal lines to low-impedance and a predetermined low-voltage during the power-save mode (such as connecting the differential signal lines to ground). The system may also include a receiver device that senses a wake-up signal, determines the type of wake-up signal, and wakes-up according to the type of wake-up signal.

Abstract: In a semiconductor device having a terminal connected to an internal portion, a termination circuit for providing on-die termination for the terminal of the device. The termination circuit comprises a plurality of transistors, including at least one NMOS transistor and at least one PMOS transistor, connected between the terminal and a power supply; and control circuitry for driving a gate of each of NMOS transistor with a corresponding NMOS gate voltage and for driving a gate of each PMOS transistor with a corresponding PMOS gate voltage, the control circuitry being configured to control the NMOS and PMOS gate voltages so as to place the transistors in an ohmic region of operation when on-die termination is enabled. The power supply supplies a voltage that is less than each said NMOS gate voltage and greater than each said PMOS gate voltage.

Abstract: Embodiments of the present invention provide electronic devices, memory devices and methods of driving an on-chip signal off a chip. In one such embodiment, an on-chip signal and a second signal complementary to the on-chip signal are generated and provided to the two inputs of a differential driver. One output of the differential driver circuitry is coupled to an externally-accessible output terminal of the package. The other output may be terminated off the chip, but within the package. By routing the output signal and a second complementary output through the package, crosstalk potentially caused by the output signal can be reduced. Simultaneous switching output noise may also be reduced through use of a current-steering differential driver topology. Signal symmetry may also improve, reducing inter-symbol interference.

Abstract: Printed circuit board having a termination of a T-shaped signal line having at least two line ends, one line end being terminated using a terminating resistor against a supply voltage, and the other line end being terminated against the reference potential of the supply voltage.

Abstract: Non-volatile memory devices including on-die termination circuits connected to an input/output circuit and an on-die termination control logic detecting a preamble of a strobe signal based on a command and a control signal and activating the on-die termination within the preamble period.

Abstract: A transceiver circuit supports a bidirectional mode and the bidirectional transceiver circuit is signal-compatible with JEDEC SSTL 2. A differential transceiver circuit supports a bidirectional mode and is also signal-compatible with JEDEC SSTL 2. Finally, transceiver circuits which, in interaction with the bidirectional transceiver circuits, allow a bus system to be set up.

Abstract: An impedance calibration circuit includes: a first calibration unit configured to compare a first converted voltage obtained by converting a first calibration signal with a reference voltage and vary the first calibration signal; a voltage detection unit configured to activate a voltage detection signal according to a level of a power supply voltage; a multiplexing unit configured to select and output the reference voltage or the first converted voltage in response to the detection signal; and a second calibration unit configured to compare a second converted voltage obtained by converting a second calibration signal with the level of the output signal of the multiplexing unit and vary the second calibration signal.

Abstract: Systems, methods, and apparatus, including computer program products, for providing termination resistance in a memory module are provided. An apparatus is provided that includes a plurality of memory circuits; an interface circuit operable to communicate with the plurality of memory circuits and to communicate with a memory controller; and a transmission line electrically coupling the interface circuit to a memory controller, wherein the interface circuit is operable to terminate the transmission line with a single termination resistance that is selected based on a plurality of resistance-setting commands received from the memory controller.

Abstract: A resistance calibration code generating apparatus includes a code calibration unit configured to calibrate and output code values of a resistance calibration code during predetermined cycles of a calibration clock, which are determined by a code calibration time control command, and a calibration clock generating unit configured to output the calibration clock using a code calibration command.

Abstract: A cable driver (301) for driving a single ended transmission medium such as a coaxial cable (115) comprising a core (120) and a shield (121) comprises a differential driver (104, 377) comprising a first output (151) for putting a first signal to the core (120) of the single ended transmission medium (115), a second output (152) for putting a second signal to the shield (121) of the single ended transmission medium (115) through a termination resistor (118) having an impedance close to the characteristic impedance (Z0) of the single ended transmission medium (115), and a third output (153) for putting a transmit ground supply signal (GNDT), local to the differential driver, to the shield (121) of the single ended transmission medium (115) through a first high frequency low impedance path (112). In use, the current through the third output (153) will be substantially the inverse of the common mode current through the first and second outputs (151, 152).

Abstract: An impedance code generation circuit includes an impedance unit configured to drive a calibration node to a first level by using an impedance value determined by an impedance code, a code generation unit configured to generate the impedance code so that a voltage of the calibration node has a voltage level between a first reference voltage and a second reference voltage, and a reference voltage generation unit configured to generate the first reference voltage and the second reference voltage in response to the impedance code.

Abstract: A single terminal is used to configure an integrated circuit into one of three states. A circuit within the integrated circuit is coupled to the terminal and determines whether the terminal: 1) is coupled by a low impedance to a voltage source, or 2) is coupled by a medium impedance to the voltage source, or 3) is floating or substantially floating. The circuit asserts a first digital logic signal when the circuit determines that the terminal is coupled by the low impedance to the voltage source. The circuit asserts a second digital logic signal when the circuit determines that the terminal is coupled by the medium impedance to the voltage source. The circuit asserts a third digital logic signal when the circuit determines that the terminal is floating or substantially floating. The terminal and circuit are particular suited for use in a Power Management Unit (PMU) Integrated Circuit.

Abstract: A semiconductor circuit includes a pad, a pad driver connected to the pad at an output terminal thereof and configured to calibrate a voltage of the pad in response to code signals, a comparison section configured to compare a reference voltage and the voltage of the pad and generate a comparison signal, and a code generation section configured to calibrate code values of the code signals in response to the comparison signal.

Abstract: A compensation circuit for controlling a variation in output impedance of at least one buffer circuit includes a monitor circuit having a pull-up portion comprising at least one PMOS transistor and a pull-down portion comprising at least one NMOS transistor. The monitor circuit is configured to track an operation of an output stage in the buffer circuit and is operative to generate a first control signal indicating a status of at least one characteristic of corresponding pull-up and pull-down portions in the output stage over variations in PVT conditions to which the buffer circuit may be subjected. The compensation circuit further includes a control circuit generating first and second sets of digital control bits for compensating the pull-up and pull-down portions in the output stage over prescribed variations in PVT conditions. The second set of digital control bits is generated based at least on the first set of digital control bits and the first control signal.

Abstract: A constant impedance driver provides controlled output slew rates. The driver includes a plurality of buffers, each with an output impedance that is multiple of the output impedance of the driver. Outputs of buffers are coupled in parallel to form the output of the driver. Inputs to the buffers are coupled to an input signal or delayed versions of the input signal. The buffer inputs may be selectively coupled to taps of a delay line to provide selected slew rates on the output of the driver. The buffers may be selectively enabled to change or calibrate the output impedance of the driver.

Abstract: A signal transceiver apparatus suitable for a wired signal transceiver system includes a differential signal transmitter, an impendence matching control module and a signal receiver. The signal transmitter has an output terminal which is connected to a transceiver wire. The signal transmitter includes a first impendence tuner and is used to receive a control signal so as to tune impendence of the first impendence tuner according to the control signal. Moreover, the impendence matching control module generates the control signal according to a compare signal and a lock signal. Besides, the signal receiver generates the lock signal and the compare signal according to a compare result between a current flowing through the first impendence tuner and a reference current.

Abstract: Certain embodiments described herein include a memory module having a printed circuit board including at least one connector configured to be operatively coupled to a memory controller of a computer system. The memory module further includes a plurality of memory devices on the printed circuit board and a circuit including a first set of ports operatively coupled to at least one memory device. The circuit further includes a second set of ports operatively coupled to the at least one connector. The circuit includes a switching circuit configured to selectively operatively couple one or more ports of the second set of ports to one or more ports of the first set of ports. Each port of the first set and the second set comprises a correction circuit which reduces noise in one or more signals transmitted between the first set of ports and the second set of ports.

Abstract: An impedance control signal generation circuit includes an impedance control signal generation unit configured to generate an impedance control signal in response to a command, a storage unit configured to latch and output the impedance control signal in response to an update pulse signal, a control unit configured to determine whether the impedance control signal is within a predetermined range and generate an update enable signal according to a determination result, and a prohibition unit configured to control input of the update pulse signal to the storage unit in response to the update enable signal.

Abstract: Various embodiments of an on-die termination (ODT) signal generating circuit are disclosed. In one exemplary embodiment, the ODT signal generating circuit includes a latency unit and an ODT control signal generating unit. The latency unit is configured to receive a clock signal and an ODT signal. The latency unit is configured to delay the ODT signal by a predetermined time to generate a first ODT signal. The latency unit is also configured to delay the ODT signal by less than the predetermined time to generate a second ODT signal. The ODT control signal generating unit is configured to provide either one of the first and second ODT signals as an ODT control signal in response to a control signal.

Abstract: Embodiments of a memory controller are described. This memory controller communicates signals to a memory device via a signal line, which can be a data signal line or a command/address signal line. Termination of the signal line is divided between an external impedance outside of the memory controller and an internal impedance within the memory controller. The memory controller does not activate the external impedance prior to communicating the signals and, therefore, does not deactivate the external impedance after communicating the signals. The internal impedance of the memory controller can be enabled or disabled in order to reduce interface power consumption. Moreover, the internal impedance may be implemented using a passive component, an active component or both. For example, the internal impedance may include either or both an on-die termination and at least one driver.

Abstract: A transceiver system includes a first semiconductor device having a first input/output (I/O) pad connected with an I/O channel and a second semiconductor device having a second I/O pad connected with the I/O channel. The first semiconductor device is configured to terminate the first I/O pad with a first voltage when data is received, and maintain the first I/O pad and the I/O channel at the first voltage when data is transmitted. The second semiconductor device is configured to terminate the second I/O pad with a second voltage higher than the first voltage when data is received, and maintain the second I/O pad and the I/O channel at the second voltage when data is transmitted.

Abstract: An I/O driver has v/i characteristic control for maintaining a substantially flat output impedance response using a transmission gate configuration at an I/O output pad. The configuration includes a linear resistive element electrically connected at an I/O pad for limiting a processed data I/O signal, an active impedance element for receiving and processing the data signal, which comprises data represented by a series of voltage state transitions, and pull-up and pull-down array calibration words, for generating and outputting a processed I/O output signal to the resistive element to output a substantially flat v/i response at switching of the data signal.

Abstract: Described are integrated-circuit die with differential receivers, the inputs of which are coupled to external signal pads. Termination legs coupled to the signal pads support multiple termination topologies. These termination legs can support adjustable impedances, capacitances, or both, which may be controlled using an integrated memory.

Abstract: An impedance adjustment circuit for adjusting a terminal resistance includes a resistance evaluation unit and a terminal resistor unit. The resistance evaluation unit is utilized for evaluating a ratio of an off-chip resistor and a basic resistor to generate a control signal by a successive approximation method. The terminal resistor unit is coupled to the resistance evaluation unit, and is utilized for deciding a number of shunt basic resistors to provide a matched terminal resistance according to the control signal.

Abstract: A clock driving circuit and a method of driving a plurality of output lines for a PC architecture are disclosed. The clock driving circuit includes a clock generating circuit coupled to an output buffer for the PC having a plurality of output lines connected to a plurality of output loads having output load impedances. The output lines are driven differentially at an output voltage lower than a supply voltage. The circuit includes a voltage node having a voltage node impedance. The voltage node is maintained at substantially the output voltage. The circuit includes a current sinking transistor that sinks current from the voltage node. The current sinking transistor is operated in a linear region characterized by an ohmic resistance determined by the size of the current sinking transistor. The impedance of the voltage node is matched to one of the load impedances by sizing the current sinking transistor.

Abstract: This document discusses, among other things, output slew rate control. Methods and structures are described to provide slew rate control of an output driver circuit such as a DRAM output driver on a die. A selectable combination of series coupled transistors are configured as a parallel array of complementary inverter pairs to provide a divided voltage to a calibrator. The calibrator is configured to respond to a differential voltage to adjust the divided voltage such that the differential voltage is forced to zero. The calibrator outputs a plurality of discrete signals from an up/down counter to switch on and off the individual transistors of the parallel array to increase and decrease a collective current. In some embodiments, transistor channel currents are modulated to step-adjust a voltage based on a ratio associated with a static resistance. In various embodiments, the divided voltage is an analog voltage based on a resistance associated with trim circuitry.

Abstract: In performing calibration, a control circuit in a calibration circuit of an interface circuit controls a selector so that voltages V1, VREF or voltages V1, V2 are applied to a comparator. The two voltages input to the comparator is switched between positive and negative inputs of the comparator. In both of the states, the control circuit obtains signal values of variable-resistor control signals UPCODE, DNCODE at a time when an output of the comparator is changed, and obtains calibration data to control the resistance value of the terminating resistor by using a mean value of the obtained signal values.

Abstract: Hybrid frequency compensation is provided. Hybrid circuits are used to subtract the transmit signal from the receive signal in a full duplex communication system. Since the hybrid circuit and the main line driver are exposed to different loads, accurate subtraction is difficult to achieve. A frequency dependent network is used to match the loading seen by the driver and the hybrid. The compensation network can be based on active and/or passive components.

Abstract: Current-mode transmission is implemented in a cascode amplifier by splitting a cascode circuit into a front end and a back end to ensure wideband current-mode transmission of an audio signal. A transmission cable is located between the high impedance output of the first end and the low impedance input of the back end. The front end includes a first amplifying device, and the back end includes a second amplifying device. The front end is phantom powered by the back end using the same electrical conductors that carry the current-mode signal over the transmission cable.

Abstract: A data output circuit includes a main driver including a pull-up driver, coupled between a power supply terminal and a node coupled to the pad and a pull-down driver coupled between the node and a ground terminal, an impedance controller configured to control an output impedance at the node by sensing a voltage at the node and to generate pull-up control signals and pull-down control signals based on the sensed voltage, and a pre-driver configured to control driving strengths of the pull-up driver and the pull-down driver in response to the pull-up control signals, the pull-down control signals, and data.

Abstract: To suppress the number of clocks needed to adjust the impedance of an output buffer. A pull-up replica buffer is connected between a calibration terminal and power supply wiring, and is controlled in impedance by a DRZQP signal supplied from a counter. A pull-down replica buffer is connected between ground wiring and a connection node A, and is controlled in impedance by a DRZQN signal supplied from the counter. More specifically, the DRZQP signal and the DRZQN signal indicate count values. The impedances of the replica buffers are increased or decreased stepwise in proportion to the count values. The count values are updated according to a binary search method.

Abstract: A communication system having first and second states for use with a shared transmission line composed of at least two conductors and composed of first and second transmission line segments connected to each other at a single connection point. In the first state, a termination is coupled to the single connection point and is operative to at least attenuate a signal propagated between the first and second segments. In the second state, a driver is coupled to the connection point and is operative to conduct a signal over the first and second segments.

Abstract: Embodiments of a memory controller are described. This memory controller communicates signals to a memory device via a signal line, which can be a data signal line or a command/address signal line. Termination of the signal line is divided between an external impedance outside of the memory controller and an internal impedance within the memory controller. The memory controller does not activate the external impedance prior to communicating the signals and, therefore, does not deactivate the external impedance after communicating the signals. The internal impedance of the memory controller can be enabled or disabled in order to reduce interface power consumption. Moreover, the internal impedance may be implemented using a passive component, an active component or both. For example, the internal impedance may include either or both an on-die termination and at least one driver.

Abstract: In described embodiments, automatic de-emphasis setting is provided for driving a capacitive backplane. Line impedance and line length of a transmission (TX) device are measured that form a load impedance of a driver. For some exemplary embodiments, the line impedance is predominantly a line capacitance, and such embodiments detect this capacitance. Measured line impedance is converted to a control signal (such as, for example, a three bit digital control signal) which automatically sets the de-emphasis of the TX stage. With the amount of capacitance and the length of the transmission line, the appropriate de-emphasis settings might be determined, and such de-emphasis setting be applied by the transmitter to the driver to compensate for transmission line effects.

Abstract: The invention relates to an interfacing device for transmission through interconnections used for sending a plurality of electrical signals. The interfacing device of the invention comprises signal terminals and a common terminal. A transmitting circuit receives the input signals of the transmitting circuit coming from a source and delivers, when the transmitting circuit is in the activated state, currents to the signal terminals, each of the currents being mainly determined by one or more of the input signals of the transmitting circuit, one or more of the currents being not mainly determined by only one of the input signals of the transmitting circuit. The balancing circuit is such that, when the transmitting circuit is in the activated state, the current flowing out of the common terminal approximates the opposite of the sum of the currents flowing out of the signal terminals.