Abstract: Aspects disclosed in the detailed description include skew control for three-phase communication. A three-phase communication involves three signal branches. A signal skew may occur when one signal branch is being coupled to a common mode voltage while another signal branch is being decoupled from the common mode voltage. In this regard, in one aspect, an impedance mismatch is introduced in the signal branch being coupled to the common mode voltage to help shift a rightmost crossing of the signal skew leftward. In another aspect, a current source or a current sink is coupled to the signal branch being decoupled from the common mode voltage to help shift a leftmost crossing of the signal skew rightward. By shifting the rightmost crossing leftward and the leftmost crossing rightward, it is possible to reduce the signal skew, thus leading to reduced jitter and improved data integrity in the three-phase communication.

Abstract: A voltage converting device includes first and second stage circuits for converting a differential voltage to an output signal that has a magnitude smaller than the differential voltage. The second stage circuit includes input transistors for receiving voltages from the first stage circuit, output transistors for outputting the output signal, and a clamp module to clamp voltages at the input transistors of the second stage circuit.

Abstract: An ODT circuit capable of generating an OCD/ODT code and/or a reference voltage adaptively adjusted according to a system environment is disclosed. The ODT circuit comprises a system environment detector, an OCD/ODT replica circuit, an OCD/ODT code generator and an OCD/ODT unit. The system environment detector detects a supply voltage to generate a voltage code, detects an operating temperature to generate a temperature code, and detects an operating frequency to generate a frequency code. The OCD/ODT code generator generates a pull-up code and a pull-down code currently optimized for a semiconductor memory device based on a pull-up reference voltage, a pull-down reference voltage, the voltage code, the temperature code and the frequency code.

Abstract: A transmission line driver circuit includes: a transmission line driving amplifier having a first transmission terminal and a second transmission terminal; a first signal node; a second signal node; a first adjustable resistor positioned between the first transmission terminal and the first signal node; a second adjustable resistor positioned between the second transmission terminal and the second signal node; a first voltage difference generating circuit coupled with two terminals of the first adjustable resistor to generate a first voltage difference value; a second voltage difference generating circuit coupled with two terminals of the second adjustable resistor to generate a second voltage difference value; sample-and-hold circuits for generating sampled signals according to the first voltage difference value and the second voltage difference value; a comparing circuit for comparing the sampled signals; and an adjusting circuit for adjusting resistance of the first and/or second adjustable resistors accor

Abstract: To decrease the circuit scale necessary for the calibration of the output circuit and to decrease the time required for the calibration operation. The invention includes a first output buffer and a second output buffer that are connected to a data pin, and a calibration circuit that is connected to a calibration pin. The first output buffer and the second output buffer include plural unit buffers. The unit buffers have mutually the same circuit structures. With this arrangement, the impedances of the first output buffer and the second output buffer can be set in common, based on the calibration operation using the calibration circuit. Consequently, both the circuit scale necessary for the calibration operation and the time required for the calibration operation can be decreased.

Abstract: Apparatuses, sense circuits, and methods for controlling a clock signal to a clock tree is described. An example apparatus includes a consecutive write command detection circuit configured to detect whether a next write command is received within a consecutive write command period of a current write command responsive to the current write command provided at an output of the write command register. The example apparatus further includes a clock signal control circuit coupled to the consecutive write command detection circuit and configured to control a clock signal to an input/output (I/O) latch based on whether the consecutive write command detection circuit detects that the next write command is within the consecutive write command period.

Abstract: An image processing device for processing an image signal is provided. The image processing device includes a circuit board, a slot and an image processing module. The slot, disposed on the circuit board, is to be plugged in by either a first connector corresponding to a first image interface format or a second connector corresponding to a second image interface format. The image processing module, disposed on the circuit board and coupled to the slot, detects the image signal inputted from either the first connector or the second connector to determine a target image interface format, and processes the image signal by an image processing method corresponding to the target image interface format.

Abstract: A DC-DC converter, which provides a converter output voltage using a DC source voltage, is disclosed. The DC-DC converter includes converter control circuitry and a boosting charge pump. The converter control circuitry selects one of a first boost operating mode, a second boost operating mode, and a boost disabled mode based on the DC source voltage. During the boost disabled mode, the boosting charge pump presents a high impedance at a charge pump output of the boosting charge pump. Otherwise, the boosting charge pump provides a charge pump output voltage. During the first boost operating mode, a nominal value of the charge pump output voltage is equal to about one and one-half times the DC source voltage. During the second boost operating mode, a nominal value of the charge pump output voltage is equal to about two times the DC source voltage.

Abstract: A semiconductor device includes an output circuit having a plurality of unit buffer circuits, an impedance of each unit buffer circuit of the plurality of unit buffer circuits being adjustable, a control circuit configured to selectively activate one or more unit buffer circuits of the plurality of unit buffer circuits, and an impedance adjustment unit configured to adjust the impedance of each of the unit buffer circuits of the plurality of unit buffer circuits. The impedance adjustment unit includes a first power line, a replica circuit, and a load current generation circuit. The replica circuit and the load current generation circuit are coupled in common to the first power line, the replica circuit has a replica impedance that is substantially equal to the impedance of the output circuit, and the load current generation circuit changes current flowing therethrough.

Abstract: A driver circuit drives data to an output based on an input data signal in a transmission mode. The driver circuit includes transistors. A comparator generates a comparison output in a calibration mode based on a reference signal and a signal at the output of the driver circuit. A calibration control circuit adjusts an equivalent resistance of the transistors in the driver circuit based on the comparison output in the calibration mode. The equivalent resistance of the transistors in the driver circuit can be adjusted to support the transmission of data according to multiple different data transmission protocols using transmission links having different characteristic impedances. The equivalent resistance of the transistors in the driver circuit can also be adjusted to compensate for resistance in the package routing conductors and/or to compensate for parasitic resistance.

Abstract: An IO driver for an integrated circuit and a method for calibrating such an IO driver are provided. The IO driver comprises a plurality of IO driver cells, a plurality of IO partial driver cells and an external resistor. The IO driver cells control IO operations for a corresponding plurality of data channels of the integrated circuit. The IO partial driver cells are coupled to respective cells of the plurality of IO driver cells. The external resistor provides a reference impedance. The reference partial driver cell is coupled to the external resistor and is arranged to determine the reference impedance and to provide information depending on the reference impedance to the IO partial driver cells. The IO partial driver cells are arranged to calibrate the respective IO driver cells based on the provided information.

Abstract: This invention aims at reducing the probability of short-circuiting between terminals in a display device in which an IC driver is connected by COG. Terminals for connection with the IC driver are formed in a terminal region of a TFT substrate. The terminals are each comprised of a terminal metal, a first through-hole formed in a first insulation film, a second through-hole formed in a second insulation film, a first ITO formed in the first through-hole and being in contact with the terminal metal, and a second ITO formed over the first ITO. The second ITO is formed within an area where the second ITO is in contact with the first ITO but is not formed outside the second through-hole. This ensures that the distance between the ITOs of the adjacent terminals can be enlarged, whereby the probability of short-circuiting between the terminals can be lowered.

Abstract: Described are integrated-circuit die with differential receivers, the inputs of which are coupled to external signal pads. Termination legs coupled to the signal pads support multiple termination topologies. These termination legs can support adjustable impedances, capacitances, or both, which may be controlled using an integrated memory.

Abstract: A high-speed data transmission interface circuit used in a network switch device is provided. The high-speed data transmission interface circuit comprises a main circuit hoard, a connector and a daughter circuit board. The main circuit board comprises a transmission port interface module and a first wire. The transmission port interface module comprises a reduced pin extended attachment unit interface (RXAUI). The first wire connects the connector and the main circuit board. The daughter circuit board comprises a high definition multimedia interface (HDMI) module and a second wire. The HDMI module is connected to an external network device through a HDMI signal wire. The second wire connects the connector and the HDMI module. The transmission port interface module communicates with the external network device through the connector and the daughter board.

Abstract: A device includes a data output terminal, an output buffer including n first transistors (n is a natural number greater than 1) connected in parallel with the data output terminal, and a calibration circuit to output an n-bit first code signal for controlling each of the n first transistors. In some embodiments, the calibration circuit includes a first counter circuit to output a k-bit second code signal (k is a natural number less than n), and a first code conversion circuit to convert the k-bit second code signal to the n-bit first code signal. Additional apparatus, systems, and methods are disclosed.

Abstract: A semiconductor system may include a first semiconductor device including a first pad, a second pad and a first test input pad, and suitable for storing data inputted in series through the first test input pad and outputting the stored data in parallel through the first pad and the second pad; a second semiconductor device including a third pad, a fourth pad and a second test output pad, and suitable for storing data inputted in parallel through the third pad and the fourth pad, a first through via connecting the first pad and the third pad so that the stored data outputted in parallel through the first pad is inputted in parallel through the third pad; and a second through via connecting the second pad and the fourth pad so that the stored data outputted in parallel through the second pad is inputted in parallel through the fourth pad.

Abstract: Disclosed herein is a semiconductor device that includes a first circuit comprising a plurality of first logic elements coupled in cascade and configured, in response to first and second clock signals and a control signal, to produce control information that indicates a first number of the first logic elements through which the control signal has been propagated during a period defined by a first change in logic level of the first clock signal and by a second change in logic level of the second clock signal, the first and second changes occurring adjacently to each other in same directions as each other, and a second circuit comprising a delay circuit configured to receive the first clock signal and the control information and to produce a third clock signal by delaying the first clock signal by an amount responsive to the control information.

Abstract: Apparatus and methods for digital-to-analog conversion are disclosed. In one embodiment, an electronic system includes a bias circuit and a digital-to-analog converter (DAC) including an input that receives a digital input signal and an output that drives a transmission line. The digital input signal can be used to control a magnitude and polarity of an output current of the DAC. The DAC further includes one or more p-type metal oxide semiconductor (PMOS) termination transistors that receive a first bias voltage from the bias circuit and one or more n-type metal oxide semiconductor (NMOS) termination transistors that receive a second bias voltage from the bias circuit. The bias circuit controls the voltage levels of the first and second bias voltages to control the termination transistors' small signal resistance to actively terminate the DAC's output.

Abstract: A calibration circuit of a semiconductor apparatus may include: a reference voltage generator suitable for generating first and second pull-up reference voltages based on a pull-up control signal, and generating first and second pull-down reference voltages based on a pull-down control signal; and a calibrator suitable for generating a pull-up resistor code corresponding to an external reference resistor based on the first and second pull-up reference voltages, and generating a pull-down resistor code corresponding to the external reference resistor based on the first and second pull-down reference voltages and the pull-up resistor code.

Abstract: A comparison circuit includes: an offset removal unit configured to store offset information of a comparator in response to a reference voltage, and compare a pad voltage with the reference voltage based on the offset information to drive a first node; and a comparison signal output unit configured to buffer a signal of the first node and output a comparison signal.

Abstract: A non-volatile memory device determines, based at least partly on a first multi-bit device address received via a signaling interface and an incoming chip-select signal, whether the device is to participate in a memory access transaction by receiving or outputting data via an I/O node of the signaling interface. Based at least in part on that determination, on-die termination circuitry within the non-volatile memory device switchably couples or decouples a termination resistance between the I/O node and a supply voltage node during a data transmission phase of the memory access transaction.

Abstract: A memory controller transmits a plurality of control values to a non-volatile memory device together with one or more programming commands. The plurality of control values include (i) a first control value that specifies a first termination resistance to be applied to an I/O node of the non-volatile memory device during an interval in which a first data signal transmitted on a bidirectional signaling line coupled to the I/O node is to be received within the non-volatile memory device and (ii) a second control value that specifies a second termination resistance to be applied to the I/O node during an interval in which a second data signal is transmitted on the bidirectional signaling line by another non-volatile memory device.

Abstract: In a non-volatile memory device having an array of non-volatile storage elements, control information received via one or more control input nodes indicates, at different times, that (i) data signals representative of data to be stored within the array of non-volatile storage elements are to be received via a plurality of input/output (I/O) nodes of the non-volatile memory device, and (ii) data signals representative of data read from the array of non-volatile storage elements are to be output via the plurality of I/O nodes. First termination elements are switchably coupled to and decoupled from the I/O nodes based at least in part on the control information, and second termination elements are switchably coupled to and decoupled from the one or more control input nodes based at least in part on the control information.

Abstract: An identifier value stored within a programmable register of a memory device is compared with a selector address received, together with a memory access command, via a signaling interface having at least one I/O node coupled to a bidirectional signaling line. On-die termination circuitry is transitioned between first and second states or maintained in one or the other of the first and second states based, at least in part, on whether the selector address matches the identifier value, with transition to the first state including switchably coupling a first termination resistance between the I/O node and a supply voltage line.

Abstract: On-die termination circuitry within a non-volatile memory device applies a first termination resistance to an I/O node in response to a data storage command indicating that a data signal conveyed on a bidirectional signaling line is to be received within the non-volatile memory device via the I/O node, and applies a second termination resistance to the I/O node in response to information indicating that another memory device is to output a data signal onto the bidirectional signaling line.

Abstract: Methods of changing a centerline voltage of a data signal are described, along with apparatuses to change the centerline voltage. In one such method, portions of a termination circuit coupled to an output pin are selectively activated to change an impedance of the termination circuit to change the centerline voltage of the data signal driven to the output pin. One such apparatus includes pull-up impedances and pull-down impedances that can be activated to change the centerline voltage of the data signal. Additional embodiments are also described.

Abstract: An apparatus is described that includes a combined drive and termination circuit programmable to interface to DDR2 and DDR3 memory modules. In an exemplary embodiment the apparatus includes a combined output/termination driver, an input driver and a calibration subsystem. The combined output/termination driver includes a number of pull-up circuits and a number of pull-down circuits. One of the pull-up circuits presents a fixed output impedance. The rest of the pull-up circuits have an impedance programmable between two desired impedance values. One of the pull-down circuits presents a fixed output impedance. The rest of the pull-down circuits have an impedance programmable between two desired impedance values. The necessary number of pull-up circuits and pull-down circuits is activated in order to provide a desired driving and termination circuit such as to interface to specific impedance values as defined by the DDR2 and DDR3 interface protocol.

Abstract: An impedance adjustment circuit includes a counter circuit outputting a count value thereof as a plurality of first impedance adjustment signals, a mode selection circuit setting a second impedance adjustment signal to be in an active/inactive state irrespective of the count value, and a level fixing circuit fixing a third impedance adjustment signal to be in an active state. A pre-stage circuit generates a plurality of first output control signals, a second output control signal, and a third output control signal in response to the first impedance adjustment signals, the second impedance adjustment signal, and the third impedance adjustment signal, respectively, and a data signal. An output circuit includes a plurality of first transistors, a second transistor, and a third transistor connected in parallel to each other between an output terminal and a first power supply wiring.

Abstract: A method includes communicating over an interface between a controller and multiple memory dies, which comprise respective on-die terminations (ODTs) that are each connectable to the interface by the controller. A plurality of termination settings are evaluated, each termination setting specifies a respective subset of the ODTs to be connected to the interface, so as to identify a preferred termination setting in which the communication quality with a given memory die meets a predefined criterion. Subsequent communication with the given memory die is performed while applying the preferred termination setting.

Abstract: Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including first and second transmitter-receivers that execute transmission and reception of data through a signal line. The first transmitter-receiver includes a first termination circuit that includes a first resistor and a first switch, the first resistor being provided between a first power supply terminal and the signal line, the first switch controlling a current flowing through the first resistor to be turned on and off, and a control circuit that outputs a first control signal to the first termination circuit so that the first switch is turned on when the first transmitter-receiver receives data, the first switch is turned off when the first transmitter-receiver transmits the data, and the first switch is continuously on during a first predetermined period after receiving the data when the first transmitter-receiver further receives another data after receiving the data.

Abstract: An on-die termination (ODT) circuit includes a calibration unit, an offset-code generating unit, an adder, and an ODT unit. The calibration unit generates a pull-up code and a pull-down code. The offset-code generates a pull-up offset code and a pull-down offset code based on a mode-register-set signal, the pull-up code, and the pull-down code. The adder adds the pull-up offset code and the pull-down offset code to the pull-up code and the pull-down code, respectively, and generates a pull-up calibration code and a pull-down calibration code. The ODT unit changes ODT resistance in response to the pull-up calibration code and the pull-down calibration code.

Abstract: Systems and method for operating a low power universal serial bus are described herein. A universal serial bus port includes a link layer and protocol layer that are compatible with a standard USB2 protocol. The link layer and protocol layer to control a physical layer for transmitting and receiving data on a pair of signal lines. The physical layer includes a fully-digital Low-Speed/Full-Speed (LS/FS) transceiver to transmit and receive data on the pair signal lines using single-ended digital communications on the pair of signal lines.

Abstract: A wideband harmonic trap includes a first resonant tank in the form of a parallel LC circuit, and a second resonant tank in the form of a series LC circuit. The LC circuits are connected to a common input, an output of the parallel LC circuit is connected to a load and to ground via a shunt capacitor, and an output of the series LC circuit is connected to the ground.

Abstract: The present disclosure includes devices, methods, and systems supporting on unit termination. A number of embodiments include a number of memory units, wherein a memory unit includes termination circuitry, and a memory unit does not include termination circuitry.

Abstract: A system for use with a transmitter and an antenna includes a radio frequency power detection portion, a tunable matching network, and a phase lock loop. The tunable matching network has a modifiable impedance to account for impedance mismatch between the transmitter and the antenna. The phase lock loop tunes the tunable matching network to modify the modifiable impedance.

Abstract: A device includes a transmission circuit that is configured and arranged to transmit data in accordance with a signal bus protocol that uses passive bias to set a signal bus to a recessive value in the absence of an actively-driven signal value. The transmission circuit includes a first driver circuit that is configured and arranged to actively drive the signal bus to a dominant value that is different from the recessive value. The transmission circuit also includes a second driver circuit that is configured and arranged to actively drive the signal bus to the recessive value. A control circuit is configured and arranged to disable the second driver circuit in response to the device operating in a first data transmission mode, and to enable the second driver circuit in response to the device entering a second transmission mode.

Abstract: In a non-volatile memory device having an array of non-volatile storage elements, command, address and data signals are received at respective times via a time-multiplexed external signaling line, the data signals representing data to be stored within the array of non-volatile storage elements. A control signal is received via a signaling path external to the non-volatile memory device, and an on-die termination element is switchably coupled to the time-multiplexed signaling line at least in part in response to a transition of the control signal from a first logic state to a second logic state.

Abstract: A semiconductor memory device comprises: a plurality of on-die termination circuits connected to each of a plurality of input/output pads; and a control circuit for controlling the on-die termination circuit. The on-die termination circuit comprises: a pull-up element connected between a first terminal and an output terminal; and a pull-down element connected between the output terminal and a second terminal. The pull-up element is driven by a first pull-up element driver, and the pull-down element is driven by a first pull-down element driver. The control circuit activates a plurality of the on-die termination circuits at different timings.

Abstract: Termination impedance of a digital signal bus is adaptively selected as a function of a present or anticipated state of the bus. A variable termination resistor is arranged in series between a termination switch and a common voltage node at the termination end of each bus conductor. Information regarding the current or anticipated bus state is received from an external device such as a bus controller or may be derived by sensing activity on the bus. For example, clock frequency detection logic coupled to clock lines of the bus senses the current operational speed of the bus. A highest-value termination resistance predetermined to be consistent with reliable bus operation under conditions of the current or anticipated bus state is selected for each bus conductor. A bus conductor termination may be taken to a high impedance state by opening the associated termination switch. Decreased average bus power consumption may result.

Abstract: A method for calibrating an output buffer including adjusting a first impedance code applied to a first plurality of first transistor units connected in parallel between a calibration terminal and a first power supply potential so that the potential on the calibration terminal substantially equals a reference potential, applying the first impedance code to a second plurality of first transistor units connected in parallel between a node and the first power supply potential, adjusting a second impedance code applied to a second transistor unit connected between the node and a second power supply potential so that the potential on the node substantially equals the reference potential, applying the first impedance code to a third plurality of first transistor units connected in parallel between a data terminal and the first power supply potential, and applying the second impedance code to a fourth plurality of second transistor units.

Abstract: In a particular embodiment, a method includes modifying an output impedance associated with the input receiver. In response to modifying the output impedance, the method restricts an output voltage at an output node of the input receiver. Particular embodiments of an input receiver circuit are also disclosed.

Abstract: Apparatuses and methods are disclosed herein, including those, performed by a memory die, that operate to detect that a command on a bus connected to the memory die is addressed to another memory die responsive to a chip select signal, and to change the impedance of an on-die termination circuit of the memory die responsive to the detecting.

Abstract: An integrated circuit includes a data input such as a data pad for receiving an external data signal input and an on-die termination (ODT) information input for receiving ODT information from an external device. An ODT circuit selectively couples a termination resistor to the data pad based on the ODT information. An input buffer is coupled to the data pad for determining data that is input into the pad using a reference voltage. A reference voltage generator is coupled to the input buffer and generates the reference voltage on the basis of the ODT information.

Abstract: The semiconductor device includes: a first die configured to include a first input pad and a first output pad; and a second die configured to include a second input pad and a second output pad. The second die corrects a level of an output voltage in response to a feedback reference voltage applied from the first output pad to the second input pad.

Abstract: The present invention discloses a reception circuit capable of enhancing accuracy of signal reception. The reception circuit includes a variable termination resistance unit, coupled to at least one channel, for utilizing at least one termination resistance corresponding to the at least one channel to perform impedance matching, a receiver, coupled to the at least one channel, for receiving a calibration signal to generate a digital calibration signal, and a data determination control unit, for comparing the digital calibration signal with a predefined data, to adjust the at least one termination resistance.

Abstract: Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing voltages. Comparison circuitry employed to calibrate the reference resistance is also used to calibrate the drive current. Termination elements in some embodiments are divided into two adjustable resistive portions, both of which are designed to minimize capacitive loading. One portion is optimized to produce a relatively high range of adjustment, while the other is optimized for fine-tuning and glitch-free switching.

Abstract: A transmitter includes first to third power supply terminals, a first buffer that is electrically coupled between the first power supply terminal and the second power supply terminal and buffers and outputs a first input signal, and a second buffer that is electrically coupled between the second power supply terminal and the third power supply terminal and buffers and outputs a second input signal that is in a differential relation to the first input signal.

Abstract: A calibration circuit for calibrating a device to be calibrated includes a variable current generator, a device under test and a control unit. The variable current generator is coupled to a first node of a reference voltage and configured to generate a variable current responsive to variations of the reference voltage. The device under test is a copy of at least one portion of the device to be calibrated, and coupled to the variable current generator to derive, at a second node, a voltage dependent on the variable current. The control unit is coupled to the second node to receive the derived voltage and configured to compare the derived voltage with the reference voltage and to generate, based on a comparison result, at least one calibration signal for adjusting an adjustable electrical parameter of the device under test and the device to be calibrated.

Abstract: In a memory module having an integrated-circuit buffer device coupled to one or more integrated-circuit memory devices, the buffer device receives write data signals from an external control component via a set of data inputs, the write data signals indicating write data to be stored within one or more of the memory devices. Logic within the buffer device sequentially applies controllable termination impedance configurations at the data inputs based on an indication received from the control component and an internal state of the buffer device, applying a first controllable termination impedance configuration at each of the data inputs during a first internal state of the buffer device corresponding to the reception of the write data signals on the data inputs, and applying a second controllable termination impedance configuration at each of the data inputs during a second internal state of the buffer device that succeeds the first internal state.

Abstract: An information handling system includes a cable, a backplane, and a processor. The cable is connected to a storage controller of the information handling system. The backplane is configured to connect a drive to the information handling system. The processor is in communication with the cable and with the backplane. The processor is configured to detect a presence of the drive, to output a pulse in response to the detection of the presence of the drive, to determine a first storage technology of the drive in response to the output pulse, to determine a second storage technology of the storage controller, to determine whether there is a misconfiguration between the first storage technology and the second storage technology, and to generate a notification when the misconfiguration is determined.