Abstract: An active termination circuit for clamping a signal on a transmission line in an electronic device is described. The active termination circuit is configured to clamp the signal on the transmission line to one of a first reference voltage level and a second reference voltage level. In one embodiment, the active termination circuit includes a bottom clamping transistor coupled to a first potential having a bottom clamping transistor control node arranged for clamping the signal at about a first reference voltage. The active termination circuit also includes a top clamping transistor coupled to a second potential having a top clamping transistor control node arranged for clamping the signal at about a second reference voltage as well as an inverter unit coupling the transmission line to stabilizing capacitors for stabilizing control node voltages.

Abstract: An inter-chip line transmission circuit in a transmitting chip and complementary receiving circuit in a receiving chip provide the capability to characterize the inter-chip interface by separately generating identical pseudo-random test data at both chips, comparing the data, and recording errors. Preferably, one or both chips can be tuned on an individual line basis to reduce errors by altering threshold detection voltage, signal delay, and/or driver power. The receiver circuit preferably contains counters for counting test cycles and errors, which can be masked for any particular line or type of error. A tunable and characterizable interface in accordance with the preferred embodiment thus supports the accurate determination of low error rates on an individual line basis for various tuning parameter settings.

Abstract: An apparatus comprising a transmit portion and a receive portion. The transmit portion may be configured to present (i) one or more data signals and (ii) a configuration signal, in response to one or more input signals. The receive portion may be configured to receive (i) all of the one or more data signals when operating in a first mode and (ii) less than all of the data signals when operating in a second mode. The first and second modes may be configured in response to the configuration signal.

Abstract: An improved signaling system and method are provided that uses transconductance signaling rather than voltage or current signaling. A transient voltage applied to a first end of a conductor can produce a varying current placed into a low impedance node at a second end of the conductor. The second end is preferably pinned to a fixed voltage value, and the low impedance second end will allow current upon the second end to freely transition, enabling the conductor to arrive at a steady state condition much sooner than with conventional signaling methods. The present transconductance signaling method avoids large changes in voltage along the greater part of the conductor due to a current sent through this resistive conductor. This greatly improves transient behavior as, for example, evidenced by signal rise and fall times for digital signals produced by this transconductance signaling method.

Abstract: An output buffer circuit comprises an input terminal, an output terminal first and second inverters, a pull up control circuit, a pull down control circuit and first and second output transistors. Each of the first and second inverters is connected to the input terminal for outputting a signal having a slow rise up and fall down characteristic. Both of the pull up and pull down control circuits are connected to the input terminal and the output terminal. The pull up control circuit pulls up an output voltage of the first inverter when the output signal of the first inverter has a level lower than a first threshold voltage level. The pull up control circuit stops the pull up operation when the level of the output signal of the first inverter exceeds the first threshold voltage level. The pull down control circuit pulls down an output voltage of the second inverter when the output signal of the second inverter has a level higher than a second threshold voltage level.

Abstract: A high-frequency compatible bidirectional level conversion circuit in which high-voltage port A and low-voltage port B are connected using pass transistor 12, and the side of port A is connected to power supply voltage terminal C using primary and secondary switching circuits 21 and 22 connected in parallel. When port B changes from low level to high level to transmit a level-converted signal from the side of port B to the side of port A, the level at port A rises to turn on primary and secondary switching circuits 21 and 22, and secondary switching circuit 21 turns off after port A has reached the high level. When secondary switching circuit 22 is configured to have a lower impedance than that of primary switching circuit 21, the load capacitance connected to port A is charged by a high current which flows in secondary switching circuit 22 as the level of port A rises. When port B changes from the high level to the low level, secondary switching circuit 22 remains off.

Abstract: A transmission line is terminated by a buffer. The buffer isolates a load from the transmission line using a transmission gate. The transmission gate is turned off and does not conduct most of the time, but turns on when a transition is detected on the transmission line, allowing the transmission line to directly drive the load for a short time. Once the load is switched beyond a logic threshold voltage, the transmission gate is again turned off and a latch or latching transistors driven by the transmission line continue to drive the isolated load to power or ground voltages. Driver transistors are also enabled when the transmission gate is turned on, driving either the output (load) node or the input (transmission line) node with the new data. Feedback from the output node disables the transmission gate and driver transistors once the output has been driven past the logic threshold.

Abstract: A method for reducing leakage power of a logic network comprising the steps of: using (observability) don't care information to identify “sleep states” for individual nets; determining based on probabilistic analysis at least one net in which expected power consumption will be reduced by forcing a net to a particular value during at least a portion of a “sleep state”; and forcing the determined net to the determined value determined portion of that “sleep state”.

Abstract: A high voltage switching device includes a switching circuit for switching a high voltage to an output line and for providing a control signal. The high voltage switching device also includes a switching transistor connected to the switching circuit for switching a low voltage to the output line based upon the control signal. The output signal is controlled by a control circuit that sets up a control loop between the drop in the gate voltage level of the switching transistor and the voltage level of the output line that is controlled by the switching circuit.

Abstract: Transistors having large gate tunnel barriers are used as transistors to be on in a standby state, MIS transistors having thin gate insulating films are used as transistors to be off in the standby state, and main and sub-power supply lines and main and sub-ground lines forming a hierarchical power supply structure are isolated from each other in the standby state so that a gate tunnel current is reduced in the standby state in which a low power consumption is required. In general, a gate tunnel current reducing mechanism is provided for any circuitry operating in a standby state and an active state, and is activated in the standby state to reduce the gate tunnel current in the circuitry in the standby state, to reduce power consumption in the standby state.

Abstract: Power dissipation of a semiconductor integrated circuit chip is reduced when it is operated at an operating voltage of 2.5 V or below. A switching element is provided in each circuit block within the chip. Constants of the switching element are set so that leakage current in each switching element in their off-state is smaller than the subthreshold current of MOS transistors within the corresponding circuit block. Active current is supplied to active circuit blocks, while switching elements of non-active circuit blocks are turned off. Thus, dissipation currents of non-active circuit blocks are limited to leakage current value of corresponding switching elements. Thus, the sum of dissipation currents of non-active circuit blocks is made smaller than the active current in the active circuit blocks. As a result, power dissipation in the semiconductor integrated circuit chip can be reduced even in the active state.

Abstract: A power-up reference circuit and related method that generates a reference voltage in response to the circuit being powered up. The circuit includes a power-up sensing circuit that generates a set signal, a latch to generate and sustain the reference voltage in response to the set signal, and a reset key decoder to receive an N-bit key and in response thereto generate a reset signal that causes the latch to reset. Upon the circuit being powered up, the power-up sensing circuit generates the set signal which sets the latch to generate the reference voltage. The reference voltage can be used by other circuits to initialize their operating conditions. Once the reference voltage has been used, the N-bit key is generated which causes the decoder to generate the reset signal, which in turn, causes the latch to reset. When the latch is reset, the power-up reference circuit consumes substantially no power.

Abstract: A method and apparatus for a multi-level GTL interface signaling buffer utilizing midrail buffer pad clamping are described. The system includes a buffer having a P-kicker pull-up device which pulls up a pad voltage level to an intended overshoot level. A pull-down device pulls down the pad voltage level to a termination voltage level VTT. Consequently, the P-kicker pull-up device and the pull-down device counteract one another to generate a low-voltage midrail overshoot level that is less than or equal to a maximum gate voltage level. The midrail overshoot level that is less than or equal to the maximum gate voltage level in order to prevent gate oxide breakdown to CPU LVGTL input buffer circuits caused by overshoot levels in excess of a maximum gauge voltage level.

Abstract: A circuit for suppressing false operation of a level shift circuit due to a noise transient, the circuit comprising a first transistor coupled to a voltage source of the level shift circuit and being coupled to pass a current when a noise transient is present on the voltage source an output terminal coupled to the first transistor providing as an injected signal a current proportional to the current in the first transistor to at least one level shift transistor of the level shift circuit to prevent false triggering of the level shift circuit due to the noise transient.

Abstract: A bus made up of a plurality of lines is interposed between a driver circuit on the transmitting end and a receiver circuit on the receiving end. An equalizer circuit includes multiple CMOS switches, each of which is connected between two adjacent ones of the bus lines. In changing data to be transmitted through the bus lines, first, the outputs of tristate buffers on the transmitting end should have high impedance and input buffers on the receiving end should be deactivated. Then, an equalize (EQ) signal is asserted, thereby activating the equalizer circuit. While the potential levels on the bus lines are being equalized, these bus lines are all electrically disconnected from a power supply. After the potential levels on the bus lines have been equalized in this manner, the EQ signal is negated and then normal signal transmission is carried out.

Abstract: In one embodiment, a driver impedance control mechanism is adapted for a circuit board. The driver impedance control mechanism comprises (i) an integrated circuit including at least one driver circuit operating as a pull-up driver and a pull-down driver, (ii) a link coupled to an interface pin of the integrated circuit, the interface pin receiving signals from the at least one driver circuit, and (iii) a single resistive element terminating the link and separately compensating the at least one driver when operating as the pull-up driver and the pull-down driver and supplying the same impedance control bits to all driver to have good signal quality over the interface.

Abstract: An active termination circuit for clamping a signal on a transmission line in an electronic device is described. The active termination circuit is configured to clamp the signal on the transmission line to one of a first reference voltage level and a second reference voltage level. In one embodiment, the active termination circuit includes a bottom clamping transistor coupled to a first potential having a bottom clamping transistor control node arranged for clamping the signal at about a first reference voltage. The active termination circuit also includes a top clamping transistor coupled to a second potential having a top clamping transistor control node arranged for clamping the signal at about a second reference voltage as well as an inverter unit coupling the transmission line to stabilizing capacitors for stabilizing control node voltages.

Abstract: A method and apparatus for simultaneously communicating data over a plurality of data links, such as a bus, determines initial logic levels of data to the output on each of the plurality of data links and changes the logic levels, such as inverting the data, of at least some of the data to produce logic level adjusted data in response to determining the initial logic level of the data to reduce switching transitions of simultaneously switched output data over the plurality of data links.

Abstract: An input buffer having a stable trip point over at least process skew and supply voltage variations includes a first inverter stage; a second inverter stage; and an arrangement for compensating for process skew and supply voltage variations. The compensating arrangement is disposed both in the pull-up and pull-down paths, and increases the conductivity of the pull-up path and decreases the conductivity of the pull-down path when the DC trip point of the input buffer falls below nominal. The compensating arrangement also decreases the conductivity of the pull-up path and increases the conductivity of the pull-down path when the DC trip point rises above nominal. The compensating arrangement may include at least one device disposed in each of the pull-up and pull-down paths. The conductivity of these devices may then be controlled by a reference signal that swings about the DC trip point responsive to at least process skew corners and variations in supply voltage.

Abstract: A driver circuit includes a driver and a control device that controls the driver. The control device modifies the power of the driver based on the waveform of the signal (DAT_OUT) to be driven by the driver and/or based on the waveform of the signal output by the driver. Such a driver circuit makes it possible to reduce the energy consumption of the driver and/or the interference caused by the driver to a minimum.

Abstract: A logic isolation circuit has a transmitter circuit for receiving a logic input signal and providing a periodic signal to an isolation barrier, and a receiving circuit for receiving the periodic signal from the isolation barrier and for providing an output signal that indicates the transitions in the logical input signal.

Abstract: A loss of signal condition is evaluated for an input data stream according to a signal strength threshold level. The signal strength threshold level is determined according to a supplied loss of signal (LOS) threshold level. Two hysteresis modes are used to ensure the hysteresis at low LOS threshold levels is sufficient. The first mode uses hysteresis for the signal strength threshold level that is proportional to the LOS threshold level when the LOS threshold level is above a predetermined level. The second mode employs fixed hysteresis for the signal strength threshold level when the LOS threshold level is below the predetermined level. The hysteresis provides a signal strength threshold level that has a greater magnitude on deassertion of a loss of signal indication than on assertion of the loss of signal indication.

Abstract: A system and method for reducing reflections in a transmission line and for recovering energy from the load in the transmission during the process. At least three drive signal levels are utilized. The transition from the second level to the third level during a rising transition and the transition from the second. level to the first level during a falling transition is timed to coincide with the arrival of the reflected signal from the immediately preceding transition. A capacitor is advantageously used as the source for the intermediate drive signal levels and advantageously facilitates energy recovery and conservation.

Abstract: A low-voltage differential dual receiver for a SCSI bus uses a symmetrical driver by doing without a termination bias voltage. The data phase and protocol phase of SCSI communication are separated by using two receivers and optimizing each receiver for its particular function. A high-speed receiver is used when transmitting data at high-speeds, and a lower performance, low-speed receiver is used for other SCSI phases. A built-in offset allows the low-speed receiver to operate correctly during bus arbitration. The built-in offset in the low-speed receiver takes the place of the termination bias voltage in a traditional SCSI bus and is implemented in a variety of ways.

Abstract: A master device in a system including a bidirectional bus and at least one device manages whether the system is in an access state in which the master device permits an access to or from one device or a non-access state in which the master device permits an access to none of the devices. The master device drives the bidirectional bus using a predetermined current to transfer data to or from one device connected to the bidirectional bus when the system is in the access state. When the state of the system changes from the access state to the non-access state, the master device drives the bidirectional bus in order to stabilize the potential of the bidirectional bus to keep the bus potential from changing when the system is in a non-access state, thereby eliminating the need for conventional pull-up/pull-down resistors for stabilizing the bus potential during a non-access state.

Abstract: A buffer driver, driving signals with edge transitions onto a transmission line is controlled to improve slew rate and glitch termination by controlling the driver to have a low impedance during a period when edge transitions are taking place, and upon cessation of edge transitions, controlling the driver to have a high impedance.

Abstract: Described is a control circuit for an output stage for suppressing electrical and electromagnetic interference having a signal input (I), a signal output (O), and a ground terminal, two switch stages (1; 2) which are connected to the signal input (I) and the ground and which have one control terminal and one output terminal each, each switch stage (1; 2) switching over from a first state in which the potential at the output terminal follows the potential at the signal input (I) to a second state in which the potential at the output terminal is drawn to ground when a first or second threshold value (Uin1, Uin2) is exceeded at its control terminal, the control terminal (4) of the first switch stage (1) being connected to an intermediary potential, which is between the potential at the signal input (I) and ground, the output terminal (5) of the first switch stage (1) forming the control terminal of the second switch stage (2), the output terminal of the second switch stage forming the signal output (O) of the co

Abstract: Disclosed is a semiconductor integrated circuit realizing improved operating speed, reduced power consumption in an active mode, reduced power consumption in a standby mode, and reduced area of a chip. A first logic gate using a first pair of potentials VDDL, VSSL having a relatively small potential difference as an operation power source and a second logic gate using a second pair of potentials VDDH, VSSH having a relatively large potential difference as an operation power source commonly use substrate potentials VBP, VBN of MIS transistors. The second logic gate has a relatively high driving capability, and the first logic gate can operate on relatively low power. The MIS transistor has a threshold voltage which increases by a reverse substrate bias and decreases by a forward substrate bias. By commonly using the substrate potential, even in the case where different substrate bias states are generated at both of the logic gates, MOS transistors of the logic gates can be formed in the common well region.

Abstract: A methodology for predicting incidents of ground bounce and using this information for reducing data error caused thereby is described. In one embodiment, data to be clocked into a plurality of output buffers from a first register is read before it goes to the buffers and a determination is made as to what number of bits B will change state, i.e., from a zero to a one or a one to a zero. B is then compared to a predetermined threshold T. If B is greater than T, a wait state or some other indication is issued when the bits are clocked into the I/O buffers.

Abstract: In the present semiconductor integrated circuit device, a buffer is provided between a constant-current source circuit and an internal circuit that becomes a source of noise. The buffer controls the potential of an output node such that the potential of the output node becomes the bias potential. Even when noise is generated on the bias potential line when the internal circuit is in operation, the buffer dampens the noise. Thus, the noise generated in the internal circuit is prevented from adversely affecting the constant-current source circuit, and a stable operation of the internal circuit itself is achieved.

Abstract: An integrated circuit having a CMOS circuit constituted by electrically connecting an n-type well 2, in which p-channel transistor Tp of the CMOS circuit is set, with a supply line Vdd through switching transistor Tps, and electrically connecting a p-type well 3, in which n-channel transistor Tn of the CMOS circuit is set, with supply line Vss through switching transistor Tns. Thermal runaway due to leakage current can be controlled by turning off switching transistors Tps and Tns and supplying potentials suitable for a test to the n-type well 2 and the p-type well 3 from an external unit when the integrated circuit is being tested. Fluctuations of the latch-up phenomenon and operation speed can be prevented by turning on switching transistors Tps and Tns and setting the n-type well 2 and the p-type well 3 to the voltages Vdd and Vss, respectively.

Abstract: An input buffer within an integrated circuit capable of receiving an input signal that complies with the electrical characteristic voltage levels of TTL, LVTTL, SSTL, or GTL, buffering the input signal, and converting the input signal to an output signal having voltage levels acceptable to internal circuitry of the integrated circuits is described. The input buffer will have an adjustable threshold trip point at which the input signal will cause the output signal to change between a first logic state and a second logic state. The adjustable threshold trip point will be determined by an adjustment voltage circuit that is immune to variation in semiconductor processing parameters, power supply voltage and operating temperature.

Abstract: Both buses connected to a bus switch are protected from undershoots. A bus switch transistor is an n-channel metal-oxide-semiconductor (MOS) with its source connected to a first bus and its drain connected to a second bus. An enable gate drives the gate node of the bus switch transistor high to enable or low to disable. Undershoot sensing circuits are attached to the first and second bus. When a low-going transition is detected by an undershoot sensing circuit, an n-channel connecting transistor is turned on, connecting the bus with the low-going transition to the gate node through a grounded-gate n-channel transistor. If an undershoot occurs, it is coupled to the gate node. Since both the gate and source of the bus switch transistor are coupled to the undershoot, the gate-to-source voltage never reaches the transistor threshold and the bus switch transistor remains off.

Abstract: In an ABS control ECU, a power supply output circuit and a power supply monitoring unit are formed on the same chip. A power supply terminal for the power supply output circuit is provided separately from a power supply terminal for the power supply monitoring unit. A ground terminal for the power supply output circuit is provided separately from a ground terminal for the power supply monitoring unit.

Abstract: In accordance with one embodiment of the invention, a system includes an integrated circuit that has a compensation value generator. The compensation value generator processes multiple compensation values to generate a compensation value that may be used by compensation circuitry.

Abstract: A voltage adjusting circuit includes a reference voltage generator generating a reference voltage, a differential amplifier comparing the reference voltage with a distribution voltage, and compensating for a variation of the reference voltage, and a voltage divider dividing a power supply voltage and generating a constant output voltage according to an output from the differential amplifier.

Abstract: A noise suppression circuit for suppressing noises above and below reference voltages is provided. The noise suppression circuit for suppressing noises includes a clamping transistor, a feedback circuit, and a presetting means for presetting an internal latch of the noise suppression circuit to a predetermined state. The predetermined state is a high state or a low state depending upon the type of noise suppression accomplished by the circuit. After the occurrence of a noise coupling event, the clamping transistor restores the state of a data input of a circuit to which the suppression circuit is providing protection. The feedback circuit then turns off the clamping transistor after a predetermined amount of time.

Abstract: An apparatus and method of communicating signals between a 2.5 volt internal circuit and both 3.3 and 5 volt external circuits using a P-well. The apparatus includes a circuit having a P-well control circuit and a number of NMOS transistors. The P-well control circuit is configured to receive a P-well control signal and an external signal, and in accordance therewith selectively generate a P-well voltage. The NMOS transistors are coupled to the P-well control circuit. At least one of the NMOS transistors has a bulk region configured to receive the P-well voltage. The NMOS transistors are further configured to receive a 5 volt signal and in accordance therewith selectively generate a 2.5 volt signal. The NMOS transistors are still further configured to receive a 3.3 volt signal and in accordance therewith selectively generate a 2.5 volt signal.

Abstract: The invention provides a structure and method of generating a clock enable signal in a programmable logic device (PLD). A first embodiment of the invention comprises a clock enable circuit implemented such that the critical paths have only two levels of logic. In this embodiment, the critical paths are implemented in dedicated logic while other portions of the clock enable circuit are implemented using programmable logic. According to another embodiment of the invention, the clock enable circuit is located near the center of a first edge of the device. A first plurality of output registers are located along the first edge on either side of the clock enable circuit, with additional output registers being located along the two adjacent half-edges. Programmable interconnection points (PIPs) permit a clock enable interconnect line along the first edge to be programmably extended to the additional output registers. In another embodiment, the clock enable circuit is duplicated in two opposite edges of the device.

Abstract: To provide a semiconductor integrated circuit having a CMOS circuit constituted by electrically connecting an n-type well 2, in which one transistor Tp for constituting the CMOS circuit is set, with a first power-supply-voltage line Vdd through a switching transistor Tps, and electrically connecting a p-type well 3 in which the other transistor Tn for constituting the CMOS circuit is set with a second power-supply-voltage line Vss through a switching transistor Tns. Moreover, the semiconductor integrated circuit is constituted so that thermal runaway due to leakage current can be controlled by turning off the switching transistors Tps and Tns and supplying a potential suitable for a test to the n-type well 2 and the p-type well 3 from an external unit when the semiconductor integrated circuit is being tested.

Abstract: A technique for reducing standby leakage current in a circuit block using input vector activation. A complex circuit includes a plurality of inputs and one or more transistor stacks. At least some of the transistor stacks are coupled to at least one of the inputs. The circuit also includes logic to apply a selected input vector to the plurality of inputs during a standby mode. The input vector is selected based on a configuration of the one or more transistor stacks in the circuit block to turn off a first number of transistors in the transistor stacks. The first number is within a selected percent of a maximum number of transistors in the transistor stacks that can be turned off by any vector applied at the plurality of inputs.

Abstract: There is provided a driver circuit which does not require a large driving current, even when a logic circuit having a large capacity component is connected as the load. When the input voltage level is “H”, the first driving means inserted between the source and the load is maintained at the on state and it is turned off when it is detected by the first detecting means that the voltage level of the load exceeds the first voltage level. When the input voltage level is “L”, the second driving means inserted between the ground and the load is maintained at the on state and it is turned off when it is detected by the second detecting means that the voltage level of the load is below the second voltage level. The above mentioned first voltage level is higher than the logic threshold of the logic gate for receiving signals from the driver circuit, and the above mentioned second voltage level is lower than the logic threshold of the logic gate for receiving signals from the driver circuit.

Abstract: A CMOS-based bus-hold circuit having overvoltage tolerance. The bus-hold circuit of the present invention includes, in addition to conventional input and latching inverters, a sense circuit and an arbiter circuit designed in combination to block overvoltage events from powering the latching inverter. The sense circuit includes a comparator designed to compare the potential of a standard high-potential power supply rail to the potential associated with a signal applied to the bus-hold circuit's input node. The higher of those two potentials is used to activate the arbiter circuit that in turn couples the higher of those two signals to a pseudo high-potential power rail. The pseudo high-potential power rail is used to supply power to the latching inverter such that the latching inverter will not be activated during overvoltage conditions, particularly when the circuit is in its high-impedance state. The bus-hold circuit may be similarly designed to establish an undervoltage tolerance as well.

Abstract: A programmable variable impedance output driver circuit uses analog biases to match driver output impedance to load input impedance. A current mirror is used to obtain a measurement of an external resistance value for matching the impedance of a driven load. The mirrored current generates the voltage "NBIAS" when passed through the resistively connected NFET. Similarly, the current is again mirrored and passed through a resistively connected PFET resulting in the voltage "PBIAS". The analog bias voltages, NBIAS and PBIAS are used to vary the impedance of complementary FETs in an impedance matched driver for a high degree of dI/dt control. The driver provides a high degree of flexibility because its turn-on and turn-off characteristics do not depend on a combination of digital control signals connected directly to the driving FETs as in the prior art.

Abstract: A ring oscillator using CMOS technology having three logic gates, including a threshold amplifier, where the transistors that set the voltage rise threshold and the voltage drop threshold in the amplifier are controlled by a bias control circuit so that the ratio of voltage rise threshold to the voltage supply diminishes and the ratio of the voltage drop threshold to the voltage supply increases, when the supply voltage falls.

Abstract: An input buffer includes a first CMOS inverter (400) made up of a PMOS transistor (602) connecting Vdd to the buffer output and an NMOS transistor (604) connecting the buffer output to Vss. NMOS transistors (404) and (414) have with series connected source to drain paths to connect the buffer output to Vss in conjunction with transistor (604) of inverter (400). PMOS transistors (402) and (412) have series connected source to drain paths connecting Vdd to the buffer output in conjunction with transistor (602). To control transistors (402, 404, 412 and 414) an inverter (420) is connected from the buffer output to the gates of transistors (402 and 404), and inverters (431, 432, 433, and 440) are connected between the buffer input and the gates of transistors (412 and 414).

Abstract: An integrated circuit such as an ASIC device having partitioned functional units with independent threshold voltage control. A first partition is always operated in a normal mode, while subsequent partitions are maintained in a standby mode until a transition is detected at the input of the first partition. The subsequent partitions are switched to the normal mode by lowering the body voltage applied to the devices with each partition. A pulse stretcher is used to keep a partition in a normal mode for a predetermined period of time after the transition is detected.

Abstract: Method and circuitry for implementing low voltage input buffers using low voltage CMOS transistors are disclosed. Various novel circuit techniques enable the input buffer to safely receive and reliably detect input logic signals in the presence of overshoot or undershoot conditions. In a preferred embodiment, the source terminals of input transistors are biased such that the impact of overshooting or undershooting signals at the input terminal are drastically reduced.

Abstract: A CMOS logic circuit comprises a logic gate having an input node (e.g., a storage node) coupled to a positive supply potential through a p-type field-effect transistor (PFET), with one or more n-type field-effect transistors (NFETs) being coupled between the storage node and a negative supply potential. Since the response of the circuit to a high-energy particle strike is dominated by the N+ diffusion associated with the NFETs when the state of the storage node is high, i.e., a logical "1", the gate has a switching point that is set closer to the negative supply potential than to the positive supply potential.

Abstract: A compensated CMOS receiver includes an inverter, at least one compensation transistor coupled between a first voltage and the output of the inverter, a comparison circuit coupled to the output of the inverter, and a control circuit coupled to the comparison circuit and the compensation transistor. When the receiver is driven to a calibration state, the comparison circuit generates an output signal that reflects the difference between the inverter's output voltage and a switch-point reference. The control circuit adjusts the one or more compensation transistors according to the difference signal generated by the comparison circuit.