Abstract: A signal transmission system includes a transmitter and a receiver connected via a transmission line. When a control circuit 103 in the transmitter 200 outputs a test signal to a transmission line 123, a voltage detection section 112 in the receiver 210 determines whether a voltage value on a terminal 115 falls within a given range or not. Based on the result, the control signal generation section 113 generates an instruction as to whether or not to change the current amount of the driving current. The control circuit 103 in the transmitter 100 drives the transmission line 123 with the driving current increased or decreased based on the instruction, and again outputs a test signal. This process is repeated until the voltage on the terminal 115 of the receiver 210 comes into the range. As a result, an optimum output impedance for the control circuit 103 of the transmitter 200 can be obtained.

Abstract: A control circuit and method for controlling the electrical characteristics of an input/output (I/O) circuit such as an output driver to account for variations in fabrication process, supply voltage, and/or temperature (PVT) conditions includes a PVT controller having appropriate control logic to permit PVT compensation to be observed, tested, and selectively adjusted. The PVT controller permits selection between PVT sensing circuit-provided control signals and control signals stored in a hardware register for controlling drive strength. The PVT controller further provides the capability to offset the selected drive strength by a fixed amount and select whether or not the offset is applied and permits full testability and observability of the selected control signal, an offset value applied thereto, and the resulting output signal.

Abstract: A termination circuit for a transmission line may include an input node, a pull-down circuit, and a pull-up circuit. The input node receives an input signal over the transmission line. The pull-down circuit is coupled between the input node and a first reference voltage, and the pull-down circuit may be configured to provide an electrical path between the first reference voltage and the input node responsive to the input signal having a first voltage level. The pull-up circuit is coupled between the input node and a second reference voltage, and the pull-up circuit is configured to provide an electrical path between the second reference voltage and the input node responsive to the input signal having a second voltage level. More particularly, the first reference voltage is less than the second reference voltage, and the first voltage level is greater than the second voltage level. Related methods are also discussed.

Abstract: A dynamically adjustable signal detector receives a differential input signal and outputs a signal indicative of whether a valid signal is being received based on dynamically adjustable threshold settings. The threshold settings can include differential voltage, peak power, average power, or other suitable settings, and can have a dynamically adjustable value for a selected threshold setting. The threshold settings and the value for a selected threshold setting can be set using control signals that are set by programmable logic resource circuitry, by soft intellectual property programmed into a programmable logic resource, by a processor, by circuitry external to a programmable logic resource, or by user input.

Abstract: This invention provides a storage medium on which there is stored a cell library to design a semiconductor integrated circuit to satisfy low power consumption and high speed operation and a design method using the cell library. The cell library is registered with at least two kinds of cells which are different in delay and power consumption while having the same function and the same shape. To satisfy the specification of the semiconductor integrated circuit, one cell is selected from at least two kinds of cells of the cell library.

Abstract: The strength of the output buffer is changed gradually when there is a transition in the output (or input) value. Due to the gradual change, switching noise is avoided in several contexts (e.g., when driving a transmission line, which causes reflections). In an embodiment, the gradual change is implemented using a combination of a current source and a capacitor. The capacitor is provided at an input of the gate terminal of a drive transistor, and a current source is used to control the rate at which the capacitor discharges. As a result, the drive strength of a buffer is controlled.

Abstract: The present invention provides a method and apparatus is provided for calibrating a driver impedance in an integrated circuit device. The method includes providing a signal from a synchronous circuit that is indicative of an impedance mismatch between a driver circuit and a load. The method also includes selecting one of a plurality of impedances of the driver circuit to reduce the impedance mismatch in response to the signal.

Abstract: When an output voltage output from a buffer approaches a ground voltage, a MOS transistor turns off, so that clamp for a gate of the MOS transistor is released.

Abstract: An output buffer circuit (10, 40, 50) includes an output driver transistor (12), a predriver circuit (14, 54), and a bias generator (16, 54). The predriver circuit (14, 54) has an input terminal for receiving an input signal (IN), a first terminal coupled to a power supply voltage terminal, a second terminal, and an output terminal coupled to the control electrode of the transistor (12). The bias generator (16, 54) is coupled to the second terminal of the predriver circuit (14, 54), and provides a bias voltage (VG) to the second terminal of the predriver circuit (14, 54) for controlling the gate voltage of the output driver transistor (12).

Abstract: A low voltage differential signal (LVDS) input circuit with extended common mode range has been disclosed. One embodiment of the LVDS input circuit includes a first resistor coupled between a differential logic circuit and a first input pad, a second resistor coupled between the differential logic circuit and a second input pad, and a first and a second termination resistors coupled to the first and the second input pads, respectively, the first and second termination resistors being coupled to each other in series at a node to produce a common mode reference voltage at the node. Other embodiments are described and claimed.

Abstract: An output circuit includes a source follower constituted by a n-channel MOS transistor, having a drain connected to a power source and a source connected to an output terminal, and applying an output voltage to a load through the output terminal when a gate is charged, a voltage detector determining if the output voltage is at a first voltage or at a second voltage level, a first discharge circuit discharging the gate of the source follower according to an inputted turn-off signal when the output voltage is at the first voltage level, and stopping discharging the gate of the source follower when the output voltage decreases to the second voltage level and a second discharge circuit discharging the gate of the source follower more gradually than the first discharge circuit does according to the turn-off signal when the output voltage decreases from the first voltage to the second voltage level.

Abstract: A GTL output structure having an active charging and discharging stage that actively restores internal nodes for slew rate control without the need to wait for a slow rise and fall RC time constant is disclosed herein. The novel GTL output structure includes an input stage connected to an RC network for providing slew rate control. The output stage connects between the RC network and a feedback network. The feedback network in includes an active charging stage for providing a charging current to the gate of the at least one transistor for a period of time to the value of a power supply rail and wherein the feedback network includes an active discharging stage for providing a discharge current from the gate of the at least one transistor to ground.

Abstract: This invention has as objects the realization of reduced power consumption in a semiconductor integrated circuit, as well as faster transitions of circuits from a standby state to an operating state. In order to achieve these objects, a semiconductor integrated circuit of this invention comprises a plurality of circuit blocks capable of transitions from an operating state to a standby state and from a standby state to an operating state, and a master unit which controls, in event-driven fashion, the back-gate voltages of transistors forming logic elements of the circuit blocks, based on a finite state machine which stipulates in advance each of the state transitions of the plurality of circuit blocks.

Abstract: A CMOS switching circuit that includes a charge reservoir and a multiplexer connected to the charge reservoir. The multiplexer receives control signals from a delay line and a control signal line, and it delivers a switching signal to an output terminal. A first set of signals delivered to the control terminals of the multiplexer causes the charge reservoir to deliver charge to the output terminal, and a second set of signals delivered to the control terminals causes charging of the charge reservoir. With the charge reservoir, charge from falling signals is conserved and used to help rising signals at the output, reducing the power required to provide an output switching signal.

Abstract: The power supply-voltage dependency of a current source current is reduced and the power supply voltage is lowered. The invention includes an emitter-coupled logic circuit 118 and a reference-voltage generating circuit 119 for generating a reference voltage VCSC for controlling a drain current (=current source current ICS) of a constant current-supplying n-type MOS transistor 110. The emitter-coupled logic circuit 118 comprises a current switch made up of a pair of emitter-coupled bipolar transistors 106 and 107, a constant current-supplying n-type MOS transistor 110 that is connected in series with the current switch, and resistor means 108 and 109 connected in series with the bipolar transistors 106 and 107 individually for obtaining an output voltage.

Abstract: An I/O pad has a data transmitting circuit, a data monitoring control circuit, and a control selection circuit. The control selection circuit controls the data transmitting circuit. When it is enabled, data in the data transmitting circuit are exported to a receiving circuit. When it is disabled, data exportation stops. The data monitoring circuit receives signals of the data transmission circuit and export signals to the control selection circuit. The data monitoring circuit judges whether the data transmission is under a stable condition. If it is not, an unstable signal is exported to a first input end of the control selection circuit. A second input end of the control selection circuit receives an output enabling signal. When the data transmission is stable and the output enabling signal indicates a disable status, the control selection circuit disables the data transmitting circuit. Otherwise, the control selection circuit enables the data transmitting circuit.

Abstract: The invention relates to a method and to a circuit configuration for adjusting the voltage level for the electrical data transmission between a transmitting component and a receiving component of one or different assemblies. According to the invention, the voltage level is increased step-wise or continuously until the required value for the correct representation of the signals to be transmitted is reached in the receiving component. Increase of the voltage level is stopped by the transmission of respective information. The inventive method and circuit are advantageous in that the minimum voltage level required for the transmission of data can be precisely adjusted. Power loss can be thereby reduced and adjacent channel interferences through high voltage levels can be reduced to a minimum.

Abstract: An off chip driver impedance adjustment circuit includes a storage circuit adapted to receive and store a drive strength adjustment word. A counter circuit is coupled to the storage circuit to receive the drive strength adjustment word and develops a drive strength count responsive to the drive strength adjustment word. A programmable fuse code to preset the counter. An output driver circuit is coupled to the counter circuit to receive the drive strength count and is adapted to receive a data signal. The output driver circuit develops an output signal on an output responsive to the data signal and adjusts a drive strength as a function of the drive strength count.

Abstract: An integrated circuit is disclosed herein. One embodiment of the integrated circuit comprises a power supply conductor, a circuit, at least one bypass capacitor, and an electrostatic protection circuit. The circuit may be located on a first piece of silicon, which may be located on a first insulator. The bypass capacitor may be located on a second piece of silicon, which may be located on second insulator. The electrostatic protection circuit may be located on a third piece of silicon, which may be located on a third insulator. The electrostatic protection circuit is connected to the power supply conductor by way of a first line. The bypass capacitor and the circuit are connected to the power supply conductor by way of a second line. The resistance of the second line is greater than the resistance of the first line.

Abstract: Differential power analysis on an integrated circuit is made more difficult by providing a circuit configuration for generating current pulses in the supply current of the integrated circuit. These additional pulses that are generated in the supply current are synchronous with the edges of the internal clock signal of the integrated circuit. In this case, the pulse shape and also the amplitude and the time profile are similar to the pulses in the supply current which are generated by other circuit sections, for example by processors or by some other digital logic, and in digital circuits, typically correspond to a charging curve of a capacitor via a resistor. The circuit generates these additional pulses by using a delay element.

Abstract: A circuit includes a first driver, a second driver, and a transformer coupled to the first and second driver. In operation, the first driver receives a first signal from a first input port, the second driver receives a time-delayed version of the first signal from a second input port, and the transformer provides provide an output signal to an output port. A method includes receiving a first input signal, receiving a second input signal, and then processing the first input signal and the second input signal. The second input signal is a time-delayed version of the first input signal and the processing of the first input signal and the second input signal generates a half-raised cosine signal.

Abstract: An apparatus is described having a feedback loop. The feedback loop has an output that approaches a steady state as a data line voltage approaches a reference voltage. The apparatus also includes a driving transistor that drives the data line. The driving transistor has an output impedance that is controlled by the feedback loop output, the feedback loop output keeps the driving transistor output impedance within a high output impedance region when the feedback loop output reaches the steady state.

Abstract: Semiconductor integrated circuit devices that operate under different power supply voltages are directly interconnected by a bidirectional bus which is a transmission line. A driver is of a push-pull type and a reception side is CTT-terminated. If a terminating resistor is in conformity with the characteristic impedance of the transmission line, the on resistance of the driver is equal to or lower than the characteristic impedance. If the on resistance of the driver is in conformity with the characteristic impedance of the transmission line, the value of the terminating resistor is equal to or lower than the characteristic impedance of the transmission line. If the reception side is VTT-terminated, the value of the VTT is ½ of a lower one of power supply voltages that are supplied to the respective semiconductor integrated circuit devices. The value of the terminating resistor is in conformity with the characteristic impedance of the transmission line.

Abstract: A dynamically adjustable signal detector receives a differential input signal and outputs a signal indicative of whether a valid signal is being received based on dynamically adjustable threshold settings. The threshold settings can include differential voltage, peak power, average power, or other suitable settings, and can have a dynamically adjustable value for a selected threshold setting. The threshold settings and the value for a selected threshold setting can be set using control signals that are set by programmable logic resource circuitry, by soft intellectual property programmed into a programmable logic resource, by a processor, by circuitry external to a programmable logic resource, or by user input.

Abstract: Output buffers are provided that are compatible with any differential output standard. The output buffers compensate for variations in process, the supply voltage, and temperature. The edge rate of an output buffer can be programmed to be compatible with different output standards. The edge rate of an output buffer can compensate for variations in process, voltage, and temperature. The output voltage of an output buffer can be adjusted to be compatible with different output standards.

Abstract: A semiconductor integrated circuit device is composed of logic gates each provided with MOS transistors. The semiconductor integrated circuit device includes a current control device. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors, that have both an operation mode and a low power back-up or sleep mode used for power reduction.

Abstract: The present invention provides a refresh clock generator which optimally controls a period of a refresh clock signal according to temperature variation and outputs the refresh clock signal. The refresh clock generator includes a bias voltage generating unit for generating first and second bias voltages in response to a temperature variation and a clock generator for generating a refresh clock signal having a frequency which is controlled or adjusted based on the first and second bias voltages, wherein the first bias voltage is varied in proportion to the temperature variation; the second bias voltage is varied in inverse proportion to the temperature variation; and the frequency of the refresh clock signal is varied in proportion to the temperature variation.

Abstract: A system and method for reducing reflections in a transmission line and for recovering energy from the load in the transmission during the process. At least three drive signal levels are utilized. The transition from the second level to the third level during a rising transition and the transition from the second level to the first level during a falling transition is timed to coincide with the arrival of the reflected signal from the immediately-preceding transition. A capacitor is advantageously used as the source for the intermediate drive signal levels and advantageously facilitates energy recovery and conservation.

Abstract: An adaptive threshold logic circuit is provided in which the switching threshold levels of the logic circuit are automatically changed to accommodate variations in the level of applied data signals to the switching circuit. A detector stage detects the voltage level of the incoming data signals and selectively adjusts the threshold level of a threshold adaptor stage in accordance with the output of the detector stage. The threshold adaptor stage is essentially an adaptive CMOS inverter having various switching paths turned on or off in accordance with the output of the detector stage.

Abstract: A blocking circuit technique achieves very low Ioff and Ioz leakage in low power digital logic devices that incorporate Ioff and overvoltage tolerance. The blocking circuit employs a diode-connected P-channel device in parallel with a PN diode. The diode-connected P-channel device provides enough forward leakage in the subthreshold region to keep Ioz through the upper output driver to a very low level (0.2 uA typical). Further, both the diode-connected P-channel device and the PN diode together provide enough reverse blocking capability to keep Ioff to a very low level (0.2 uA typical).

Abstract: An integrated circuit having a CMOS circuit constituted by electrically connecting an n-type well 2, in which p-channel transistor Tp of the CMOS circuit is set, with a supply line Vdd through switching transistor Tps, and electrically connecting a p-type well 3, in which n-channel transistor Tn of the CMOS circuit is set, with supply line Vss through switching transistor Tns. Thermal runaway due to leakage current can be controlled by turning off switching transistors Tps and Tns and supplying potentials suitable for a test to the n-type well 2 and the p-type well 3 from an external unit when the integrated circuit is being tested. Fluctuations of the latch-up phenomenon and operation speed can be prevented by turning on switching transistors Tps and Tns and setting the n-type well 2 and the p-type well 3 to the voltages Vdd and Vss, respectively.

Abstract: An embodiment of a graphics device that maintains load balance on a graphics bus when an upgrade graphics device is installed is disclosed. The embodiment includes load balancing buffers for the strobe compliment signals AD_STB0#, AD_STB1#, and SB_STB# on a 2X mode AGP graphics device. The load balancing buffers couple the 2X mode AGP graphics device to the strobe compliment signals AD_STB0#, AD_STB1#, and SB_STB#, but the load balancing buffers are not connected to any internal circuits within the 2X mode AGP graphics device. The load balancing buffers provide equal capacitive loading between the strobe signals AD_STB0 , AD_STB1 , and SB_STB and their compliment signals AD_STB0#, AD_STB1#, and SB_STB# when an upgrade 4X mode AGP graphics device is installed.

Abstract: A logic isolation circuit has a transmitter circuit for receiving a logic input signal and providing a periodic signal to an isolation barrier, and a receiving circuit for receiving the periodic signal from the isolation barrier and for providing an output signal that indicates the transitions in the logical input signal.

Abstract: A circuit configuration for signal balancing in antiphase bus drivers, particularly for a CAN bus, which have, in each driver path of the bus, a driver amplifier unit and an output stage, driven by the latter, having a power transistor circuit for transmitting an antiphase signal using a two-wire line. A control circuit is connected to one of the driver paths and controls the turn-on resistance of the power transistor circuit in this driver path such that the power transistor circuits in the two driver paths have the same turn-on resistance.

Abstract: Techniques of increasing drive strength and reducing propagation delays of a digital logic circuit through the use of feedback are presented. Logic circuitry operative to receive an input signal of the digital logic circuit and a delayed version of an output signal of the digital logic circuit turns “ON” a supplemental drive transistor for a digital state transition of the output signal. The supplemental drive transistor provides supplemental drive current to the digital logic circuit during the output signal digital state transition, thus advantageously reducing propagation delay and increasing fan-out capability. The logic circuitry turns “OFF” the drive transistor once the output signal digital state transition is complete.

Abstract: A circuit receives a first supply voltage on a first terminal where the first supply voltage is used to supply circuitry within the circuit. The circuit includes an input terminal receiving a first signal and an input circuit coupled to the input terminal. The first signal has a logical high value at a second voltage and a logical low value at a third voltage. The second voltage is used to establish a switching threshold of at least some of the input and output signals of the circuit. The input circuit provides a reset signal to circuitry within the circuit causing the circuitry to reset. The reset signal is asserted when the first signal on the input terminal has a logical low value and the third voltage comprises a voltage below a predetermined trigger threshold of the input circuit.

Abstract: A logic isolation circuit has a transmitter circuit for receiving a logic input signal and providing a periodic signal to an isolation barrier, and a receiving circuit for receiving the periodic signal from the isolation barrier and for providing an output signal that indicates the transitions in the logical input signal.

Abstract: An integrated device having a pad receiving, in a standard operative condition, an input signal having a first value and, in a test operative condition, a test voltage having a second value higher than the first value; an input stage connected to the pad and including an electronic component having a first terminal connected to the pad; a third-level detecting stage connected to the pad and supplying a logic third-level signal having a first level in presence of the input signal and a second level in presence of the test voltage; and a selector connected to a second terminal of the electronic component and structured to connect the second terminal to a reference potential in the presence of the first logic level of the third-level signal and to a biasing voltage higher than the reference potential and lower than the second value in the presence of the second logic level of the third-level signal.

Abstract: An inter-block interface circuit which effectively prevents occurrences of inconveniences (for example, such that a shoot-through current flows due to unsteady potential in wiring) caused by switching off a power supply of a block, using simple circuitry, in LSI such that signals are communicated between the blocks and the power supplies of the blocks are interrupted independently. In the circuit, gate circuits 112 and 114 are respectively provided in blocks 102 and 104 that communicate signals with one another, and interface control circuit 202 dynamically controls respective input levels of gate circuits 112 and 114. In other words, the circuit 202 fixes an input level of gate circuit 112 or 114 in a block whose power supply is ON to “L”, and thereby compulsively fixes an output level of the gate circuit to “L”.

Abstract: A programmable device includes a plurality of programmable blocks each associated with a distributed memory block. The programmable blocks may be configured as logic or memory. The addressing circuitry for each distributed memory block may be shared with its associated programmable block or may be separate.

Abstract: A detachable cartridge unit and an auxiliary unit combined forms a functional component for a data processing system. The cartridge unit is configured to receive a variety of auxiliary units in order to form different functional components and perform different functions. The circuit board of the cartridge unit contains circuits and components common to each functional component. The auxiliary unit contains components and circuits unique to the function that the auxiliary unit represents. The cartridge unit comprises a circuit board, a housing containing the circuit board, a first connector coupled to the circuit board for connecting to a data processing system, a second connector coupled to the circuit board, and a grip movably connected to the housing with a hinge.

Abstract: A circuit configuration has a first driver stage for feeding in an input signal and for outputting an amplified signal. A second driver stage, which is connected in parallel with the first driver stage, is fed, on the input side, both the input signal and a control signal from a reference circuit connected upstream. The reference circuit compares the feedback level of an output signal, which level is present at one of its inputs, with the level of the input signal present at its other input and generates the control signal for driving the driver stage in the event that the level of the output signal is lower than the level of the input signal. As a result, the driver stage is connected for additional amplification of the input signal.

Abstract: An output circuit includes: a power supply unit; an output MIS transistor connected to the power supply unit; a reference MIS transistor that is connected to the power supply unit and is invariably in ON state; a current supply unit for generating a reference voltage Vref; an output terminal through which a current is supplied to a load circuit; a comparator; a logic circuit; and a control circuit for carrying out the ON/OFF control of the output MIS transistor. Comparison is made between the reference voltage Vref and output terminal voltage Vout by utilizing the ON-state resistances of the output and reference MIS transistors, thus detecting the magnitude of an output current. If the output current exceeds the target value, the output MIS transistor is turned OFF, thereby protecting it from an excessive current.

Abstract: Disclosed is a semiconductor integrated circuit realizing improved operating speed, reduced power consumption in an active mode, reduced power consumption in a standby mode, and reduced area of a chip. A first logic gate using a first pair of potentials VDDL, VSSL having a relatively small potential difference as an operation power source and a second logic gate using a second pair of potentials VDDH, VSSH having a relatively large potential difference as an operation power source commonly use substrate potentials VBP, VBN of MIS transistors. The second logic gate has a relatively high driving capability, and the first logic gate can operate on relatively low power. The MIS transistor has a threshold voltage which increases by a reverse substrate bias and decreases by a forward substrate bias. By commonly using the substrate potential, even in the case where different substrate bias states are generated at both of the logic gates, MOS transistors of the logic gates can be formed in the common well region.

Abstract: Power dissipation of a semiconductor integrated circuit chip is reduced when it is operated at an operating voltage of 2.5 V or below. A switching element is provided in each circuit block within the chip. Constants of the switching element are set so that leakage current in each switching element in their off-state is smaller than the subthreshold current of MOS transistors within the corresponding circuit block. Active current is supplied to active circuit blocks, while switching elements of non-active circuit blocks are turned off. Thus, dissipation currents of non-active circuit blocks are limited to leakage current value of corresponding switching elements. Thus, the sum of dissipation currents of non-active circuit blocks is made smaller than the active current in the active circuit blocks. As a result, power dissipation in the semiconductor integrated circuit chip can be reduced even in the active state.

Abstract: Disclosed is a semiconductor integrated circuit realizing improved operating speed, reduced power consumption in an active mode, reduced power consumption in a standby mode, and reduced area of a chip. A first logic gate using a first pair of potentials VDDL, VSSL having a relatively small potential difference as an operation power source and a second logic gate using a second pair of potentials VDDH, VSSH having a relatively large potential difference as an operation power source commonly use substrate potentials VBP, VBN of MIS transistors. The second logic gate has a relatively high driving capability, and the first logic gate can operate on relatively low power. The MIS transistor has a threshold voltage which increases by a reverse substrate bias and decreases by a forward substrate bias. By commonly using the substrate potential, even in the case where different substrate bias states are generated at both of the logic gates, MOS transistors of the logic gates can be formed in the common well region.

Abstract: A digital logic interface circuit makes use of a logic signal representative of a logic signaling level definition, to determine the logic swing amplitude of signals from a given source adopting the same logic signaling level definition. The digital logic interface circuit generates a threshold level from the logic swing amplitude thus determined, and compares digital logic input signals against the threshold level in order to discriminate different logic levels in the digital logic input signals. The comparison result is provided as digital interface output signals adopting a predetermined logic signaling level definition for use by subsequent system sections. Examples of such representative signals are the digital input logic signals themselves, clock signals or line encoded signals. Other examples can be mode control signals or NRZ signals.

Abstract: An I/O pad has a data transmitting circuit, a data monitoring control circuit, and a control selection circuit. The control selection circuit controls the data transmitting circuit at the control end, so as to enable or disable the transmission. When it is enabled, data in the data transmitting circuit are exported to a receiving circuit. When it is disabled, data exportation stops. The data monitoring circuit receives signals of the data transmission circuit and export signals to the control selection circuit. The data monitoring circuit judges whether the data transmission is under a stable condition. If it is not yet, an unstable signal is exported to a first input end of the control selection circuit. A second input end of the control selection circuit receives an output enabling signal. The output end of the control selection circuit is connected to the control end of the data transmitting circuit.

Abstract: Devices, methods, and networks that divide and proportionally distribute the drive strength of a clock buffer such that the output drive strength of the clock buffer is divided proportionally among a plurality of outputs from the clock buffer. In one embodiment, the present invention selectively couples adjacent parallel inverters present in a clock buffer to separate, internal distribution wires. The internal distribution wires are selectively coupled to one or more outputs by a connector wire to provide proportional, multiple outputs of the drive strength from the clock buffer to a clock network.

Abstract: A plurality of switching transistors is provided, each connects power supply terminals of a plurality of first circuit blocks to a power supply line, respectively. Among the first circuit blocks, the power supply terminals of the first circuit blocks operating at different timings are connected by an internal power supply line. A power supply control circuit simultaneously turns on the switching transistors connected to the internal power supply line, in response to operation(s) of at least any one of the first circuit blocks connected to the internal power supply line. Since the switching transistors can be shared among the first circuit blocks not operating simultaneously, operation speed of the first circuit blocks can be increased. Since a total size of the switching transistors can be made small, standby current can be decreased. Accordingly, a semiconductor integrated circuit operating at a high speed can be constituted without increasing the standby current.