Signal Level Or Switching Threshold Stabilization Patents (Class 326/31)
  • Patent number: 5418472
    Abstract: An apparatus for activating a dual-mode logic device is provided. The apparatus monitors a parameter of an input signal of the logic device. If the parameter falls outside of predetermined parametric ranges, the apparatus activates the logic device. In the preferred embodiment, the apparatus resides on the same semiconductor chip as the logic device, and monitors the voltage level of the input signal. If the voltage level falls outside the voltage range which represents a logical HIGH and the voltage range which represents a logical LOW, the apparatus activates the logic device.
    Type: Grant
    Filed: October 8, 1993
    Date of Patent: May 23, 1995
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Jerry O. Moench
  • Patent number: 5384498
    Abstract: A DC-coupled active pull-down ECL circuit ("LS-APD") has a pull-down drive that self-adjusts to load conditions. A current source sinks emitter current from first and second push-pull transistors. The input signal is coupled to the base of the first transistor, whose inverted collector signal is coupled to the base of a pull-up transistor whose emitter is the LS-APD output voltage node. (A non-inverting configuration provides the input signal to the base of the second transistor.) The pull-up transistor is coupled between the upper rail and the second transistor's collector load resistor. A pull-down transistor has its base coupled to the second transistor's collector, its collector coupled to the LS-APD output node, and its emitter coupled to a node receiving a regulated Vreg voltage. As load capacitance increases, the output voltage takes longer to drop sufficiently to nearly turn-off the pull-down transistor.
    Type: Grant
    Filed: April 30, 1993
    Date of Patent: January 24, 1995
    Assignee: Synergy Semiconductor
    Inventor: Thomas S. W. Wong