Abstract: A circuit having a core circuit for sinking a first current from a first internal power supply node; a power bouncing reduction circuit for receiving power from a second internal power supply node and sourcing a second current to the first internal power supply node in accordance with a comparison between a voltage at the first internal power supply node and a low-pass filtered voltage of the first internal power supply node; and a package for coupling the first internal power supply node and the second internal power supply node to a first external power supply node and a second external power supply node, respectively.

Abstract: A device includes a first transistor including a first gate electrode including first and second parallel electrode portions each extending in a first direction, and a first connecting electrode portion extending in a second direction approximately orthogonal to the first direction and connecting one ends of the first and second parallel electrode portions to each other, and first and second diffusion layers separated from each other by a channel region under the first gate electrode, a first output line connected to the first diffusion layer of the first transistor, and a second transistor comprising a second gate electrode extending in the second direction, and the second transistor being configured to use the second diffusion layer of the first transistor as one of two diffusion layers that are separated from each other by a channel region under the second gate electrode.

Abstract: A logic circuit is operated in a normal mode, with a supply voltage coupled to a supply rail of the logic circuit, and with a ground rail of the logic circuit grounded; It is determined that at least a portion of the logic circuit has experienced degradation due to bias temperature instability. Responsive to the determining, the logic circuit is operated in a power napping mode, with the supply voltage coupled to the ground rail of the circuit, with the supply rail of the circuit grounded, and with primary inputs of the circuit toggled between logical zero and logical one at low frequency. A logic circuit and corresponding design structures are also provided.

Abstract: A semiconductor device includes a power source selection circuit configured to turn on and off each of a plurality of power source switches. The power source selection circuit includes a power source selection unit configured to select one power source from among the plurality of power sources, and a feedback control unit configured to output an on command signal to turn on an electrical connection between the selected power source and the electric circuit to a power source switch to be connected to the selected power source. When the power source selection unit switches a power source to select to another, the feedback control unit feeds back a signal indicative of that an off command signal to turn off electrical connections between the plurality of power sources and the electric circuit has been output to all of the plurality of power source switches at a predetermined delay time.

Abstract: A semiconductor integrated circuit including: a circuit block having an internal voltage line; an annular rail line forming a closed annular line around the circuit block and supplied with one of a power supply voltage and a reference voltage; and a plurality of switch blocks arranged around the circuit block along the annular rail line, the plurality of switch blocks each including a voltage line segment forming a part of the annular rail line and a switch for controlling connection and disconnection between the voltage line segment and the internal voltage line.

Abstract: A programming element including a first transistor, a second transistor, and a capacitor between a logic circuit using a semiconductor element and a power supply is provided. In the programming element, a node where a drain electrode of the first transistor, a gate electrode of the second transistor, and one of electrodes of the capacitor are electrically connected to each other is formed. A potential can be supplied to each of a source electrode of the first transistor and the other of the electrodes of the capacitor. The power supply and the logic circuit are electrically connected to each other through a source electrode and a drain electrode of the second transistor. A connection state between the power supply and the logic circuit is controlled in accordance with the state of the second transistor.

Abstract: There is disclosed a switching arrangement comprising a switch with a plurality of individually controllable elementary switches connected in parallel between a first supply rail and a second supply rail. Each of the elementary switches can be in either one of a closed state and an open state independently of the others. A controller is adapted to dynamically control the closing or opening of the elementary switches, depending on the intensity of a current flowing through the switch. The number of elementary switches in the closed state is variable. The higher is the intensity of the current, the higher the number of elementary switches in the closed state. Thus, the impedance of the switch decreases when the current increases, and vice versa, and the voltage drop across the switch may be kept substantially constant.

Abstract: A termination impedance apparatus includes a variable pull-up resistor, a variable pull-down resistor, and a small-signal calibration circuit. The variable pull-up resistor is coupled between a first power supply voltage terminal and an output terminal. The variable pull-down resistor is coupled between the output terminal and a second power supply voltage terminal. The small-signal calibration circuit is for calibrating the variable pull-up resistor and the variable pull-down resistor to achieve a desired small-signal impedance.

Abstract: Apparatus and method for digital configuration of integrated circuits (ICs) are provided herein. In certain implementations, an IC includes an impedance sensing circuit and at least one pin used for digital configuration. The impedance sensing circuit can detect an impedance value of an external passive network electrically connected to the pin, and can digitally configure the IC based on the detected impedance. For example, an end-user can connect an external resistor of a particular resistance to the pin, and the impedance sensing circuit can sense or detect the external resistor's resistance and digitally configure the IC based on the detected resistance. Accordingly, an end-user can digitally configure the IC by connecting a passive external component corresponding to a desired digital configuration to the pin. In certain implementations, the IC includes multiple pins, and the digital configuration is based on the impedances detected on each of the pins.

Abstract: An impedance calibration circuit includes a first calibration voltage driver configured to operate in response to a first enable signal, compare a first calibration voltage signal with a first reference voltage signal, and drive the first calibration voltage signal, a first control code generator configured to operate in response to a second enable signal, compare the first calibration voltage signal with a first target voltage signal, and generate a first control code signal, and a first reference voltage generator configured to generate the first reference voltage signal in response to the first control code signal.

Abstract: The power consumption of a data sampling unit that selects a phase of a clock signal appropriate for sampling payload data is reduced at an input interface. A semiconductor integrated circuit includes an input interface and internal core circuits. The input interface includes a hysteresis circuit and a data sampling unit. The hysteresis circuit detects an input signal between first and second input thresholds as a sleep command. The data sampling unit selects an appropriate phase of a sampling clock signal in accordance with a synchronizing signal and samples payload data. When a sleep command is detected, a sleep signal is also supplied to the internal core circuits and the data sampling unit and they are controlled into a low-power consumption state.

Abstract: Provided is a logic circuit that can reduce the variation of a power supply voltage supplied thereto and a semiconductor integrated circuit including the logic circuit. The logic circuit includes a buffer unit, a voltage detection unit, and a switch unit. The buffer unit is connected between a first power supply or a voltage regulator and a second power supply to receive power supply, and outputs a signal having the same or inverted logic level as an input signal to an output terminal. The voltage detection unit detects a voltage at the output terminal and outputs a detection signal based on a detection result. The switch unit connects the buffer unit to the first power supply or the voltage regulator in accordance with the detection signal.

Abstract: The present invention discloses a CMOS differential logic circuit. The CMOS differential logic circuit includes a precharge differential logic unit, which is precharged to a source voltage in response to a clock signal and is configured to output voltage having an increased load-driving ability using a boosting voltage; a voltage-boosting unit, which is pulled down by a ground voltage in response to the clock signal and is configured to boost the pulled-down voltage using capacitive coupling and output the boosting voltage; and a switching unit, which is configured to couple the precharge differential logic unit and the voltage-boosting unit in response to the clock signal. The propagation delay of a signal from the input terminal to the output terminal of a circuit in a low-source-voltage environment can be reduced, and the operating speed of the circuit and energy efficiency of the operation thereof can be improved.

Abstract: An integrated circuit includes a plurality of power gating elements for controlling power applied to a first module which is in a powered off state, while a second module is in a powered on state, the second module being coupled to receive at least one signal from the first module when the first module is powered on. A a synchronization controller is provided for controlling the power gating elements to ramp up the power gated to the first module in order to power it up and, for a time while the power gated to the first module is below a first level, reducing the power gated to the second module, and for a time when the power gated to the first module is above the first level, increasing the power gated to the second module.

Abstract: An internal voltage generation circuit of a semiconductor apparatus includes: an active driver configured to output an internal voltage to an output node; a standby driver configured to output the internal voltage to the output node; and a voltage stabilizer connected to the output node. The voltage stabilizer starts a voltage stabilization operation of supplying or receiving electric charges to or from the output node when an active enable signal is disabled, and stops the voltage stabilization operation in a predetermined time after the active enable signal is enabled.

Abstract: An integrated circuit device comprising at least one calibration module for calibrating an impedance of at least one on-die interconnect line driver in order to adaptively match an impedance between the at least one on-die interconnect line driver and at least one on-die interconnect line conjugated thereto. The at least one calibration module is arranged to receive an indication of an output signal of the at least one line driver, compare the received indication of an output signal to a reference signal and detect a presence or an absence of a voltage overshoot of the output signal of the at least one line driver, and upon detection of a presence or an absence of a voltage overshoot of the output signal of the at least one line driver, cause the adjustment of power supply of the at least one line driver, to be decreased or increased correspondingly.

Abstract: A power distributor includes a large reservoir capacitor, a switch coupled between at least one power supply line and the large reservoir capacitor, and a controller configured to turn on or off the switch based on whether a circuit block connected to the power supply line is in operation or not.

Abstract: An internal voltage generation circuit of a semiconductor apparatus includes: an active driver configured to output an internal voltage to an output node; a standby driver configured to output the internal voltage to the output node; and a voltage stabilizer connected to the output node. The voltage stabilizer starts a voltage stabilization operation of supplying or receiving electric charges to or from the output node when an active enable signal is disabled, and stops the voltage stabilization operation in a predetermined time after to the active enable signal is enabled.

Abstract: A power gating circuit includes a first current switch, a second current switch, and a switching controller. The first current switch is connected between a power rail and a circuit block operated by an operating supply voltage, and provides a first current when turned on. The second current switch is connected between the power rail and circuit block, and provides a second current larger than the first current when turned on. The switching controller turns on first current switch when transitioned from a sleep mode to an active mode to change the operating supply voltage using the first current, generates a reference voltage based on the operating supply voltage that changes more slowly than the operating supply voltage, and turns on the second current switch based on the reference voltage to provide the second current to the circuit block.

Abstract: A high speed transmit driver is provided, along with methods to improve driver slew rate, decrease transmit jitter, improve termination accuracy, and decrease sensitivity to supply noise.

Abstract: A current steering logic buffer for generating an output clock signal, comprises: a buffer for receiving an input clock signal; a current source; switches controlled by the buffer, wherein the switches connect the current source to outputs for generating the output clock signal; and a feedback loop for controlling the current source as a function of the outputs and a reference voltage.

Abstract: A digital signal processing apparatus includes a digital circuit device having one or more elements configured to process digital data; a power supply configured to deliver a controllable operating voltage for the one or more elements; control logic configured to receive feedback signals from each of the one or more elements, the feedback signals indicative of a rate at which data is moving through each individual element; and the control logic configured to output a control signal to the power supply so as to cause the power supply to reduce the operating voltage for the one or more elements responsive to a decreasing workload detected therein, and to cause the power supply to increase the operating voltage for the one or more pipelines responsive to an increasing workload detected therein.

Abstract: A method and system are disclosed for calibrating a mid-voltage node in an integrated circuit including an input-output circuit having charge-recycling stacked voltage domains including at least first and second voltage domains. In one embodiment, the method comprises transmitting data through the input-output circuit, including transmitting a first portion of the data across the first voltage domain, and transmitting a second portion of the data across the second voltage domain. The method further comprises measuring a specified characteristic of the data transmitted through the input-output circuit; and based on the measured specified characteristic, adjusting a voltage of said mid-voltage node to a defined value. The voltage of the mid-voltage node may be adjusted to accomplish a number of objectives, for example, to achieve a desired trade-off between power and performance, or so that the two voltage domains have the same performance.

Abstract: Integrated circuits with sequential logic circuitry are provided. Sequential logic circuitry may include a chain of bypassable clocked storage elements coupled between a speed critical input terminal and a speed critical output terminal. Combinational logic circuits may be interposed between each adjacent pair of bypassable clocked storage elements in the chain. Dynamic voltage-frequency scaling (DVFS) control circuitry may provide an adjustable power supply voltage to the combinational logic circuits and may provide an adjustable clock signal to control the clocked storage elements. The DVFS control circuitry may be used to selectively enable at least some of the bypassable clocked storage elements while disabling other bypassable clocked storage elements so that the power supply voltage can be reduced while maintaining the same operating frequency. The power supply voltage and the frequency of the clock signal can be adjusted to provide the desired voltage-frequency tradeoff.

Abstract: A multi-path power switch scheme for functional block wakeup is disclosed. The scheme may be applied to functional blocks of an integrated circuit. When a power on procedure is initiated within a given functional block, a first group of power switches in a functional block may be powered on, while a second group of power switches is inhibited from powering on. After a predetermined time has elapsed, activation of the second group of power switches is initiated. After initiation of a power up procedure for a given functional block, the powering up of a second functional block to be powered on may initially be inhibited. After a predetermined time has elapsed, the powering on of the second functional block may be initiated. Overlap between times when the first and second groups of switches are active may depend on process, voltage, and temperature variations.

Abstract: A low voltage electronic module interface, with a low voltage interface for an electronic module receiving a constant current from a body control module, the interface including a reverse current protection circuit 152; and a switch 154 operably connected in series with the reverse current protection circuit 152, the switch 154 being responsive to a status signal 144. The reverse current protection circuit 152 and the switch 154 form a low voltage electronic module interface circuit 150 having a resistance; and the resistance is selected so voltage across the low voltage electronic module interface circuit 150 is less than 2.70 Volts when the switch 154 is closed and the constant current 124 flows through the low voltage electronic module interface circuit 150.

Abstract: A method for improving the performance of a digital circuit is provided in the illustrative embodiments. A real frequency of operation of the digital circuit is adjusted using a control loop in the digital circuit, the adjusting the real frequency being responsive to a change in an operating condition of the digital circuit. A measurement of a current drawn by the digital circuit is received from a voltage regulator supplying electrical power to the digital circuit. An over-current target current value is received. A voltage output from the voltage regulator to the digital circuit is adjusted such that the current drawn by the digital circuit does not exceed the over-current target current value.

Abstract: A memory tracking circuit controls discharge duration of a tracking bit-line based on (i) a signal received at the far end of a tracking row after a propagation delay and (ii) a signal applied to a transistor-based gate delay. The tracking circuit (i) extends the discharge duration when one or more of (a) the propagation delay and (b) the transistor-based gate delay is shorter than an uncontrolled discharge duration of the tracking bit-line, and (ii) does not extend the discharge duration otherwise. Based on the discharge duration, the tracking circuit activates a reset signal that resets a clock-pulse generator to switch the memory from an access operation to a recess state. Controlling the discharge duration, and consequently the reset signal, based on the propagation delay and the gate delay allows the clock-pulse generator to adjust access times to account for the memory array configuration and process, temperature, and voltage conditions.

Abstract: Disclosed is a system and method for providing Process-Voltage-Temperature (PVT) compensation for an Input/Output interface. An embodiment may connect an analog section and a digital section together to generate and measure an oscillation frequency (FOSC) used to look up a corresponding PVT control bit value in a look-up table. The analog section may be comprised of a voltage reduction system that reduces a bandgap reference voltage (VBGR) to half the supplied VBGR to a current mirror that supplies a PVT current (IPVT) to driver bit cells and a proportional mirrored control current (ICNTL) to a current controlled oscillator (CCO), which generates FOSC. The digital section may be used in combination with a frequency variable resistor and beta multiplier connected to the CCO to calibrate the capacitance of the CCO to tune out the process variation of the CCO capacitance and render FOSC to be linearly dependent on ICNTL.

Abstract: Described is an apparatus which comprises: a clamp coupled between a first power supply and a second power supply; and a circuit to operate with the second power supply, wherein the clamp is operable to adjust the second power supply when the apparatus enters a low power mode.

Abstract: The present invention discloses a CMOS differential logic circuit. The CMOS differential logic circuit includes a precharge differential logic unit, which is precharged to a source voltage in response to a clock signal and is configured to output voltage having an increased load-driving ability using a boosting voltage; a voltage-boosting unit, which is pulled down by a ground voltage in response to the clock signal and is configured to boost the pulled-down voltage using capacitive coupling and output the boosting voltage; and a switching unit, which is configured to couple the precharge differential logic unit and the voltage-boosting unit in response to the clock signal. The propagation delay of a signal from the input terminal to the output terminal of a circuit in a low-source-voltage environment can be reduced, and the operating speed of the circuit and energy efficiency of the operation thereof can be improved.

Abstract: An integrated circuit cell includes a set of circuit elements associated with a logic function along a logical path between an input and an output of the integrated circuit cell. The set of circuit elements includes a first subset of circuit elements having a first width size and a first threshold voltage and configured to operate within a cycle of time. The set of circuit elements also includes a second subset of circuit elements having a second width size and a second threshold voltage and configured to operate within the cycle of time. The first subset and second subset of circuit elements are configured to toggle data between the input and the output. The second threshold voltage is less than the first threshold voltage when the second width size is less than the first width size.

Abstract: There is provided a semiconductor package configured for externally controlled power management. Instead of integrating voltage regulation on-chip as done conventionally, power regulation is moved externally to the PCB level, providing numerous package advantages including size, simplicity, power efficiency, integration flexibility, and thermal dissipation. In particular, the use of flip-chip package configurations provides ready access to power supply bumps, which also allows the use of a universal receiving PCB and power supply through simple reconfiguring of voltage traces. As a result, flexible power management can be implemented, and portions of semiconductor packages may be managed for performance or thermal considerations, which may be of particular use for applications such as multi-core processors.

Abstract: A field programmable gate array (FPGA) includes a set of monitor circuits adapted to provide indications of process, voltage, and temperature for at least one circuit in the FPGA, and a controller adapted to derive a range of body-bias values for the at least one circuit from the indications of process, voltage, and temperature for the at least one circuit. The FPGA further includes a body-bias generator adapted to provide a body-bias signal to at least one transistor in the at least one circuit. The body-bias signal has a value within the range of body-bias values.

Abstract: To reduce power consumption of a semiconductor integrated circuit and to reduce delay of the operation in the semiconductor integrated circuit, a plurality of sequential circuits included in a storage circuit each include a transistor whose channel formation region is formed with an oxide semiconductor, and a capacitor whose one electrode is electrically connected to a node that is brought into a floating state when the transistor is turned off. By using an oxide semiconductor for the channel formation region of the transistor, the transistor with an extremely low off-state current (leakage current) can be realized. Thus, by turning off the transistor in a period during which power supply voltage is not supplied to the storage circuit, the potential in that period of the node to which one electrode of the capacitor is electrically connected can be kept constant or almost constant. Consequently, the above objects can be achieved.

Abstract: A low leakage logic circuit. The low leakage logic circuit includes a control circuit for logic circuit. The control circuit has a first transistor, a second transistor, a third transistor, a first diode, a first resistor and a second resistor. When the control circuit is ON, a first circuit path in the logic circuit is supplied with a first voltage from the source terminal of the third transistor. This voltage acts as a logic output and has the ability to source current at output terminal of the logic circuit. When the control circuit is OFF, a second circuit path in the logic circuit is supplied with a second voltage from the control circuit which is lower than the turn-on voltage of the second circuit path. This voltage is insufficient to turn ON the logic circuit, hence no current flows into the logic circuit.

Abstract: A power control circuit is connected between a power supply voltage and a logic circuit to switch power supplied to the logic circuit. The power control circuit includes a plurality of first power gating cells (PGCs) receiving an external mode change signal in parallel, at least one second PGC connected with one first PGC, at least one third PGC connected with the at least one second PGC, and at least one fourth PGC connected with the at least one third PGC. The second power gating cell, the third PGC, and/or the fourth PGC may include a plurality of gating cells. At least one of the second, third, and fourth pluralities has power gating cells connected in series. Each of the first through fourth PGCs switches power supplied in response to the mode change signal.

Abstract: Circuits, architectures, a system and methods for providing multiple power rails to a plurality of standard cells in a region of an integrated circuit. The circuitry generally includes a plurality of cells configured for connection to a first or second power rail, the first power rail providing a first voltage to at least one of the plurality of cells, and the second power rail providing a second voltage (which may be independent from the first voltage) to remaining cells in the plurality of cells. The method generally includes routing, in an IC layout, a first power rail providing a first voltage and a second power rail providing a second voltage, placing the plurality of cells, and selectively connecting first and second subsets of the plurality of cells to the first and second power rails, respectively. The present invention further advantageously minimizes regional layout design considerations and time delays.

Abstract: A system and method for calibrating bias in a data transmission system including a calibrated bias having impedance calibration for accommodating parameter variations in the data transmission system. A current mirror receives and balances bias currents between the calibrated bias and an output driver from the data transmission system. A digital compensation logic circuit is connected to the calibrated bias to adjust the calibrated bias for variations in parameters causing a current tail effect. A calibration logic circuit adjusts calibration due to variations in operational parameters, such that the tail current variations are minimized.

Abstract: Localized logic regions of a circuit include a local comparator electrically connected to a local resistive voltage circuit, to a local resistive ground circuit, and to a local register structure. The local comparator supplies a clock pulse to the local register structures when the local reference voltage is below a local voltage threshold. Activity in the local combinatorial logic structure causes the local reference voltage to drop below the local reference voltage independently of changes in the global reference voltage causing the comparator to output the clock pulse (with sufficient delay to allow the logic results to be stored in the registers only after setup times have been met in the local logic devices). This eliminates the need for a clock distribution tree, thereby saving power when there is no activity in the local combinatorial logic structure.

Abstract: A boundary scan circuit containing a freeze circuit and a transparency circuit that provides a capability to selectively place portions of a system logic in a sleep mode and thereby conserving power. There are two transparency circuit configurations, one that connects to an input pad cell and one that connects to an output pad cell. The circuitry in the transparency circuit is controlled in such a manner as to establish at the output of transparency circuit a known logic state to control leakage current resulting from the circuitry of the various pad cell configurations, which further conserves power during sleep mode.

Abstract: Disclosed is a high-swing voltage-mode transmitter or line driver. The transmitter can operate over a wide range of supply voltages. Increasing the available output swing merely involves increasing the supply voltage; the circuit adapts to maintain the desired output impedance. This allows for a tradeoff between output amplitude and power consumption. Another advantage of the proposed architecture is that it compensates for process, voltage, and temperature (PVT) and mismatch variations so as to keep rise and fall times matched. This feature reduces common-mode noise and hence EMI in systems in which the transmitter is used.

Abstract: A data transmission system comprises: a pair of transmission lines connecting a plurality of apparatuses; a bridge termination resistor connected between the transmission lines and having a resistance value matching a differential impedance of the transmission lines; a first switch connecting the bridge termination resistor to the transmission lines when being turned on, and disconnecting the bridge termination resistor from the transmission lines when being turned off; pull-up/down resistors connected between the transmission lines and a fixed voltage node, and having resistance values respectively matching characteristic impedances of the transmission lines, the fixed voltage node being a power supply or a ground; and second switches connecting the pull-up/down resistors between the transmission lines and the fixed voltage node when being turned on, and disconnecting the pull-up/down resistors from the transmission lines when being turned off.

Abstract: Disclosed is a circuit for adjusting a voltage supplied to an IC by a power supply circuit that produces a regulated-output voltage based on an output-control signal generated by a resistive voltage divider. The circuit includes a PVT detector configured to generate an interface control signal and an interface circuit (i) connected to PVT detector and to the resistive voltage divider and (ii) configured to adjust its resistance in response to the interface control signal. Adjusting the resistance of the interface circuit causes the voltage of the output-control signal to be adjusted, thus causing the power supply circuit to adjust the regulated output voltage.

Abstract: A circuit, an adjusting method, and use of a control loop for adjusting a data retention voltage and/or a leakage current of a CMOS circuit for a sleep mode, wherein the CMOS circuit is operated to control in a measuring mode, whereby in the measuring mode a leakage current exclusively flows through the CMOS circuit, the control loop in the measuring mode adjusts the data retention voltage and/or the leakage current, and the adjustments of the control loop for the sleep mode are stored.

Abstract: Systems and methods for reducing power distribution network noise are provided. For example, in one embodiment, a method includes determining delay variations of a user design via a delay sensor of an integrated circuit (IC). The delay variations are associated with voltage variations of the user design. Low frequency components of the voltage variations are filtered via control logic of the IC to obtain an AC response of the user design. An artificial current load is introduced to the IC to negate the AC response of the user design.

Abstract: Implementations to mitigating side effects of impedance transformation circuits are described. In particular, mitigation circuitry may be coupled to a high impedance circuit to minimize or eliminate non-linear output of the high impedance circuit in order to provide a well-defined bias voltage to the input of a buffer or amplifier device coupled to a capacitive sensor. Additionally, the mitigation circuitry may be coupled to the high impedance circuit to reduce or eliminate rectifying effects of the high impedance circuit. Accordingly, a bias voltage can be utilized to provide a stable operating point of the buffer or amplifier device via a high impedance circuit utilizing one or more impedance transformations.

Abstract: In one embodiment, an integrated circuit includes a self calibration unit configured to iterate a test on a logic circuit in the integrated circuit at respectively lower supply voltage magnitudes until the test fails. A lowest supply voltage magnitude at which the test passes is used to generate a requested supply voltage magnitude for the integrated circuit. In an embodiment, an integrated circuit includes a series connection of logic gates physically distributed over an area of the integrated circuit, and a measurement unit configured to launch a logical transition into the series and detect a corresponding transition at the output of the series. The amount of time between the launch and the detection is used to request a supply voltage magnitude for the integrated circuit.

Abstract: An apparatus includes a temperature sensor, a voltage regulator, and a field programmable gate array (FPGA). The temperature sensor and the voltage regulator are adapted, respectively, to provide a temperature signal, and to provide at least one output voltage. The FPGA includes at least one circuit adapted to receive the at least one output voltage of the voltage regulator, and a set of monitor circuits adapted to provide indications of process and temperature for the at least one circuit. The FPGA further includes a controller adapted to derive a body-bias signal and a voltage-level signal from the temperature signal, from the indications of process and temperature for the at least one circuit, and from the at least one output voltage of the voltage regulator. The controller is further adapted to provide the body-bias signal to at least one transistor in the at least one circuit, and to provide the voltage-level signal to the voltage regulator.

Abstract: In accordance with this invention the above and other problems are solved by a switching apparatus and method that uses a switching circuit having a pair of parallel solid-state diodes (e.g., PN diodes), one of which is connected to a transistor (e.g., power MOSFET or IGBT), to switch a capacitor in or out of a variable capacitance element of an impedance matching network. Charging a body capacitance of the transistor reverse biases one of the two diodes so as to isolate the transistor from the RF signal enabling a low-cost high capacitance transistor to be used. Multiple such switching circuits and capacitors are connected in parallel to provide variable impedance for the purpose of impedance matching.