Abstract: A tolerant input circuit that functions stably regardless of fabrication differences without having to adjust the threshold value of an input circuit. The tolerant input circuit includes a step-down device configured by an N-channel MOS transistor connected between an input pad and the input circuit. Voltage from a power supply is supplied to the gate of the N-channel MOS transistor in the step-down device to decrease the voltage of a high voltage signal provided to the input pad to the voltage of the power supply or lower. The signal with decreased voltage is provided to the input circuit. The tolerant input circuit includes a back gate voltage control circuit for increasing back gate voltage of the N-channel MOS transistor in the step-down device when the input pad is provided with a high voltage signal.

Abstract: A differential signaling system in which errors in signal transmission or reception, or both, can be detected to allow signal transmission to be interrupted and thereby prevent further erroneous signal transmission or reception.

Abstract: A semiconductor integrated circuit comprises logic cones having a structure in which substrates thereof are isolated from each other and substrate potentials can be controlled, and a potential switching section for supplying a substrate voltage from any of a first substrate bias supply potential and a second substrate bias supply potential to the logic cone. A signal output by a logic cone previous to a logic cone whose substrate potential is controlled is input as a trigger signal to the substrate supply potential switching section.

Abstract: An output driver includes a pre-pull up drive unit configured to perform a pre-pull up drive operation; a pre-pull down drive unit configured to perform a pre-pull down drive operation; a drive unit configured to perform a drive operation in response to outputs of the pre-pull up drive unit and the pre-pull down drive unit; and a compensation unit configured to sense changes of driving strengths of the pre-pull up drive unit and the pre-pull down drive unit to control the driving forces of the pre-pull up drive unit and the pre-pull down drive unit.

Abstract: A method for minimizing power consumption in a mobile device using cooperative adaptive voltage and threshold scaling is provided that includes receiving a supply voltage, a PMOS back bias voltage, and an NMOS back bias voltage. A clock signal is received. The clock signal is propagated through a timing comparison circuit. An output of the timing comparison circuit is examined. A determination is made regarding whether to request more power based on the output of the timing comparison circuit. A voltage control signal is sent to request more power when a determination is made to request more power based on the output of the timing comparison circuit.

Abstract: A method for extending lifetime reliability of CMOS circuitry includes coupling a first switching device between a logic high supply rail/logic low supply rail, and coupling a virtual supply rail to the CMOS circuitry. In a first mode of operation the first switching device supplies the full voltage value between the logic high supply rail and the logic low supply rail, and in a second mode of operation, the first switching device isolates the virtual supply rail from the logic high supply rail/logic low supply rail, thereby reducing the voltage supplied to the CMOS circuitry. A second switching device is coupled between the virtual supply rail and the logic low supply rail/logic high supply rail, wherein in a third mode of operation, the voltage on the virtual supply rail and the logic low supply rail/logic high supply rail is equalized.

Abstract: The present invention is directed to a circuit and a method that features selectively isolating a logic device from a source of power implementing a counter circuit to transmit a signal to a voltage control device to isolate a source of power from a logic device, coupled to a plurality of switching elements, with the voltage control device being coupled to allocate power to the logic device in response to activation of one of said plurality of switching elements. The logic device is typically a programmable logic device. In one embodiment, the voltage control device is a field effect transistor. In another embodiment the voltage control device is a voltage regulator.

Abstract: A memory system includes a first memory unit, a transmission bus having an impedance, and a memory controller having a first on-die termination circuit, coupled to the first memory unit through the transmission bus. The first on-die termination circuit matches the impedance of the transmission bus in response to the memory controller writing data to the first memory unit.

Abstract: A method for extending lifetime reliability of CMOS circuitry includes configuring a logic high supply rail, a logic low supply rail, and a virtual supply rail. In an intense recovery mode of operation, a first switching device is rendered nonconductive to isolate the virtual supply rail from the one of the logic high supply rail and the logic low supply rail, and the second switching device is rendered conductive so as to equalize the voltage on the virtual supply rail and the other of the logic high supply rail and the logic low supply rail. At least one device within the circuitry provides one of the logic high voltage and the logic low voltage to a gate terminal of an FET within the circuitry, with a source terminal of the FET coupled to the virtual supply rail, such that the FET is subjected to a reverse bias condition.

Abstract: A data-processing arrangement (3) comprises a data-handling circuit (4) and a supply-current circuit (8) whose dynamic behavior is inherently chaotic in the sense of Lyapunov. The data-processing arrangement is arranged so that a power supply current (io) consumed by the data-handling circuit flows through the supply-current circuit.

Abstract: An apparatus includes a transmitter, receiver or transceiver to couple to a communication link. An input receives one or more signals for a desired power level of the transmitter, receiver or transceiver. A power supply provides power to the transmitter, receiver or transceiver depending on at least the one or more signals.

Abstract: A power gated semiconductor integrated circuit comprises: (1) logic circuit to be power gated, said logic circuit having a virtual ground rail; (2) footer device disposed between said virtual ground rail and a ground rail for reducing power consumption of said logic circuit; and (3) virtual rail voltage clamp disposed electrically in parallel with said footer device for limiting the voltage at the virtual ground rail, the virtual rail voltage clamp comprising at least one NFET. A total of Nf NFETs are connected to the virtual ground rail of the integrated circuit for use as both virtual rail voltage clamps and footer devices. A quantity of Nmax-VC NFETs are scanned and perform the function of voltage clamps and the remaining (Nf?Nmax-VC) NFETs perform power gating. Manufacturing variability immunity and tuning of the variability immunity is achieved by adjusting the quantity Nmax-VC based upon testing of the manufactured integrated circuit.

Abstract: A voltage supply control circuit is arranged between a true ground voltage and a pseudo ground line. In an active mode, first and second control signals are at the “H” and “L” levels, respectively. In response to this, a first switch is turned on so that a first node is electrically coupled to a power supply voltage, and attains the “H” level. Further, a second switch is turned on to couple electrically the ground voltage to a second node. In a standby mode, the first and second control signals are at the “L” and “H” levels, respectively. In response to this, a third switch is turned on to couple electrically the first and second nodes together. Since the power supply voltage was electrically coupled to the first node according to the turn-on of the first switch in the active mode, the path of the control signal including the first node to the switch has accumulated charged charges.

Abstract: A switching power-supply circuit generates a predetermined output voltage by controlling a first switching transistor connected to a power supply and a second switching transistor connected between the first switching transistor and the ground. The switching power supply circuit includes a first driver, a second driver, a soft-start voltage generator and an error amplifier. The first driver drives the first switching transistor. The second driver drives the second switching transistor. The soft-start voltage generator generates a soft-start voltage that increases gradually after the time of start. The error amplifier amplifies an error voltage between a feedback voltage based on the predetermined output voltage and the soft-start voltage, and controls the first and second drivers in accordance with an amplified error voltage.

Abstract: A semiconductor integrated circuit including on the same semiconductor substrate: a first circuit block including a switching transistor which is off when the first circuit block is inactive and on when the first circuit block is active, the first circuit block including internal circuits adapted to provide predetermined functions, the internal circuits being connected to a first power line maintained at a low-level source voltage; a second circuit block including internal circuits adapted to provide predetermined functions, the internal circuits being connected to a second power line maintained at a low-level source voltage; a power line switch section connected between the first and second power lines; and a control circuit adapted to control the power line switch section so that the first and second power lines are connected together at a later timing or gradually over a longer period of time than the switching transistor turns on.

Abstract: A buffer circuit capable of switching between input mode and output mode includes a first transistor for outputting a prescribed voltage to an input/output terminal depending on a conductive state during the output mode of the buffer circuit, a pre-driver for controlling the conductive state of the first transistor during the output mode of the buffer circuit, and a power supply circuit for providing a first power supply to the pre-driver during the output mode of the buffer circuit and providing or blocking the first power supply to the pre-driver in accordance with an input voltage to the input/output terminal during the input mode of the buffer circuit.

Abstract: Consistent with an example embodiment, there is a method is for powering an integrated circuit. An integrated circuit comprises a chip within a package assembly, the chip includes a plurality of logic circuits each having at least one power input which should not receive a power voltage exceeding a predetermined maximum operating voltage. The method comprises measuring a power voltage supplied to the integrated circuit directly within the chip at the power input of at least one logic circuit. The power voltage is regulated such that the voltage supplied to the power input of at least one logic circuit of the chip is equal to the predetermined maximum operating voltage of this logic circuit.

Abstract: A method of reducing power consumption while maintaining performance characteristics and avoiding costly over-design of a high-speed communication link embedded in an SOC is provided. The method includes synthesizing the communication link at a reduced voltage to determine and isolate circuitry that is supply-voltage-critical from circuitry that is non-supply-voltage-critical. The supply-voltage-critical circuitry contains components that may not operate at the reduced voltage without degrading the performance characteristics of the communication link. A non-reduced voltage is used to drive the supply-voltage-critical circuitry while the reduced voltage is used to drive the non-supply-voltage-critical circuitry. The reduced voltage is generated using a voltage regulator embedded in the communication link.

Abstract: A down converter includes an interface section, which connects the down converter to switches and respective driver circuits, wherein the driver circuits and the switches are combined on an integrated circuit. The driver circuits include a high-side driver circuit, and a low-side driver circuit. The integration of the driver circuits with the switches reduces parasitic inductance, particularly in power applications.

Abstract: A voltage supply control circuit is arranged between a true ground voltage and a pseudo ground line. In an active mode, first and second control signals are at the “H” and “L” levels, respectively. In response to this, a first switch is turned on so that a first node is electrically coupled to a power supply voltage, and attains the “H” level. Further, a second switch is turned on to couple electrically the ground voltage to a second node. In a standby mode, the first and second control signals are at the “L” and “H” levels, respectively. In response to this, a third switch is turned on to couple electrically the first and second nodes together. Since the power supply voltage was electrically coupled to the first node according to the turn-on of the first switch in the active mode, the path of the control signal including the first node to the switch has accumulated charged charges.

Abstract: Systems and methods for Current Management of Digital Logic Devices is provided. In one embodiment, a method of current management for a digital logic circuit is provided. The method comprises drawing power to drive a digital logic integrated circuit; performing one or more switching operations with the digital logic integrated circuit; learning at least one bypass current setpoint based on a voltage powering the digital logic integrated circuit while performing the one or more switching operations.

Abstract: In one embodiment, NMOS transistors have their source coupled to a common source node such that the NMOS transistors conduct a leakage current if the common source node is grounded. To reduce this leakage current, the common source node is raised in potential. Similarly, PMOS transistors have their source coupled to a common source node such that the PMOS transistors conduct a leakage current if the common source node is charged to a power supply voltage VDD. To reduce this leakage current, the common source node is lowered in potential.

Abstract: Semiconductor circuit capable of selecting a corresponding adjusting parameter to adjust the received signal according to different voltages and frequencies. A voltage detector detects a voltage level of an external power voltage to generate a voltage detection signal, a frequency detector detects frequency of a main clock to generate a frequency detection signal, and a signal adjustment unit receives a first signal and selects one of a plurality of different adjusting parameters to adjust the first signal according to the voltage detection signal and the frequency detection signal.

Abstract: The transition time of an output is sometimes changed by a certain supply voltage connected to an output terminal of an output circuit. An output circuit to address this problem includes: a level detection circuit which detects a pull-up supply voltage applied to an output terminal OUT; and an open drain buffer circuit which can switch its driving ability on the basis of the detection result of the level detection circuit. Even if the output circuit is connected to a circuit whose supply voltage is different, it is made possible to produce an output while stabilizing the transition time of the output.

Abstract: A power gated semiconductor integrated circuit comprises: (1) logic circuit to be power gated, said logic circuit having a virtual ground rail; (2) footer device disposed between said virtual ground rail and a ground rail for reducing power consumption of said logic circuit; and (3) virtual rail voltage clamp disposed electrically in parallel with said footer device for limiting the voltage at the virtual ground rail, the virtual rail voltage clamp comprising at least one NFET. A total of Nf NFETs are connected to the virtual ground rail of the integrated circuit for use as both virtual rail voltage clamps and footer devices. A quantity of Nmax-VC NFETs are scanned and perform the function of voltage clamps and the remaining (Nf-Nmax-VC) NFETs perform power gating. Manufacturing variability immunity and tuning of the variability immunity is achieved by adjusting the quantity Nmax-VC based upon testing of the manufactured integrated circuit.

Abstract: A method and system for minimizing sub-threshold leakage in a logic block is disclosed. An NDR isolation device is coupled between the logic block and ground to form a virtual ground node. To put the logic block into sleep mode, the virtual ground control device raises the voltage at the virtual ground node above an isolation voltage, which causes NDR isolation device isolates the virtual ground node from ground. The virtual ground control device can then raise the voltage at the virtual ground node to the positive supply voltage to eliminate sub-threshold leakage currents the logic block. Alternatively, the virtual ground control device can raise the voltage at the virtual ground node to the positive supply voltage minus a retention voltage so that storage elements in the logic block can retain state information while still greatly reducing sub-threshold leakage current.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for time-multiplexed dynamic on-die termination. In an embodiment, an integrated circuit receives, during a first clock, an on-die termination (ODT) activation signal at its ODT pin. The integrated circuit also receives, during a second clock, an ODT value selection signal on its ODT pin. In an embodiment, the integrated circuit prevents a reset of the state of the ODT activation signal for a predetermined period of time to enable the multiplexing of signals on the ODT pin. Other embodiments are described and claimed.

Abstract: A flip-flop which eliminates a reset wiring to prevent complication of a wiring in an LSI or to increase the number of channels used for a signal wiring, an integrated circuit using the same, and a flip-flop resetting method, are provided. The flip-flop performing a reset operation by detecting a change in a power supply voltage includes a state retaining node that stores a HIGH level voltage or a LOW level voltage, and a reset signal generation circuit that detects a change in a power supply voltage exceeding a predetermined value to generate a reset signal for resetting a data storing state of the state retaining node.

Abstract: A semiconductor integrated circuit device has a combinational logic circuit including one or plural logic cells connected in series.

Abstract: An interface of the present invention includes a first inverter circuit that inverts a logic level of an input signal given to an external input terminal and outputs the inverted logic level, a second inverter circuit that outputs a potential in which a logic level of an output signal of the first inverter circuit is inverted, that is, a potential higher or lower than a logic of an input signal applied to the first inverter circuit by the amount of a predetermined potential, and a feedback path that positive-feedbacks an output signal of the second inverter circuit to the external input terminal. The interface circuit of the invention positive-feedbacks a potential of the output signal of the second inverter circuit and shifts the potential of the external input terminal in a floating state to an H or L level potential.

Abstract: An apparatus for extending lifetime reliability of CMOS circuitry includes a logic high supply rail, a logic low supply rail, and a virtual supply rail. In an intense recovery mode of operation, a first switching device is rendered nonconductive so as to isolate the virtual supply rail from the one of the logic high supply rail and the logic low supply rail, and the second switching device is rendered conductive so as to equalize the voltage on the virtual supply rail and the other of the logic high supply rail and the logic low supply rail. At least one device within the circuitry provides one of the logic high voltage and the logic low voltage to a gate terminal of an FET within the circuitry, with a source terminal of the FET coupled to the virtual supply rail, such that the FET is subjected to a reverse bias condition.

Abstract: An apparatus for extending lifetime reliability of CMOS circuitry includes a first switching device between a logic high supply rail/logic low supply rail, and a virtual supply rail coupled to the CMOS circuitry. In a first mode of operation the first switching device supplies the full voltage value between the logic high supply rail and the logic low supply rail, and in a second mode of operation, the first switching device isolates the virtual supply rail from the logic high supply rail/logic low supply rail, thereby reducing the voltage supplied to the CMOS circuitry. A second switching device coupled between the virtual supply rail and the logic low supply rail/logic high supply rail, in a third mode of operation, equalizes the voltage on the virtual supply rail and the logic low supply rail/logic high supply rail.

Abstract: A variable threshold voltage keeper circuit technique is proposed for simultaneous power reduction and speed enhancement of domino logic circuits. The threshold voltage of the keeper transistor is dynamically modified during circuit operation to reduce the contention current without sacrificing noise immunity. The threshold voltage of the keeper transistor is controlled by a body bias generator which switches between two voltages in accordance with the clock signal.

Abstract: A semiconductor integrated circuit for matching the resistance of a variable resistor, which is used as a terminating resistor or a reference of said terminating resistor, to the characteristic impedance of a transmission line, has a terminating resistor adjusting circuit that has a current circuit connected to a power supply, said variable resistor that is connected between said current circuit and the ground and receives a main current output from said current circuit, a comparator circuit that compares the potential of the variable resistor with a first reference potential and outputs a signal, and a control circuit that controls the resistance of said variable resistor based on the output signal of said comparator circuit; and an additional current adjusting circuit that is connected between said power supply and said variable resistor and outputs an additional current to said variable resistor according to an external signal determined by the resistance of an external parasitic resistor between said term

Abstract: Methods of compensating for power supply variations in an integrated circuit. During operation of the IC die, a power supply voltage level is monitored. When the power supply voltage level drops below a specified level, a performance compensation circuit in the IC is enabled, bringing a first delay (e.g., the rising delay) for a compensated circuit in the IC more closely into alignment with a second delay (e.g., a falling delay) for the circuit. When the power supply voltage level exceeds the specified level, the performance compensation circuit is disabled. When the IC is a programmable IC, for example, the compensated circuit can be a programmable interconnect multiplexer of the programmable IC. In these embodiments, the power supply voltage level for the pass transistors in the interconnect multiplexer can be monitored and compensated for as described above.

Abstract: An SOI structure semiconductor integrated circuit is disclosed that reduces the number of power supply wires setting substrate potential of a semiconductor element and reduces power consumption. With an SOI structure semiconductor integrated circuit, a first circuit block 51 does not include a critical path and a second circuit block 61 does include a critical path. First power supply wiring 28 supplies a first power supply and second power supply wiring 29 supplies a second power supply of a high-voltage compared to the first power supply. A wiring section 71 (P-channel first substrate power supply wiring and P-channel first power supply wiring) supplies the first power supply as a substrate power supply for P-channel elements of the first circuit block 51 and a source power supply.

Abstract: An input signal provided to an input terminal is terminated by coupling the input terminal to a ground voltage through a pull down transistor if the input signal at the input terminal is at a “high” level and coupling the input terminal to a power voltage through a pull up transistor if the input signal at the input terminal is at a “low” level. Termination circuits are provided including on die termination circuits.

Abstract: An integrated circuit device includes a programmable logic block, a monitoring input, a condition-sensing circuit coupled to the monitoring input and configured to generate a condition-sensed signal at an output in response to sensing a condition at the monitoring input, a first digital input, a first digital output, and a gating circuit configured in the programmable logic block and coupled between the first digital input and the first digital output. The gating circuit has a gating input coupled to the condition-sensing circuit and generates an output. The output is related to an input state of the first digital input in the absence of the condition-sensed signal and assumes an override state in the presence of the condition-sensed signal.

Abstract: A system including a single ended switching topology for high-speed bidirectional signaling includes a device coupled to a plurality of bidirectional signal paths. The device includes a plurality of voltage mode driver circuits, each coupled to a respective signal path. Each of the driver circuits may source a voltage when transmitting data and terminate a respective signal path to a ground reference when receiving data. The device also includes a shunt regulator circuit coupled to a voltage supply of the device. The shunt regulator may provide a current shunt from the voltage source to the ground reference in response to detecting a transition on the voltage supply in which the voltage increases above an average DC voltage.

Abstract: A logic gate is constructed of an insulated gate field effect transistor (MIS transistor) having a thin gate insulation film. An operation power supply line to the logic gate is provided with an MIS transistor having a thick gate insulation film for switching the supply and stop of an operation power source voltage. A voltage of the gate of the power source switching transistor is made changing in an amplitude greater than an amplitude of an input and an output signal to the logic gate. Current consumption in a semiconductor device configured of MIS transistor of a thin gate insulation film can be reduced and an power source voltage thereof can be stabilized.

Abstract: Integrated circuit devices are provided that include power detection circuits that indicate whether power supplies have reached functional voltage levels. The power detection circuits include latches coupled to power supplies that can detect whether all the power supplies have reached functional voltage levels, logic circuits to provide appropriate output signals, and well bias circuits that supply current to the power detection circuits. Well bias circuits provide current from first power supplies to reach functional voltage levels so that indication may be provided from the power detection circuit without requiring functional voltage levels of all power supplies. Outputs from power detection circuits can be combined with control signals, for various applications. Applications include holding an integrated circuit device in reset until power supplies have reached functional voltage levels.

Abstract: A communication system having first and second states for use with a shared transmission line composed of at least two conductors and composed of first and second transmission line segments connected to each other at a single connection point. In the first state, a termination is coupled to the single connection point and is operative to at least attenuate a signal propagated between the first and second segments. In the second state, a driver is coupled to the connection point and is operative to conduct a signal over the first and second segments.

Abstract: Provided is a circuit for compensating for the declination of balanced impedance elements and a frequency mixer. The compensation circuit compensates for a difference between impedance measured at first and second impedance elements, and comprises first and second impedance circuits. The first impedance circuit transforms a first impedance value into a fine impedance value having 2n steps in response to n lower bits of a control signal having k bits. The second impedance circuit transforms a second impedance value into a coarse impedance value having 2m steps in response to m upper bits of the control signal. The first and second impedance values are measured at the first and second impedance elements, respectively, and k is equal to m plus n. The impedance difference between the impedance elements is linearly regulated.

Abstract: A diode circuit includes a differential circuit having a first MOS transistor whose source is connected to a first input terminal, a second MOS transistor whose source is connected to a second input terminal and gate and drain are connected to a gate of the first MOS transistor, and a first resistive load connected to a drain of the first MOS transistor, and a third MOS transistor whose conductive state is controlled according to an output of the differential circuit.

Abstract: A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.

Abstract: A semiconductor integrated circuit includes a CMOS controlled inverter consisting of series-connected PMOS and NMOS transistors. The source of the NMOS transistor is coupled to a ground line through an additional NMOS transistor for power gating of voltage VSS. The source of the PMOS transistor can be coupled to a power supply line through an additional PMOS transistor for power gating of voltage VDD. The inverter receives an input signal IN and its complementary version that has transitioned earlier than the input signal. In response to the input signal, the inverter produces an output signal. A NAND gate that receives the output signal and the complementary input signal controls the power gating NMOS transistor. A NOR gate that receives the output signal and the complementary input signal controls the power gating PMOS transistor.

Abstract: In general, this disclosure is directed to circuitry for implementation of headswitches and footswitches in an ASIC for power management. The disclosed circuitry supports not only effective power management, but also efficient use of ASIC area, reduced complexity, and the use of electronic design automation (EDA) tools. In this manner, the disclosed circuitry can support enhanced performance and simplified ASIC design. In some cases, headswitch or footswitch circuitry may be implemented as a switch pad ring that extends around a hard macro forming part of an ASIC core. In other cases, headswitch or footswitch circuitry can be distributed within an ASIC core by embedding distributed headswitch or footswitch components under metal layer power routing coupled to standard cell rows.

Abstract: An integrated circuit having two or more power domains that include load circuits in different portions of the integrated circuit is disclosed. In order to conserve power, the circuits in one of the power domains are shut down by disconnecting the power source serving that domain. The load circuits in each power domain are buffered from the load circuits in other power domains by buffer cells. The buffer cells reduce leakage currents in the power domain that is shut down, by restricting data signals from the “live” power domain from reaching the shut-down power domain, and further by providing predetermined voltage signals to the load circuits in the shut-down power domain that are selected to minimize leakage currents in the inactive load circuits. The invention further provides a corresponding method for reducing power consumption in an integrated circuit having at least two power domains separated by a buffer cell.

Abstract: Virtual power-gated cells (VPC) are configured with control circuitry for buffering control signals and a power-gated block (PGB) comprising two or more NFETs for virtual ground rail nodes and PFETs for virtual positive rail nodes. Each VPC has a control voltage input, a control voltage output, a node coupled to a power supply voltage potential, and a virtual power-gated node that is coupled and decoupled from the power supply potential in response to logic states on the control input. The control signals are buffered by non-power-gated inverters before being applied to the input of a PGB. VPCs may propagate a control signal that is in phase with or inverted from a corresponding control signal at the control input. VPCs may be cascaded to create virtual power rails in chains and power grids. The control signals are latched at the cell boundaries or latched in response to a clock signal.

Abstract: In one embodiment, NMOS transistors have their source coupled to a common source node such that the NMOS transistors conduct a leakage current if the common source node is grounded. To reduce this leakage current, the common source node is raised in potential. Similarly, PMOS transistors have their source coupled to a common source node such that the PMOS transistors conduct a leakage current if the common source node is charged to a power supply voltage VDD. To reduce this leakage current, the common source node is lowered in potential.