Having Details Of Setting Or Programming Of Interconnections Or Logic Functions Patents (Class 326/38)
  • Patent number: 10983948
    Abstract: A reconfigurable computing appliance includes a number of computing tiles. Each computing tile includes a reconfigurable processing element and a network fabric interface device configured to communicate over a network fabric. The reconfigurable processing element operates on data received from an I/O input interface and/or data received via the network fabric interface device.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: April 20, 2021
    Assignee: Raytheon Company
    Inventor: Russell E. Dube
  • Patent number: 10977057
    Abstract: An electronic apparatus and an operation method thereof are provided. The electronic apparatus includes a nonvolatile memory, a first integrated circuit and a second integrated circuit. The nonvolatile memory stores the first firmware code of the first integrated circuit and the second firmware code of the second integrated circuit. The first integrated circuit is coupled to a memory access interface of the nonvolatile memory to read the first firmware code and the second firmware code. The first integrated circuit has an emulation memory access interface to emulate an emulation memory. The second integrated circuit is coupled to the emulation memory access interface of the first integrated circuit. The second integrated circuit reads the second firmware code from the first integrated circuit via the emulation memory access interface.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: April 13, 2021
    Assignee: VIA LABS, INC.
    Inventors: Terrance Shiyang Shih, Chin-Sung Hsu
  • Patent number: 10970409
    Abstract: Circuits, methods, and apparatus for storing application data, keys, authorization codes, or other information in a volatile memory on an FPGA. A field programmable gate array (FPGA) can include multiple memory blocks and partition those blocks among multiple independent reconfigurable regions. Access to the memory blocks can then be restricted so that only authorized regions have access to particular memory partitions. In addition, each partition can store multiple message authentication codes (MACs) for further controlling access to data in each partition.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: April 6, 2021
    Assignee: Altera Corporation
    Inventor: Martin Langhammer
  • Patent number: 10948815
    Abstract: The present disclosure discloses a mask, which includes a first substrate and a second substrate. The mask further includes a polarity particle positioned between the first substrate and the second substrate. The polarity particle has a light absorption or light transmission effect. The first substrate includes a plurality of driving electrodes disposed toward the second substrate and arranged in an array. Each of the driving electrodes is configured to receive an electric signal and control the polarity particle to move to a designated driving electrode to form a pattern.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: March 16, 2021
    Assignees: Beijing BOE Optoelectronics Technology Co., Ltd., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yue Geng, Peizhi Cai, Fengchun Pang, Le Gu, Chuncheng Che
  • Patent number: 10942753
    Abstract: A data loading system includes a processing circuit, a nonvolatile memory, and a programmable logic device. The processing circuit and the programmable logic device are separately coupled to different data interfaces of the nonvolatile memory. The nonvolatile memory stores start code of the processing circuit and configuration data of the programmable logic device, and the processing circuit and the programmable logic device are configured to respectively obtain the start code and the configuration data from the nonvolatile memory at the same time under the action of a first synchronization clock. Hence, the system increases a speed and reliability of data loading and increases a start speed and reliability of a board.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: March 9, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventor: Yansong Li
  • Patent number: 10943652
    Abstract: An in-memory computing system for computing vector-matrix multiplications includes an array of resistive memory devices arranged in columns and rows, such that resistive memory devices in each row of the array are interconnected by a respective wordline and resistive memory devices in each column of the array are interconnected by a respective bitline. The in-memory computing system also includes an interface circuit electrically coupled to each bitline of the array of resistive memory devices and computes the vector-matrix multiplication between an input vector applied to a given set of wordlines and data values stored in the array. For each bitline, the interface circuit receives an output in response to the input being applied to the given wordline, compares the output to a threshold, and increments a count maintained for each bitline when the output exceeds the threshold. The count for a given bitline represents a dot-product.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: March 9, 2021
    Assignee: The Regents of the University of Michigan
    Inventors: Wei Lu, Mohammed A. Zidan
  • Patent number: 10936235
    Abstract: The present disclosure includes apparatuses and methods for data movement. An example apparatus comprises a memory device. The memory device includes an array of memory cells and sensing circuitry coupled to the array via a plurality of sense lines. The sensing circuitry includes a sense amplifier and a compute component coupled to a sense line and configured to implement operations. A controller in the memory device is configured to couple to the array and sensing circuitry. A shared I/O line in the memory device is configured to couple a source location to a destination location.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: March 2, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Glen E. Hush, David L. Pinney
  • Patent number: 10929331
    Abstract: Examples described herein generally relate to a layered boundary interconnect in an integrated circuit (IC) and methods for operating such IC. In an example, an IC includes a programmable logic region, a plurality of input/output circuits, a plurality of hard block circuits, and a programmable native transmission network. The programmable native transmission network is connected to and between the plurality of input/output circuits and the plurality of hard block circuits. The plurality of hard block circuits is connected to and between the programmable native transmission network and the programmable logic region.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: February 23, 2021
    Assignee: XILINX, INC.
    Inventor: Rafael C. Camarota
  • Patent number: 10897627
    Abstract: A partial decoder and event detection logic are deployed in a non-volatile memory system to offload processing from a host system while maintaining high video recording performance and backward compatibility with conventional host system logic.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: January 19, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventor: Ramanathan Muthiah
  • Patent number: 10891992
    Abstract: An SRAM architecture to optimize the performance of the SRAM. The local bit-lines are activated one at a time with control signals from a decoder. The global bit-lines are broken with repeaters to optimize performance. This guarantees optimal performance for the SRAM array across a wide range of supply voltages spanning from the nominal voltage of a process to a sub-threshold range.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: January 12, 2021
    Assignee: Synopsys, Inc.
    Inventors: Prashant Dubey, Jamil Kawa, Kritika Aditya
  • Patent number: 10884976
    Abstract: A parallel processing unit includes a plurality of main processing units and a decision processing unit. Each of the plurality of main processing units includes a main processing calculator for performing a calculation on one or more inputs, a main processing adder for adding an output of the main processing calculator and an output of a decision processing delayer, and a main processing comparator for making a comparison with an output of the main processing adder. The decision processing unit includes a decision processing calculator for adding outputs of the plurality of main processing calculators, a decision processing adder for adding an output of the decision processing calculator and the output of the decision processing delayer, the decision processing delayer for delaying an output of the decision processing adder, and a decision processing comparator for making a comparison with the output of the decision processing adder.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: January 5, 2021
    Assignee: MORUMI Co., Ltd.
    Inventor: Taehyoung Kim
  • Patent number: 10867090
    Abstract: A method for designing a system on a target device is disclosed. The system is synthesized from a register transfer level description. The system is placed on the target device. The system is routed on the target device. A configuration file is generated that reflects the synthesizing, placing, and routing of the system for programming the target device. A modification for the system is identified. The configuration file is modified to effectuate the modification for the system without changing the placing and routing of the system.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: December 15, 2020
    Assignee: Intel Corporation
    Inventors: Gregg William Baeckler, Martin Langhammer, Sergey Gribok, Scott J. Weber, Gregory Steinke
  • Patent number: 10868539
    Abstract: A field programmable gate array (FPGA) includes: a first logic block having a first lookup table; and a second logic block having a second lookup table, wherein the first logic block is coupled to the second logic block, in which the first logic block is configured to pass, upon a clock cycle of the FPGA, data about a lookup table configuration stored in the first lookup table to the second logic block.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: December 15, 2020
    Assignee: Google LLC
    Inventor: Jonathan Ross
  • Patent number: 10868538
    Abstract: A logic cell structure includes: a first portion, with a first height, arranged to be a first layout of a first semiconductor element; a second portion, with the first height, arranged to be a second layout of a second semiconductor element, wherein the first portion is separated from the second portion; and a third portion arranged to be a third layout of an interconnecting path used for coupling the first semiconductor element and the second semiconductor element.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shao-Huan Wang, Chun-Chen Chen, Sheng-Hsiung Chen, Kuo-Nan Yang
  • Patent number: 10854551
    Abstract: A semiconductor package includes a redistribution layer having a first surface and a second surface opposite to each other, the redistribution layer including a plurality of first redistribution pads on the first surface, a semiconductor chip on the second surface of the redistribution layer, an active surface of the semiconductor chip facing the redistribution layer, a plurality of conductive structures on the second surface of the redistribution layer, the plurality of conductive structures being spaced apart from the semiconductor chip, and a plurality of external connection terminals on and coupled to the conductive structures, the plurality of first redistribution pads have a pitch smaller than a pitch of the plurality of external connection terminals.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: December 1, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hae-Jung Yu, Kyung Suk Oh
  • Patent number: 10855284
    Abstract: A method of routing interconnects of a field programmable gate array including: a plurality of logic tiles, and a tile-to-tile interconnect network, having a plurality of tile-to-tile interconnects to interconnect logic tile networks of the logic tiles, the method comprises: routing a first plurality of tile-to-tile interconnects in a first plurality of logic tiles. After routing the first plurality of tile-to-tile interconnects, routing a second plurality of tile-to-tile interconnects in a second plurality of logic tiles. The start/end point of each tile-to-tile interconnect in the first plurality and the second plurality of tiles is independent of the start/end point of the other tile-to-tile interconnects in the first and second plurality, respectively.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: December 1, 2020
    Assignee: Flex Logix Technologies, Inc.
    Inventors: Yongning Liu, Fan Mo, Cheng C. Wang
  • Patent number: 10838389
    Abstract: Provided are embodiments including a system and method for operating a reconfigurable control architecture for programmable logic devices. Some embodiments include a storage medium that is coupled to a programmable logic device and a dispatch mechanism that is operably coupled to the programmable logic device. In embodiments, the dispatch mechanism is configured is receive an object, select one or more constructs of the programmable logic device based on the object, schedule one or more inputs and outputs for each of the selected constructs based on the object, and execute a system level operation indicated by the object based on the schedule.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: November 17, 2020
    Assignee: HAMILTON SUNSTRAND CORPORATION
    Inventors: Christopher Grant, John M. Maljanian, Michael T. Runde
  • Patent number: 10839880
    Abstract: A sense amplifier utilizes a phase transition material (PTM) in conjunction with CMOS circuits to provide a precise sensing threshold. The sense amplifier can be used in memory applications to sense states of stored bits with high accuracy and robustness. In one sense amplifier, a first diode-connected transistor has gate and drain nodes coupled to an input node of the sense amplifier, a second transistor has a gate node coupled to the gate node of the first diode-connected transistor, and the PTM is coupled to the source node of the second transistor. In another sense amplifier, a first transistor has a gate node coupled to an input node of the sense amplifier, a PTM is coupled to the source node of the first transistor, and an output stage including an inverter is coupled between a drain node of the first transistor and an output node of the sense amplifier.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: November 17, 2020
    Assignee: The Penn State Research Foundation
    Inventors: Sumeet Kumar Gupta, Ahmedullah Aziz, Nikhil Shukla, Suman Datta, Xueqing Li, Vijaykrishnan Narayanan
  • Patent number: 10825745
    Abstract: A multi-die integrated circuit with improved testability can include at least two dies that combined comprise an integrated circuit for a self-contained system, which includes logic and design-for-test features. The integrated circuit is split into at least two portions, where each portion is disposed on a corresponding one of the at least two dies. As part of the improved testability for both pre-bond testing of logic and post-bond testing of inter-die connections, at least one of the at least two dies further comprises a split-circuit-boundary scan chain. An automated design tool can be used to determine optimal ways for the integrated circuit for a self-contained system to be split into at least two portions for the corresponding at least two dies. In addition, a split-circuit-boundary scan chain option can be applied for each portion, via the automated design tool, to ensure boundary scans are available on timing paths.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: November 3, 2020
    Assignee: ARM LIMITED
    Inventors: Saurabh Pijuskumar Sinha, Xiaoqing Xu, Joel Thornton Irby, Mudit Bhargava
  • Patent number: 10824584
    Abstract: A device may include a processor system and an array of data processing engines (DPEs) communicatively coupled to the processor system. Each of the DPEs includes a core and a DPE interconnect. The processor system is configured to transmit configuration data to the array of DPEs, and each of the DPEs is independently configurable based on the configuration data received at the respective DPE via the DPE interconnect of the respective DPE. The array of DPEs enable, without modifying operation of a first kernel of a first subset of the DPEs of the array of DPEs, reconfiguration of a second subset of the DPEs of the array of DPEs.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: November 3, 2020
    Assignee: XILINX, INC.
    Inventors: Juan J. Noguera Serra, Sneha Bhalchandra Date, Jan Langer, Baris Ozgul, Goran H K Bilski
  • Patent number: 10810119
    Abstract: A process for wear-leveling in a memory subsystem where references to invalidated chunks and a write count for each of the invalidated chunks of a memory subsystem are received by a wear-leveling manager. The wear-leveling manager orders the received references to the invalidated chunks of the memory subsystem in a tracking structure based on the write count of each of the invalidated chunks, and provides a reference to at least one of the invalidated chunks based on the ordering from the tracking structure to a write scheduler to service a write request, wherein the memory subsystem is wear-leveled by biasing the order of the invalidated chunks to prioritize low write count chunks.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: October 20, 2020
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Justin Eno, Samuel E. Bradshaw
  • Patent number: 10804885
    Abstract: A standard cell layout for a data storage circuit includes a latch and an initialization circuit. Metallization levels over the standard cell layout support circuit interconnections. At least one metallization level is provided for metal programming of an initialization configuration of the data storage circuit. The at least one metallization level may have: a first wiring layout for interconnecting the initialization circuit to the latch for configuration programming of the data storage circuit as an initialization in reset device (assertion of an initialization signal causing the data storage circuit data output to be reset), or a second wiring layout for interconnecting the initialization circuit to the latch for configuration programming of the data storage circuit as an initialization in set device (assertion of the initialization signal causing the data storage circuit data output to be set).
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: October 13, 2020
    Assignee: STMicroelectronics SA
    Inventors: Sylvain Engels, Alain Aurand, Etienne Maurin
  • Patent number: 10797705
    Abstract: A circuit device includes first and second output signal lines from which first and second output signals constituting differential output signals are output, and first to n-th output drivers coupled to the first and second output signal lines. In a first mode, i number of output drivers of the first to n-th output drivers drive the first and second output signal lines based on first and second input signals constituting differential input signals. In a second mode, j number of output drivers of the first to n-th output drivers drive the first and second output signal lines based on the first and second input signals.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: October 6, 2020
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Fumikazu Komatsu, Minoru Kozaki
  • Patent number: 10778228
    Abstract: An integrated circuit including an FPGA, configurable to process data via a plurality of data processing operations, and an ASIC, electrically coupled to logic circuitry of the FPGA via switch interconnect network thereof. In one embodiment, the ASIC includes a plurality of circuit blocks, each circuit block configurable to process data via a data processing operation, and selection circuitry, coupled to the logic circuitry of the FPGA and the plurality of circuit blocks of the ASIC, configurable to connect one or more of the plurality of circuit blocks of the ASIC and the logic circuitry of the FPGA into a first circuit configuration to perform a first data processing operation, and in situ, connect one or more of the plurality of circuit blocks of the ASIC and the logic circuitry of the FPGA into a second circuit configuration to perform a second data processing operation.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: September 15, 2020
    Assignee: Flex Logix Technologies, Inc.
    Inventor: Valentin Ossman
  • Patent number: 10778225
    Abstract: An integrated circuit system includes: a storage element which stores in advance a plurality of pieces of circuit information and startup control circuit information used to configure a startup control logic circuit for selecting circuit information that has not failed in configuring a logic circuit; and an integrated circuit which, at the time of startup or when configuration of the logic circuit based on any of the plurality of pieces of circuit information has failed, configures the startup control logic circuit by reading the startup control circuit information from the storage element, causes the configured startup control logic circuit to select the circuit information that has not failed in configuring the logic circuit, reads the circuit information selected by the startup control logic circuit from the storage element, and configures the logic circuit according to the circuit information.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: September 15, 2020
    Assignee: NEC CORPORATION
    Inventor: Katsuhisa Ikeuchi
  • Patent number: 10778162
    Abstract: Systems and methods for sensing an analog signal through digital input/output (I/O) pins are provided. Aspects include an analog to digital (ADC) circuit configured to generate a digital signal based on observations of the analog signal obtained from an analog circuit, where the ADC circuit includes a difference amplifier, a comparator, a divideby2 counter and two AND gates. Aspects also include a controller including a pin configured to receive the digital signal. The controller is configured to count pulses within the digital signal and determine values corresponding to the analog signal based on the counted pulses.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: September 15, 2020
    Assignee: ROSEMOUNT AEROSPACE, INC.
    Inventors: Rajkumar Sengodan, Saravanan Munusamy
  • Patent number: 10768244
    Abstract: A power loss protection integrated circuit includes a storage capacitor terminal (STR), an autonomous capacitor health check circuit, and a capacitor fault terminal (CF). The capacitor health check circuit autonomously performs periodic capacitor check operations. In a check operation, current is sinked from the STR terminal for a predetermined time and in a predetermined way. If during this time the voltage on the STR terminal STR drops below a predetermined voltage, then a digital signal CF is asserted onto the CF terminal. Immediately following each capacitor check, a charging voltage is driven onto the STR terminal to recharge the external capacitors coupled to the STR terminal. In one example, the integrated circuit further includes a current switch circuit (eFuse) and a buck/boost controller. The capacitor health check circuit is only enabled during normal mode operation of the integrated circuit, and the check circuit disables boost operation during capacitor checks.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: September 8, 2020
    Assignee: Active-Semi, Inc.
    Inventors: John H. Carpenter, Jr., Brett E. Smith
  • Patent number: 10770398
    Abstract: A semiconductor device assembly that includes a second side of an interposer being connected to a first side of a substrate. A plurality of interconnects may be connected to a second side of the substrate. First and second semiconductor devices are connected directly to the first side of the interposer. The interposer is configured to enable the first semiconductor device and the second semiconductor device to communicate with each other through the interposer. The interposer may be a silicon interposer that includes complementary metal-oxide-semiconductor circuits. The first semiconductor device may be a processing unit and the second semiconductor device may be a memory device, which may be a high bandwidth memory device. A method of making a semiconductor device assembly includes attaching both a memory device and a processing unit directly to a first side of an interposer and connecting a second side of the interposer to a substrate.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: September 8, 2020
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Chan H. Yoo, Owen R. Fay
  • Patent number: 10768231
    Abstract: “Shoot-through” timing failures in a scan chain of a defective semiconductor integrated circuit corrupt test pattern data used to perform failure analysis. Methods and procedures are provided to detect “shoot-through” conditions, determine the number of shoot-through scan cells, and to determine the location of the shoot-through cells within a scan chain. Reset test pattern results can be analyzed to identify candidate locations of shoot-through cells and when combined with candidate cell locations from analysis of physical clock distribution trees and potential clock-skew issues, the exact location of all shoot-through cells can be determined. Methods are also provided to use shoot-through cell locations to identify the defective clock net containing the physical defect causing the clock skew conditions needed to produce shoot-through timing failures.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: September 8, 2020
    Assignee: TESEDA CORPORATION
    Inventor: Theodore Clifton Bernard
  • Patent number: 10763862
    Abstract: Examples described herein provide for a boundary logic interface (BLI) to a programmable logic region in an integrated circuit (IC), and methods for operating such IC. An example IC includes a programmable logic region and boundary logic interfaces. The programmable logic region includes columns of interconnect elements disposed between columns of logic elements. The boundary logic interfaces are at respective ends of and communicatively connected to the columns of interconnect elements. The boundary logic interfaces are outside of a boundary of the programmable logic region. A first boundary logic interface (BLI) of the boundary logic interfaces is configured to be communicatively connected to an exterior circuit. The first BLI includes an interface configured to communicate a signal between the exterior circuit and the programmable logic region.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: September 1, 2020
    Assignee: XILINX, INC.
    Inventors: Rafael C. Camarota, Ui S. Han, Weiguang Lu
  • Patent number: 10761503
    Abstract: A device programming system, and a method of operation thereof, includes: a field programmable gate array unit configured using a programming driver retrieved based on a device type of a first programmable device; and a second programmable device and the first programmable device configured simultaneously using a master image and the field programmable gate array unit.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: September 1, 2020
    Assignee: Data I/O Corporation
    Inventors: Andrew B. Caley, Derek P. Steffey
  • Patent number: 10754817
    Abstract: An information processing apparatus having a reconfigurable circuit capable of rewriting a logic circuit includes, a process determination circuit that determines which of a plurality of processes is to be executed, a standby buffer circuit that holds process data to be used in a process waiting for execution among processes determined by the process determination circuit, and a rewrite control circuit that rewrites the current logic circuit written in the reconfigurable circuit to a logic circuit that executes one of the plurality of processes waiting for execution using each of a plurality of process data held in the standby buffer circuit when the amount of process data held in the standby buffer circuit exceeds a first predetermined amount.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: August 25, 2020
    Assignee: FUJITSU LIMITED
    Inventor: Toshiyuki Ichiba
  • Patent number: 10754666
    Abstract: A device comprising: at least one partially reconfigurable FPGA; a Network-on-Chip (NoC) comprised in the FPGA; and at least one area on the at least one FPGA operable to house a hardware micro-service (HMS); wherein an HMS image may be loaded onto the area of the at least one FPGA via partial reconfiguration to form a new HMS, and the NoC is operable to forward information to and from the new HMS without the NoC being reloaded.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: August 25, 2020
    Assignee: Rad Data Communications Ltd.
    Inventors: Yzhak Sorani, Yaakov Stein
  • Patent number: 10755019
    Abstract: In accordance with a first aspect of the present disclosure, a method of designing an integrated circuit is conceived, comprising: placing integrated circuit cells that include supply pins in a plurality of predefined rows; determining blocked areas for supply pin extensions; extending the supply pins outside said blocked areas. A corresponding integrated circuit is also provided.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: August 25, 2020
    Assignee: NXP B.V.
    Inventors: Sven Trester, Claus Dieter Grzyb
  • Patent number: 10740435
    Abstract: Provided is a programmable logic integrated circuit wherein even if a failure occurs in any resistance-variable element, remedy would be possible and hence the improvement of reliability has been achieved. In a programmable logic integrated circuit comprising resistance-variable elements, when the states of the resistance-variable elements are to be changed according to externally inputted configuration information, a control means uses a reading means to read the states of the respective resistance-variable elements, and then uses a writing means to change only the states of resistance-changing elements that are different from a state indicated by the configuration information.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: August 11, 2020
    Assignee: NEC CORPORATION
    Inventors: Noboru Sakimura, Yukihide Tsuji, Ayuka Tada, Xu Bai, Makoto Miyamura, Ryusuke Nebashi
  • Patent number: 10735002
    Abstract: A programmable semiconductor device capable of being selectively programmed to perform one or more logic functions includes a first region, second region, first regional power control (“RPC”), and second-to-first power control connection. The first region, in one embodiment, contains first configurable logic blocks (“CLBs”) able to be selectively programmed to perform a first logic function. The second region includes a group of second CLBs configured to be selectively programmed to perform a second logic function. The first RPC port or inter-chip port which is coupled between the first and second regions facilitates dynamic power supply to the first region in response to the data in the second region. The second-to-first power control connection is used to allow the second region to facilitate and/or control power to the first region.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: August 4, 2020
    Assignee: Gowin Semiconductor Corporation
    Inventors: Jinghui Zhu, Jianhua Liu, Ning Song
  • Patent number: 10735020
    Abstract: A voltage detector circuit including a ladder selector that includes a first node, a second node and a selector node. The voltage detector circuit also includes a first resistive ladder that includes a first string of resistors coupled between a sensing input node and the first node of the ladder selector and a first set of transistors. An input node of each transistor in the first set of transistors is coupled to a respective intermediate node between two resistors in a subset of resistors in the first string of resistors and an output node of each transistor in the first set of transistors is coupled to a sensing output node. The voltage detector circuit also includes a second resistive ladder that includes a second string of resistors coupled between the sensing input node and the second node of the ladder selector and a second set of transistors.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: August 4, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Santhosh Kumar Gowdhaman, Divya Kaur
  • Patent number: 10725873
    Abstract: The present techniques generally relate to a method of monitoring for a fault event in a lockstep processing system having a plurality of cores configured to operate in lockstep, the method having: power gating, for a period of time, a subset of cores of the plurality of cores from a first power source and providing power to the subset of cores from a second power source for the period of time; processing, at each of the cores of the plurality of cores, one or more instructions; providing an output from each core of the plurality of cores to error detection circuitry to monitor for the fault event, the output from each core based on or in response to processing the one or more instructions during the period of time.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: July 28, 2020
    Assignee: Arm Limited
    Inventors: Milosch Meriac, Shidhartha Das
  • Patent number: 10720926
    Abstract: An example programmable device includes a configuration memory configured to store configuration data; a programmable logic having a configurable functionality based on the configuration data in the configuration memory; a signal conversion circuit; a digital processing circuit; an endpoint circuit coupled to the signal conversion circuit through the digital processing circuit; wherein the digital processing circuit includes a first one or more digital processing functions implemented as hardened circuits each having a predetermined functionality, and a second one or more processing functions implemented by the configurable functionality of the programmable logic.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: July 21, 2020
    Assignee: XILINX, INC.
    Inventors: John McGrath, Woon Wong, John O'Dwyer, Paul Newson, Brendan Farley
  • Patent number: 10719470
    Abstract: Techniques are disclosed for data manipulation. Data is obtained from a first switching element where the first switching element is controlled by a first circular buffer. Data is sent to a second switching element where the second switching element is controlled by a second circular buffer. Data is controlled by a third switching element that is controlled by a third circular buffer. The third switching element hierarchically controls the first switching element and the second switching element. Data is routed through a fourth switching element that is controlled by a fourth circular buffer. The circular buffers are statically scheduled. The obtaining data from a first switching element and the sending the data to a second switching element includes a direct memory access (DMA). The switching elements can operate as a master controller or as a slave device. The switching elements can comprise clusters within an asynchronous reconfigurable fabric.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: July 21, 2020
    Assignee: Wave Computing, Inc.
    Inventor: Christopher John Nicol
  • Patent number: 10719079
    Abstract: A hybrid of initial time consuming phase of a Single Directional Dijkstra's Algorithm is embodied on an unclocked CMOS logic chip using a parallelized approach with Asynchronous Digital Logic (ADL). The chip includes a a plurality of addressable configurable cells arranged as a multidimensional orthogonal array. The cell array only executes mathematical operations based on a communication between immediately adjacent cells.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: July 21, 2020
    Assignee: NOKOMIS, INC.
    Inventor: T. Eric Chornenky
  • Patent number: 10714207
    Abstract: A scannable-latch random access memory (SLRAM) is disclosed. The SLRAM includes two rows of memory cells. The SLRAM includes a functional data input, a scan data input, a first and second functional data outputs, a scan data output, and a scan enable. The functional data input is connected to a first memory cell in a first and second rows of memory cells. The scan data input is connected to the first memory cell in the first or second row of memory cells. The first and second functional data outputs are connected to a last memory cell in the first and second row of memory cells, respectively. The scan data output is connected to the last memory cell in the first or second row of memory cells. The scan enable allows data to be output from the scan data output or the first and second functional data outputs.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: July 14, 2020
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventors: David D Moser, Michael J. Frack, Jason F. Ross, Kevin Linger
  • Patent number: 10715148
    Abstract: Various implementations described herein are directed to an integrated circuit with logic circuitry having one or more components. The integrated circuit may include performance sensing circuitry that provides a performance sensing output associated with detecting variation of switching delays of the one or more components forming the logic circuitry. The integrated circuit may include transient sensing circuitry that receives the performance sensing output and provides a transient sensing output for determining stability of operating conditions of the performance sensing circuitry during one or more sampling periods. The transient sensing circuitry may use a finite state machine (FSM) to sense and classify changes in temporal behavior of the transient sensing output.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: July 14, 2020
    Assignee: Arm Limited
    Inventors: Rainer Herberholz, Amit Chhabra, Yannis Jallamion-Grive
  • Patent number: 10708036
    Abstract: An integrated circuit receiver is disclosed comprising a data receiving circuit responsive to a timing signal to detect a data signal and an edge receiving circuit responsive to the timing signal to detect a transition of the data signal. One of the data or edge receiving circuits comprises an integrating receiver circuit while the other of the data or edge sampling circuits comprises a sampling receiver circuit.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: July 7, 2020
    Assignee: Rambus Inc.
    Inventor: Jared L. Zerbe
  • Patent number: 10705995
    Abstract: The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a plurality of reconfigurable logic regions. Each reconfigurable region can include hardware that is configurable to implement an application logic design. The host logic can be used for separately encapsulating each of the reconfigurable logic regions. The host logic can include a plurality of data path functions where each data path function can include a layer for formatting data transfers between a host interface and the application logic of a corresponding reconfigurable logic region. The host interface can be configured to apportion bandwidth of the data transfers generated by the application logic of the respective reconfigurable logic regions.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: July 7, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Asif Khan, Islam Mohamed Hatem Abdulfattah Mohamed Atta, Robert Michael Johnson, Mark Bradley Davis, Christopher Joseph Pettey, Nafea Bshara, Erez Izenberg
  • Patent number: 10693469
    Abstract: An integrated circuit comprising a plurality of multiply-accumulator circuitry interconnected in a concatenation architecture. Each multiply-accumulator circuitry includes first and second MAC circuits and a load-store register. The first MAC circuit includes a multiplier to multiply first data by a first multiplier weight data and generate a first product data, and an accumulator to add first input data and the first product data to generate first sum data. The second MAC circuit includes a multiplier to multiply second data by a second multiplier weight data and generate a second product data, and an accumulator, coupled to the multiplier of the second MAC circuit and the accumulator of the first MAC circuit, to add the first sum data and the second product data to generate second sum data. The load-store register is coupled to the accumulator of the second MAC circuit to temporarily store the second sum data.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: June 23, 2020
    Assignee: Flex Logic Technologies, Inc.
    Inventor: Cheng C. Wang
  • Patent number: 10691856
    Abstract: A computer-implemented design flow can include, within a circuit design for an integrated circuit, determining a portion of the circuit design that is a candidate for implementation as a runtime customizable circuit and determining implementation options for the runtime customizable circuit. The design flow can also include generating, using computer hardware, a description of the circuit design using the runtime customizable circuit to implement the portion of the circuit design and generating, using the computer hardware, program code for an embedded processor coupled to an implementation of the runtime customizable circuit within the integrated circuit. The program code is usable by the embedded processor to parameterize the runtime customizable circuit to create a specific instance of the runtime customizable circuit.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: June 23, 2020
    Assignee: Xilinx, Inc.
    Inventors: Patrick Lysaght, Graham F. Schelle
  • Patent number: 10684983
    Abstract: Multi-level hierarchical routing matrices for pattern-recognition processors are provided. One such routing matrix may include one or more programmable and/or non-programmable connections in and between levels of the matrix. The connections may couple routing lines to feature cells, groups, rows, blocks, or any other arrangement of components of the pattern-recognition processor.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: June 16, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Harold B Noyes, David R. Brown
  • Patent number: 10680615
    Abstract: A circuit for configuring function blocks of an integrated circuit device is described. The circuit comprises a processing system; a peripheral interface bus coupled to the processing system; and a function block coupled to the peripheral interface bus, the function block having programming registers and a function block core; wherein the programming registers store data determining a functionality of the function block core and comprise programming control registers enabling a configuration of the function block core using the data. A method of configuring function blocks of an integrated circuit device is also described.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: June 9, 2020
    Assignee: XILINX, INC.
    Inventors: David P. Schultz, Ian A. Swarbrick, Nagendra Donepudi
  • Patent number: 10671429
    Abstract: An information processing apparatus includes: a reconfiguration device which can change a circuit configuration through a dynamic partial reconfiguration; and a controller which controls a circuit arrangement in the reconfiguration device, in which when a processing circuit related to a new task is arranged in the reconfiguration device, the controller determines a circuit assignment of a processing circuit related to an existing task in execution and the processing circuit related to the new task with respect to an area as a result of combining an area used for the processing circuit related to the existing task in execution and a space area, based on a predicted end time of the processing of the respective tasks, and arranges the processing circuits related to the respective tasks in the reconfiguration device in accordance with the determined circuit assignment.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: June 2, 2020
    Assignee: FUJITSU LIMITED
    Inventor: Kentaro Katayama