Abstract: A programmable integrated circuit may be provided with a memory interface for communicating with an external memory over a serial communications path. To accommodate a variety of different memory interface protocols while satisfying low-latency performance criteria, part of the memory interface may be formed from programmable logic and part of the memory interface may be formed from hardwired circuitry. The programmable logic of the memory interface may be used to implement packet formation logic that creates packets that include empty fields for sequence number information, acknowledgement information, and cyclic redundancy check information. The hardwired circuitry of the memory interface may be used to insert a sequence number, an acknowledgement, and cyclic redundancy check information into the empty fields.

Abstract: An integrated circuit may include a printed circuit board and multiple processor sockets on the printed circuit board. Each of the multiple processor sockets is operable to receive a microprocessor and a programmable device. When a microprocessor is placed in a processor socket, that microprocessor may communicate with memory dual in-line memory modules (DIMMs). When a programmable device is placed in a processor socket, that programmable device may first be configured using a configuration DIMM and may then communicate with memory DIMMs during normal operation. The configuration DIMM may include multiple options for configuring the programmable device and may also provide additional management functions specifically tailored to the programmable device.

Abstract: A multi-tenant environment is described with configurable hardware logic (e.g., a Field Programmable Gate Array (FPGA)) positioned on a host server computer. For communicating with the configurable hardware logic, an intermediate host integrated circuit (IC) is positioned between the configurable hardware logic and virtual machines executing on the host server computer. The host IC can include management functionality and mapping functionality to map requests between the configurable hardware logic and the virtual machines. Shared peripherals can be located either on the host IC or the configurable hardware logic. The host IC can apportion resources amongst the different configurable hardware logics to ensure that no one customer can over consume resources.

Abstract: A 3D-stacked memory device including: a base die including a plurality of switches to direct data flow and a plurality of arithmetic logic units (ALUs) to compute data; a plurality of memory dies stacked on the base die; and an interface to transfer signals to control the base die.

Abstract: A measurement transmitter for a multisensor system for process automation technology, wherein the measurement transmitter, for processing in- and output signals, has a processor, which is connected with an interface, to which a sensor is connected for transmission of data via a transmission line. In communication between the processor and the interface, or the sensor and the interface, different transmission rates of data occur. In order to be able to connect to the measurement transmitter a plurality of sensors working with different principles of operation, and, in spite of the plurality of sensors, largely avoid errors in the data transmission, at least two sensors are present, wherein a function module is present in the interface for each sensor and the function module for each sensor is connected with such sensor via a dedicated transmission line.

Abstract: An apparatus and method for efficient shutdown of adiabatic charge pumps. A power converter includes a charge pump, a controller, an output load and an inductor. According to one aspect, the power converter includes a switch which is connected across the inductor, where the controller is configured to sense a status of the charge pump and to correspondingly drive the switch element. According to another aspect, the charge pump includes an active discharge circuit and a current-sense circuit, where the current-sense circuit is configured to activate the active discharge circuit. According to yet another aspect, the power converter includes a cascade multiplier having a plurality of high side and low side switches, where a pair of high side and low side switches are enabled simultaneously, such that the pair of high side and low side switches act as an active discharge switch for the charge pump.

Abstract: It is hereby disclosed an apparatus for and a method of writing software objects into a rewritable nonvolatile memory of an electronic control unit of an internal combustion engine, wherein the method comprises: receiving an access request from a memory writing device, generating a seed code, transmitting the seed code to the memory writing device, generating a first key code on the basis of the seed code and a first identification code, generating a second key code on the basis of the seed code and a second identification code, receiving a reference key code from the memory writing device, comparing the reference key code with the first key code and/or with the second key code, and enabling the memory writing device to write software objects into the rewritable nonvolatile memory, if the reference key code corresponds to the first key code or to the second key code.

Abstract: A method, computer program product, and computer system for executing one of a reboot and a startup process. A write I/O may be received at a DRAM cache. Data may be written to at least two different NVMe devices. When the data of the write I/O is completely written to the at least two different NVMe devices, a response may be sent to a driver layer.

Abstract: Device(s) and method(s) related generally to a wafer or die stack are disclosed. In one such device, a die stack of two or more integrated circuit dies has associated therewith test circuits corresponding to each level of the die stack each with a set of pads. A test data-input path includes being from: a test data-in pad through a test circuit to a test data-out pad of each of the test circuits; and the test data-out pad to the test data-in pad between consecutive levels of the test circuits. Each of the set of pads includes the test data-in pad and the test data-out pad respectively thereof. A test data-output path is coupled to the test data-out pad of a level of the levels.

Abstract: A method for developing a method for compiling a quantum circuit on a quantum processor, comprising: a selection step: of a quantum circuit, of a quantum processor whereupon to compile the quantum circuit, of a set of quantum gates that can be executed on the selected quantum processor, of a metric, a meta-heuristic, a step of division of the selected quantum circuit into quantum sub-circuits, a first step of re-writing of the quantum sub-circuits comprising quantum gates that cannot be executed by the selected quantum processor to comprise only quantum gates that can be executed by the selected quantum processor, a second step of re-writing of the quantum sub-circuits, by the selected meta-heuristic, to obtain quantum sub-circuits comprising quantum gates that can be executed by the selected quantum processor, improving the selected metric, a step of regrouping of the quantum sub-circuits in a quantum circuit compilable by the selected quantum processor.

Abstract: The control system according to embodiments includes a switching element, a control unit controlling the conductive state of the switching element, and a first capacitor storing charge supplied to the control unit. The first capacitor and the control unit are connected with each other via the switching element.

Abstract: The present invention discloses a programmable logic device with on-chip user non-volatile memory, comprising: a programmable logic array, which is a user programmable logic array and comprises a SRAM array and a logic block array with an interface; the SRAM array is used to store configuration data to control the logic block array in real time, therefore, the logic block can be formed to perform the function a user desires; a non-volatile memory block, comprising one or more segments storing configuration data and one or more segments storing user data which is used during FPGA's normal operation after configuration; the non-volatile memory block has only one interface, and the non-volatile memory block connects to a programming controller through the interface; a programming controller, which can randomly access the non-volatile memory through a data bus, an address bus, and corresponding control signals.

Abstract: A reconfigurable computing appliance includes a number of computing tiles. Each computing tile includes a reconfigurable processing element and a network fabric interface device configured to communicate over a network fabric. The reconfigurable processing element operates on data received from an I/O input interface and/or data received via the network fabric interface device.

Abstract: An electronic apparatus and an operation method thereof are provided. The electronic apparatus includes a nonvolatile memory, a first integrated circuit and a second integrated circuit. The nonvolatile memory stores the first firmware code of the first integrated circuit and the second firmware code of the second integrated circuit. The first integrated circuit is coupled to a memory access interface of the nonvolatile memory to read the first firmware code and the second firmware code. The first integrated circuit has an emulation memory access interface to emulate an emulation memory. The second integrated circuit is coupled to the emulation memory access interface of the first integrated circuit. The second integrated circuit reads the second firmware code from the first integrated circuit via the emulation memory access interface.

Abstract: Circuits, methods, and apparatus for storing application data, keys, authorization codes, or other information in a volatile memory on an FPGA. A field programmable gate array (FPGA) can include multiple memory blocks and partition those blocks among multiple independent reconfigurable regions. Access to the memory blocks can then be restricted so that only authorized regions have access to particular memory partitions. In addition, each partition can store multiple message authentication codes (MACs) for further controlling access to data in each partition.

Abstract: The present disclosure discloses a mask, which includes a first substrate and a second substrate. The mask further includes a polarity particle positioned between the first substrate and the second substrate. The polarity particle has a light absorption or light transmission effect. The first substrate includes a plurality of driving electrodes disposed toward the second substrate and arranged in an array. Each of the driving electrodes is configured to receive an electric signal and control the polarity particle to move to a designated driving electrode to form a pattern.

Abstract: A data loading system includes a processing circuit, a nonvolatile memory, and a programmable logic device. The processing circuit and the programmable logic device are separately coupled to different data interfaces of the nonvolatile memory. The nonvolatile memory stores start code of the processing circuit and configuration data of the programmable logic device, and the processing circuit and the programmable logic device are configured to respectively obtain the start code and the configuration data from the nonvolatile memory at the same time under the action of a first synchronization clock. Hence, the system increases a speed and reliability of data loading and increases a start speed and reliability of a board.

Abstract: An in-memory computing system for computing vector-matrix multiplications includes an array of resistive memory devices arranged in columns and rows, such that resistive memory devices in each row of the array are interconnected by a respective wordline and resistive memory devices in each column of the array are interconnected by a respective bitline. The in-memory computing system also includes an interface circuit electrically coupled to each bitline of the array of resistive memory devices and computes the vector-matrix multiplication between an input vector applied to a given set of wordlines and data values stored in the array. For each bitline, the interface circuit receives an output in response to the input being applied to the given wordline, compares the output to a threshold, and increments a count maintained for each bitline when the output exceeds the threshold. The count for a given bitline represents a dot-product.

Abstract: The present disclosure includes apparatuses and methods for data movement. An example apparatus comprises a memory device. The memory device includes an array of memory cells and sensing circuitry coupled to the array via a plurality of sense lines. The sensing circuitry includes a sense amplifier and a compute component coupled to a sense line and configured to implement operations. A controller in the memory device is configured to couple to the array and sensing circuitry. A shared I/O line in the memory device is configured to couple a source location to a destination location.

Abstract: Examples described herein generally relate to a layered boundary interconnect in an integrated circuit (IC) and methods for operating such IC. In an example, an IC includes a programmable logic region, a plurality of input/output circuits, a plurality of hard block circuits, and a programmable native transmission network. The programmable native transmission network is connected to and between the plurality of input/output circuits and the plurality of hard block circuits. The plurality of hard block circuits is connected to and between the programmable native transmission network and the programmable logic region.

Abstract: A partial decoder and event detection logic are deployed in a non-volatile memory system to offload processing from a host system while maintaining high video recording performance and backward compatibility with conventional host system logic.

Abstract: An SRAM architecture to optimize the performance of the SRAM. The local bit-lines are activated one at a time with control signals from a decoder. The global bit-lines are broken with repeaters to optimize performance. This guarantees optimal performance for the SRAM array across a wide range of supply voltages spanning from the nominal voltage of a process to a sub-threshold range.

Abstract: A parallel processing unit includes a plurality of main processing units and a decision processing unit. Each of the plurality of main processing units includes a main processing calculator for performing a calculation on one or more inputs, a main processing adder for adding an output of the main processing calculator and an output of a decision processing delayer, and a main processing comparator for making a comparison with an output of the main processing adder. The decision processing unit includes a decision processing calculator for adding outputs of the plurality of main processing calculators, a decision processing adder for adding an output of the decision processing calculator and the output of the decision processing delayer, the decision processing delayer for delaying an output of the decision processing adder, and a decision processing comparator for making a comparison with the output of the decision processing adder.

Abstract: A logic cell structure includes: a first portion, with a first height, arranged to be a first layout of a first semiconductor element; a second portion, with the first height, arranged to be a second layout of a second semiconductor element, wherein the first portion is separated from the second portion; and a third portion arranged to be a third layout of an interconnecting path used for coupling the first semiconductor element and the second semiconductor element.

Abstract: A field programmable gate array (FPGA) includes: a first logic block having a first lookup table; and a second logic block having a second lookup table, wherein the first logic block is coupled to the second logic block, in which the first logic block is configured to pass, upon a clock cycle of the FPGA, data about a lookup table configuration stored in the first lookup table to the second logic block.

Abstract: A method for designing a system on a target device is disclosed. The system is synthesized from a register transfer level description. The system is placed on the target device. The system is routed on the target device. A configuration file is generated that reflects the synthesizing, placing, and routing of the system for programming the target device. A modification for the system is identified. The configuration file is modified to effectuate the modification for the system without changing the placing and routing of the system.

Abstract: A method of routing interconnects of a field programmable gate array including: a plurality of logic tiles, and a tile-to-tile interconnect network, having a plurality of tile-to-tile interconnects to interconnect logic tile networks of the logic tiles, the method comprises: routing a first plurality of tile-to-tile interconnects in a first plurality of logic tiles. After routing the first plurality of tile-to-tile interconnects, routing a second plurality of tile-to-tile interconnects in a second plurality of logic tiles. The start/end point of each tile-to-tile interconnect in the first plurality and the second plurality of tiles is independent of the start/end point of the other tile-to-tile interconnects in the first and second plurality, respectively.

Abstract: A semiconductor package includes a redistribution layer having a first surface and a second surface opposite to each other, the redistribution layer including a plurality of first redistribution pads on the first surface, a semiconductor chip on the second surface of the redistribution layer, an active surface of the semiconductor chip facing the redistribution layer, a plurality of conductive structures on the second surface of the redistribution layer, the plurality of conductive structures being spaced apart from the semiconductor chip, and a plurality of external connection terminals on and coupled to the conductive structures, the plurality of first redistribution pads have a pitch smaller than a pitch of the plurality of external connection terminals.

Abstract: Provided are embodiments including a system and method for operating a reconfigurable control architecture for programmable logic devices. Some embodiments include a storage medium that is coupled to a programmable logic device and a dispatch mechanism that is operably coupled to the programmable logic device. In embodiments, the dispatch mechanism is configured is receive an object, select one or more constructs of the programmable logic device based on the object, schedule one or more inputs and outputs for each of the selected constructs based on the object, and execute a system level operation indicated by the object based on the schedule.

Abstract: A sense amplifier utilizes a phase transition material (PTM) in conjunction with CMOS circuits to provide a precise sensing threshold. The sense amplifier can be used in memory applications to sense states of stored bits with high accuracy and robustness. In one sense amplifier, a first diode-connected transistor has gate and drain nodes coupled to an input node of the sense amplifier, a second transistor has a gate node coupled to the gate node of the first diode-connected transistor, and the PTM is coupled to the source node of the second transistor. In another sense amplifier, a first transistor has a gate node coupled to an input node of the sense amplifier, a PTM is coupled to the source node of the first transistor, and an output stage including an inverter is coupled between a drain node of the first transistor and an output node of the sense amplifier.

Abstract: A device may include a processor system and an array of data processing engines (DPEs) communicatively coupled to the processor system. Each of the DPEs includes a core and a DPE interconnect. The processor system is configured to transmit configuration data to the array of DPEs, and each of the DPEs is independently configurable based on the configuration data received at the respective DPE via the DPE interconnect of the respective DPE. The array of DPEs enable, without modifying operation of a first kernel of a first subset of the DPEs of the array of DPEs, reconfiguration of a second subset of the DPEs of the array of DPEs.

Abstract: A multi-die integrated circuit with improved testability can include at least two dies that combined comprise an integrated circuit for a self-contained system, which includes logic and design-for-test features. The integrated circuit is split into at least two portions, where each portion is disposed on a corresponding one of the at least two dies. As part of the improved testability for both pre-bond testing of logic and post-bond testing of inter-die connections, at least one of the at least two dies further comprises a split-circuit-boundary scan chain. An automated design tool can be used to determine optimal ways for the integrated circuit for a self-contained system to be split into at least two portions for the corresponding at least two dies. In addition, a split-circuit-boundary scan chain option can be applied for each portion, via the automated design tool, to ensure boundary scans are available on timing paths.

Abstract: A process for wear-leveling in a memory subsystem where references to invalidated chunks and a write count for each of the invalidated chunks of a memory subsystem are received by a wear-leveling manager. The wear-leveling manager orders the received references to the invalidated chunks of the memory subsystem in a tracking structure based on the write count of each of the invalidated chunks, and provides a reference to at least one of the invalidated chunks based on the ordering from the tracking structure to a write scheduler to service a write request, wherein the memory subsystem is wear-leveled by biasing the order of the invalidated chunks to prioritize low write count chunks.

Abstract: A standard cell layout for a data storage circuit includes a latch and an initialization circuit. Metallization levels over the standard cell layout support circuit interconnections. At least one metallization level is provided for metal programming of an initialization configuration of the data storage circuit. The at least one metallization level may have: a first wiring layout for interconnecting the initialization circuit to the latch for configuration programming of the data storage circuit as an initialization in reset device (assertion of an initialization signal causing the data storage circuit data output to be reset), or a second wiring layout for interconnecting the initialization circuit to the latch for configuration programming of the data storage circuit as an initialization in set device (assertion of the initialization signal causing the data storage circuit data output to be set).

Abstract: A circuit device includes first and second output signal lines from which first and second output signals constituting differential output signals are output, and first to n-th output drivers coupled to the first and second output signal lines. In a first mode, i number of output drivers of the first to n-th output drivers drive the first and second output signal lines based on first and second input signals constituting differential input signals. In a second mode, j number of output drivers of the first to n-th output drivers drive the first and second output signal lines based on the first and second input signals.

Abstract: An integrated circuit including an FPGA, configurable to process data via a plurality of data processing operations, and an ASIC, electrically coupled to logic circuitry of the FPGA via switch interconnect network thereof. In one embodiment, the ASIC includes a plurality of circuit blocks, each circuit block configurable to process data via a data processing operation, and selection circuitry, coupled to the logic circuitry of the FPGA and the plurality of circuit blocks of the ASIC, configurable to connect one or more of the plurality of circuit blocks of the ASIC and the logic circuitry of the FPGA into a first circuit configuration to perform a first data processing operation, and in situ, connect one or more of the plurality of circuit blocks of the ASIC and the logic circuitry of the FPGA into a second circuit configuration to perform a second data processing operation.

Abstract: An integrated circuit system includes: a storage element which stores in advance a plurality of pieces of circuit information and startup control circuit information used to configure a startup control logic circuit for selecting circuit information that has not failed in configuring a logic circuit; and an integrated circuit which, at the time of startup or when configuration of the logic circuit based on any of the plurality of pieces of circuit information has failed, configures the startup control logic circuit by reading the startup control circuit information from the storage element, causes the configured startup control logic circuit to select the circuit information that has not failed in configuring the logic circuit, reads the circuit information selected by the startup control logic circuit from the storage element, and configures the logic circuit according to the circuit information.

Abstract: Systems and methods for sensing an analog signal through digital input/output (I/O) pins are provided. Aspects include an analog to digital (ADC) circuit configured to generate a digital signal based on observations of the analog signal obtained from an analog circuit, where the ADC circuit includes a difference amplifier, a comparator, a divideby2 counter and two AND gates. Aspects also include a controller including a pin configured to receive the digital signal. The controller is configured to count pulses within the digital signal and determine values corresponding to the analog signal based on the counted pulses.

Abstract: A power loss protection integrated circuit includes a storage capacitor terminal (STR), an autonomous capacitor health check circuit, and a capacitor fault terminal (CF). The capacitor health check circuit autonomously performs periodic capacitor check operations. In a check operation, current is sinked from the STR terminal for a predetermined time and in a predetermined way. If during this time the voltage on the STR terminal STR drops below a predetermined voltage, then a digital signal CF is asserted onto the CF terminal. Immediately following each capacitor check, a charging voltage is driven onto the STR terminal to recharge the external capacitors coupled to the STR terminal. In one example, the integrated circuit further includes a current switch circuit (eFuse) and a buck/boost controller. The capacitor health check circuit is only enabled during normal mode operation of the integrated circuit, and the check circuit disables boost operation during capacitor checks.

Abstract: “Shoot-through” timing failures in a scan chain of a defective semiconductor integrated circuit corrupt test pattern data used to perform failure analysis. Methods and procedures are provided to detect “shoot-through” conditions, determine the number of shoot-through scan cells, and to determine the location of the shoot-through cells within a scan chain. Reset test pattern results can be analyzed to identify candidate locations of shoot-through cells and when combined with candidate cell locations from analysis of physical clock distribution trees and potential clock-skew issues, the exact location of all shoot-through cells can be determined. Methods are also provided to use shoot-through cell locations to identify the defective clock net containing the physical defect causing the clock skew conditions needed to produce shoot-through timing failures.

Abstract: A semiconductor device assembly that includes a second side of an interposer being connected to a first side of a substrate. A plurality of interconnects may be connected to a second side of the substrate. First and second semiconductor devices are connected directly to the first side of the interposer. The interposer is configured to enable the first semiconductor device and the second semiconductor device to communicate with each other through the interposer. The interposer may be a silicon interposer that includes complementary metal-oxide-semiconductor circuits. The first semiconductor device may be a processing unit and the second semiconductor device may be a memory device, which may be a high bandwidth memory device. A method of making a semiconductor device assembly includes attaching both a memory device and a processing unit directly to a first side of an interposer and connecting a second side of the interposer to a substrate.

Abstract: A device programming system, and a method of operation thereof, includes: a field programmable gate array unit configured using a programming driver retrieved based on a device type of a first programmable device; and a second programmable device and the first programmable device configured simultaneously using a master image and the field programmable gate array unit.

Abstract: Examples described herein provide for a boundary logic interface (BLI) to a programmable logic region in an integrated circuit (IC), and methods for operating such IC. An example IC includes a programmable logic region and boundary logic interfaces. The programmable logic region includes columns of interconnect elements disposed between columns of logic elements. The boundary logic interfaces are at respective ends of and communicatively connected to the columns of interconnect elements. The boundary logic interfaces are outside of a boundary of the programmable logic region. A first boundary logic interface (BLI) of the boundary logic interfaces is configured to be communicatively connected to an exterior circuit. The first BLI includes an interface configured to communicate a signal between the exterior circuit and the programmable logic region.

Abstract: An information processing apparatus having a reconfigurable circuit capable of rewriting a logic circuit includes, a process determination circuit that determines which of a plurality of processes is to be executed, a standby buffer circuit that holds process data to be used in a process waiting for execution among processes determined by the process determination circuit, and a rewrite control circuit that rewrites the current logic circuit written in the reconfigurable circuit to a logic circuit that executes one of the plurality of processes waiting for execution using each of a plurality of process data held in the standby buffer circuit when the amount of process data held in the standby buffer circuit exceeds a first predetermined amount.

Abstract: In accordance with a first aspect of the present disclosure, a method of designing an integrated circuit is conceived, comprising: placing integrated circuit cells that include supply pins in a plurality of predefined rows; determining blocked areas for supply pin extensions; extending the supply pins outside said blocked areas. A corresponding integrated circuit is also provided.

Abstract: A device comprising: at least one partially reconfigurable FPGA; a Network-on-Chip (NoC) comprised in the FPGA; and at least one area on the at least one FPGA operable to house a hardware micro-service (HMS); wherein an HMS image may be loaded onto the area of the at least one FPGA via partial reconfiguration to form a new HMS, and the NoC is operable to forward information to and from the new HMS without the NoC being reloaded.

Abstract: Provided is a programmable logic integrated circuit wherein even if a failure occurs in any resistance-variable element, remedy would be possible and hence the improvement of reliability has been achieved. In a programmable logic integrated circuit comprising resistance-variable elements, when the states of the resistance-variable elements are to be changed according to externally inputted configuration information, a control means uses a reading means to read the states of the respective resistance-variable elements, and then uses a writing means to change only the states of resistance-changing elements that are different from a state indicated by the configuration information.

Abstract: A programmable semiconductor device capable of being selectively programmed to perform one or more logic functions includes a first region, second region, first regional power control (“RPC”), and second-to-first power control connection. The first region, in one embodiment, contains first configurable logic blocks (“CLBs”) able to be selectively programmed to perform a first logic function. The second region includes a group of second CLBs configured to be selectively programmed to perform a second logic function. The first RPC port or inter-chip port which is coupled between the first and second regions facilitates dynamic power supply to the first region in response to the data in the second region. The second-to-first power control connection is used to allow the second region to facilitate and/or control power to the first region.

Abstract: A voltage detector circuit including a ladder selector that includes a first node, a second node and a selector node. The voltage detector circuit also includes a first resistive ladder that includes a first string of resistors coupled between a sensing input node and the first node of the ladder selector and a first set of transistors. An input node of each transistor in the first set of transistors is coupled to a respective intermediate node between two resistors in a subset of resistors in the first string of resistors and an output node of each transistor in the first set of transistors is coupled to a sensing output node. The voltage detector circuit also includes a second resistive ladder that includes a second string of resistors coupled between the sensing input node and the second node of the ladder selector and a second set of transistors.

Abstract: The present techniques generally relate to a method of monitoring for a fault event in a lockstep processing system having a plurality of cores configured to operate in lockstep, the method having: power gating, for a period of time, a subset of cores of the plurality of cores from a first power source and providing power to the subset of cores from a second power source for the period of time; processing, at each of the cores of the plurality of cores, one or more instructions; providing an output from each core of the plurality of cores to error detection circuitry to monitor for the fault event, the output from each core based on or in response to processing the one or more instructions during the period of time.