Abstract: There are provided a lighting control method, system, and device for an NVME backboard, and a medium. The method is applied to a mainboard. The method includes: executing a target code for parsing a target VPP signal upon reception of the target VPP signal, where the target code is added in the mainboard in advance and stores VPP addresses respectively corresponding to NVME backboards connected with the mainboard; parsing the target VPP signal to obtain a target VPP address corresponding to the target VPP signal; and delivering the target VPP address to a target NVME backboard corresponding to the target VPP address to light the target NVME backboard.

Abstract: A system comprises an integrated circuit die substrate; volatile memory electrically coupled to the integrated circuit die substrate; a first integrated circuit die element electrically coupled to the integrated circuit die substrate, the first integrated circuit die element comprising a first field programmable gate array (FPGA), and the first integrated circuit die element disposed adjacent to the volatile memory; a battery charger operable to receive power from a main power supply, the main power supply having an on state and an off state, wherein the main power supply is supplying power in the on state and not supplying power in the off state; and a battery module disposed on a top portion of the first integrated circuit die element, the battery module operable to receive power from the battery charger, and the battery module operable to supply power to the volatile memory at least when the main power supply is in the off state.

Abstract: A display device includes a display panel including a display area in which an image is displayed and a peripheral area disposed outside of the display area, and a touch sensor disposed on the display panel. The touch sensor includes a plurality of sensor electrodes formed in a repeated arrangement of sensor patterns that forms a touch active area, a plurality of sensor wirings connected to the sensor electrodes and disposed outside of the touch active area, and at least one insulating layer overlapping the display area and the peripheral area. At least a portion of the sensor electrodes is formed over the display area and the peripheral area.

Abstract: Significantly optimized multi-stage networks, useful in wide target applications, with VLSI layouts using only horizontal and vertical links to route large scale sub-integrated circuit blocks having inlet and outlet links, and laid out in an integrated circuit device in a two-dimensional grid arrangement of blocks are presented. The optimized multi-stage networks in each block employ several rings of stages of switches with inlet and outlet links of sub-integrated circuit blocks connecting to rings from either left-hand side only, or from right-hand side only, or from both left-hand side and right-hand side; and employ shuffle exchange links where outlet links of cross links from switches in a stage of a ring in one sub-integrated circuit block are connected to either inlet links of switches in the another stage of a ring in the same or another sub-integrated circuit block.

Abstract: A system comprises an integrated circuit die substrate; volatile memory electrically coupled to the integrated circuit die substrate; a first integrated circuit die element electrically coupled to the integrated circuit die substrate, the first integrated circuit die element comprising a first field programmable gate array (FPGA), and the first integrated circuit die element disposed adjacent to the volatile memory; a battery charger operable to receive power from a main power supply, the main power supply having an on state and an off state, wherein the main power supply is supplying power in the on state and not supplying power in the off state; and a battery module disposed on a top portion of the first integrated circuit die element, the battery module operable to receive power from the battery charger, and the battery module operable to supply power to the volatile memory at least when the main power supply is in the off state.

Abstract: A mechanism is described for facilitating person tracking and data security in machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting, by a camera associated with one or more trackers, a person within a physical vicinity, where detecting includes capturing one or more images the person. The method may further include tracking, by the one or more trackers, the person based on the one or more images of the person, where tracking includes collect tracking data relating to the person. The method may further include selecting a tracker of the one or more trackers as a preferred tracker based on the tracking data.

Abstract: An analog vector-matrix multiplication circuit is achieved by using a programmable storage device array. In a programmable semiconductor device array, gates of all of programmable semiconductor devices of each row are all connected to the same analog voltage input end. M rows of programmable semiconductor devices are correspondingly connected to M analog voltage input ends. Drains (or sources) of all of programmable semiconductor devices of each column are all connected to the same bias voltage input end. N columns of programmable semiconductor devices are correspondingly connected to N bias voltage input ends. Sources (or drains) of all of programmable semiconductor devices of each column are all connected to the same analog current output end. The N columns of programmable semiconductor devices are correspondingly connected to N analog current output ends.

Abstract: Methods, systems, and devices for predictive power management are described. Correlations may be identified between a set of commands performed at the memory device and oscillating voltage patterns, or a resonance frequency, or both. Voltages may be monitored by the memory device and be compared to the identified voltage pattern to mitigate undesirable oscillating voltages and resonance frequency.

Abstract: Described is an apparatus for supporting Over-The-Air Hardware Updates comprising a first circuitry, a second circuitry, and a third circuitry. The first circuitry may be operable to be fastened and electrically coupled in one or more regions to one or more respectively corresponding semiconductor dies. The second circuitry may be operable to configure the one or more regions of the first circuitry. The third circuitry may be operable to provide a set of wirelessly-received configuration instructions to the second circuitry.

Abstract: A digital signal processing block has a first input port, a second input port, a third input port, a cascade input port and an output port. The DSP block may have a cascade output port. The DSP block may have a multiplexer that has selectable output, to the cascade output port, of concatenated inputs from the first input port, the second input port and the third input port. The DSP block may be connectable to another DSP block via a cascade path. The DSP block may have a variable shifter. The DSP block may have a full-width adder and reduced-width input ports.

Abstract: Aspects of the embodiments are directed to a ThunderBolt (TBT) input/output (I/O) controller apparatus. The TBT I/O controller apparatus can include an output port to receive a connection to a display device; a multiplexer coupled to the output port; a first input port coupled to the multiplexer; a second input port coupled to the multiplexer; a memory element to store graphics preference data; and TBT firmware (FW). The TBT FW can detect a connected device at the input port; determine a graphics processor for the connected device based on the graphics preference data; and logically connect the connected device to one of the first input port or the second input port through the multiplexer based on the determined graphics processor.

Abstract: In an embodiment, responsive to determining: (a) a first command is not of a particular command type associated with one or more hardware modules associated with a particular routing node, or (b) at least one argument used for executing the first command is not available: transmitting the first command to another routing node in the hardware routing mesh. Upon receiving a second command of the command bundle and determining: (a) the second command is of the particular command type associated with the hardware module(s), and (b) arguments used by the second command are available: transmitting the second command to the hardware module(s) associated with the particular routing node for execution by the hardware module(s). Thereafter, the command bundle is modified based on execution of the second command by at least refraining from transmitting the second command of the command bundle to any other routing nodes in the hardware routing mesh.

Abstract: Disclosure is made of a shared memory switch and methods and system for controlling such. The shared memory switch may allocate cells in a storage array to respective use cases, the use cases including input buffering, output queuing, free cell allocation, and retry buffering. A set of data packets may be stored in the cells allocated to output queuing, wherein each cell allocated to output queuing stores a respective data packet of the set of data packets. A subset of the set of data packets may be transmitted to a destination external to the shared memory switch. The cells storing the subset of data packets may be reallocated to the retry buffering use case, wherein cells allocated to retry buffering use case are a retry buffer.

Abstract: A programmable device structure based on a mixed function storage unit includes a storage unit SRAM and a mixed function unit, wherein the storage unit comprises n register units and at least one selection control bit, wherein n=2{circumflex over (?)}x, and x is natural number; the register units are selected according to the selection control bit; and when the selection control bit selects the mixed function unit to serve as a lookup table, a logic function is achieved; or when the selection control bit selects the mixed function unit to serve as a multiplexer, a routing function is achieved. By multiplexing the register units, the programmable device structure achieves a routing function of a traditional FPGA and also provides a logic function, and the waste of resources is greatly reduced.

Abstract: A lateral transfer path within an adjustable-width signaling interface of an integrated circuit component is formed by a chain of logic segments that may be intercoupled in different groups to effect the lateral data transfer required in different interface width configurations, avoiding the need for a dedicated transfer path per width configuration and thereby substantially reducing number of interconnects (and thus the area) required to implement the lateral transfer structure.

Abstract: An adder-subtractor circuit includes an inverting circuit configured to invert a first operand on a bit-by-bit basis to output a first inverted operand, a circuit having a function to perform a predetermined arithmetic operation and configured to output a second operand, a carry generating circuit configured to generate carries from the first inverted operand and the second operand, and an XOR circuit configured to perform a bit-by-bit XOR on the carries, the first operand, and the second operand.

Abstract: Circuitry is provided that includes programmable fabric with fine-grain routing wires and a separate programmable coarse-grain routing network that provides enhanced bandwidth, low latency, and deterministic routing behavior. The programmable fabric may be implemented on a top die that is stacked on the active interposer die. The programmable coarse-grain routing network and smart memory circuitry may be implemented on an active interposer die. the smart memory circuitry may be configured to perform higher level functions than simple read and write operations. The smart memory circuitry may carry out command based low cycle count operations using a state machine without requiring execution of a program code, complex microcontroller based multicycle operations, and other non-generic microcontroller based smart RAM functions.

Abstract: Devices, systems, and methods for reducing sensing delays for a non-volatile memory reading circuit may include operations for pre-charging a plurality of bit lines coupling a memory array having multiple bit cells with a sensing amplifier. Upon receiving a read request identifying a given bit cell in the memory array, the addressed bit line is decoupled from a bias voltage. The addressed bit line corresponds to the given bit cell and is selected from the plurality of bit lines. With the decoupling from the bias voltage, the addressed bit lines are coupled to the sensing amplifier. After a sensing circuit delay, data stored in the given bit cell is provided to the sensing amplifier via the addressed bit lines coupled to the sensing amplifier. The data stored in the given bit cell may then be interpreted by the sensing amplifier and a corresponding data output signal is generated.

Abstract: A memory circuit includes input multiplexers passing one of a pair of input bits. A first input multiplexer receives a first data bit and a serial input bit. Additional input multiplexers receive either a respective pair of data (D) bits, or a write-enable (WEN) bit and a single D bit. Scan latches receive one of the input bits and provide a scan output bit. OR gates arranged receive the scan output bit from a different scan latch, and perform a logical OR operation thereon to generate an OR output bit. Downstream output multiplexers pass a corresponding bit from a bit array or the OR output bit from a corresponding OR gate, and sense latches receive the corresponding bit from one of the output multiplexers and provide a sense output bit. Each sense output bit feeds into one or more input multiplexers when a bit-write-mask function is disabled.

Abstract: A method for controlling power supply in a semiconductor device including a CPU and a PLD which can hold data even in an off state is provided. The semiconductor device includes a processor, a programmable logic device, and a state control circuit. The programmable logic device includes a first nonvolatile memory circuit and has a function of holding data obtained by arithmetic processing of the programmable logic device when it is turned off. The state control circuit obtains data on the amount of a task performed by the programmable logic device in accordance with an operation of the processor. The programmable logic device detects the state of progress of the task and outputs a signal to the state control circuit. The state control circuit monitors the amount of the task and the state of progress of the task and turns off the programmable logic device when the task is completed.

Abstract: In one example, an integrated circuit includes a register interface that includes a plurality of registers, a bus interface configured to monitor write requests transmitted to the register interface, where the write requests include a target address and data to be written. The bus interface is configured to receive the data to be written to the plurality of registers and register selection signals for selecting a respective register in the plurality of registers. The integrated circuit includes a monitoring circuit configured to monitor the register selection signals between the bus interface and the plurality of registers in order to determine when the data to be written to the plurality of registers is valid.

Abstract: Systems and methods are provided to enhance the functionality of an integrated circuit. Such an integrated circuit may include a primary circuitry and an embedded programmable logic programmable to adjust the functionality of the primary circuitry. Specifically, the embedded programmable logic may be programmed to adjust the functionality of the primary circuitry to complement and/or support the functionality of another integrated circuit. Accordingly, the embedded programmable logic may be programmed with functions such as data/address manipulation functions, configuration/testing functions, computational functions, or the like.

Abstract: Manufacturing integrated circuits is discussed with steps as follows. Creating a wafer with a plurality of dies, where each die contains its own integrated circuit. Fabricating multiple instances of TAP circuitry located in a margin between dies of the wafer. Fabricating on the wafer one row of test pads and power pads per group of dies on the wafer, where the row of test pads and power pads is electrically connected and shared among all of the dies in the group. The test and power pads connect to a chain of TAP circuitry in order to supply operating power as well as testing data to verify the integrity of each die in that group of dies. Singulating the dies to create each instance of the integrated circuit, and during the singulation process, the TAP circuitry located in the margin between the dies is destroyed.

Abstract: A method of routing interconnects of a field programmable gate array including: a plurality of logic tiles, and a tile-to-tile interconnect network, having a plurality of tile-to-tile interconnects to interconnect logic tile networks of the logic tiles, the method comprises: routing a first plurality of tile-to-tile interconnects in a first plurality of logic tiles. After routing the first plurality of tile-to-tile interconnects, routing a second plurality of tile-to-tile interconnects in a second plurality of logic tiles. The start/end point of each tile-to-tile interconnect in the first plurality and the second plurality of tiles is independent of the start/end point of the other tile-to-tile interconnects in the first and second plurality, respectively.

Abstract: The technology relates to a system on chip (SoC). The SoC may include a plurality of network layers which may assist electrical communications either horizontally or vertically among components from different device layers. In one embodiment, a system on chip (SoC) includes a plurality of network layers, each network layer including one or more routers, and more than one device layers, each of the plurality of network layers respectively bonded to one of the device layers. In another embodiment, a method for forming a system on chip (SoC) includes forming a plurality of network layers in an interconnect, wherein each network layer is bonded to an active surface of a respective device layer in a plurality of device layer.

Abstract: An FPGA system includes: an FPGA configured such that a partial reconfiguration is executable; and an external storage medium that is positioned outside of the FPGA and stores configuration data that is readable by the FPGA. The external storage medium stores first configuration data indicating a configuration of a circuit that is not subject to the partial reconfiguration and a second configuration data indicating a configuration of a circuit that is subject to the partial reconfiguration. The first configuration data includes configuration data indicating a configuration of a reconfiguration activation circuit for reading the second configuration data from the external storage medium and deploying the configuration indicated by the second configuration data.

Abstract: Disclosed herein is a semiconductor integrated circuit device which can ensure sufficient power supply ability and ESD protection capability for an I/O cell without increasing the area of the semiconductor integrated circuit. In-row power supply interconnects provided in I/O cell rows are connected to a power supply interconnect provided between the I/O cell rows via power supply interconnects. The power supply interconnect is thicker than the in-row power supply interconnects.

Abstract: A processing-in-memory (PIM) device includes a multiplication/accumulation (MAC) operator. The MAC operator includes a multiplying block and an adding block. The multiplying block includes a first multiplier and a second multiplier. The first multiplier performs a first multiplying calculation of first half data of first data and first half data of second data. The second multiplier performs a second multiplying calculation of second half data of the first data and second half data of the second data. The adding block performs an adding calculation of first multiplication result data outputted from the first multiplier and second multiplication result data outputted from the second multiplier. The MAC operator receives a test mode signal having a first level to perform a test operation for the multiplying block.

Abstract: A system and apparatus can include a first port configured to support a first link width; a second port configured to support a second link width, the second link width different from the first link width; and physical layer logic to receive from the first port a first data block arranged according to the first link width and frequency; create at least one second data block arranged according the second link width and frequency, the at least one second data block including data bytes from the first data block arranged sequentially in the at least one second data block; and transmit the at least one second data block to the second port.

Abstract: Multi-level hierarchical routing matrices for pattern-recognition processors are provided. One such routing matrix may include one or more programmable and/or non-programmable connections in and between levels of the matrix. The connections may couple routing lines to feature cells, groups, rows, blocks, or any other arrangement of components of the pattern-recognition processor.

Abstract: A device includes an AND logic gate and a D latch. The AND logic gate includes a first input configured to be coupled to a third-party device to receive a selection signal, a second input configured to be coupled to the third-party device to receive a status signal, and an output configured to transmit an output signal when the selection signal and the status signal are received. The D latch is capable of storing datum. The D latch includes an activation input coupled to the output of the AND logic gate and a data input configured to be coupled to the third-party device to receive a data signal that is representative of the datum. The D latch is configured to store the datum in response to the output signal.

Abstract: Software tools disclosed herein may allow a user to enter design choices that alter an aesthetic appearance of a machine-readable label such that modules included in the label deviate from a standardized definition for the modules. Such alterations may include changes in size, color and orientation of modules. The alterations may allow a user to create machine-readable labels having unique aesthetic appearances. A software engine may ensure that, despite the aesthetic design choices entered by a user, the generated machine-readable label is reliably scannable.

Abstract: Systems and methods for providing external bus protection for programmable logic devices (PLDs) are disclosed. An example system includes a programmable I/O bus configured to interface with a user device over an external bus interface coupled to a PLD; a bus protection circuit arrangement integrated with the programmable I/O interface and configured to provide I/O bus supply voltage protection for the programmable I/O interface; and a bus protection control signal generator. The bus protection control signal generator generates a default bus protection control signal for the bus protection circuit arrangement of the PLD prior to completion of a power ramp performed by the user device; an intermediate bus protection control signal for the PLD prior to completion of loading a PLD configuration into a PLD fabric of the PLD; and an operational bus protection control signal for the PLD.

Abstract: Systems and methods for a bit-cell are presented. The bit-cell comprises a read-port circuit and a write-port circuit. The read-port circuit comprises four transistors, wherein the read-port circuit is activated by a first threshold voltage. The write-port circuit comprises eight transistors, wherein the write-port circuit is activated by a second threshold voltage. The write-port circuit is coupled to the read-port circuit. The first threshold voltage and the second threshold voltage may be different and may be provided by a single supply voltage.

Abstract: An example programmable device includes a configuration memory configured to store configuration data; a programmable logic having a configurable functionality based on the configuration data in the configuration memory; a signal conversion circuit; a digital processing circuit; an endpoint circuit coupled to the signal conversion circuit through the digital processing circuit; wherein the digital processing circuit includes a first one or more digital processing functions implemented as hardened circuits each having a predetermined functionality, and a second one or more processing functions implemented by the configurable functionality of the programmable logic.

Abstract: The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a plurality of reconfigurable logic regions. Each reconfigurable region can include hardware that is configurable to implement an application logic design. The host logic can be used for separately encapsulating each of the reconfigurable logic regions. The host logic can include a plurality of data path functions where each data path function can include a layer for formatting data transfers between a host interface and the application logic of a corresponding reconfigurable logic region. The host interface can be configured to apportion bandwidth of the data transfers generated by the application logic of the respective reconfigurable logic regions.

Abstract: A memory circuit device includes multiple memory cells that are each constituted of a resistive memory element; a write circuit unit that is configured to write data to any one of the memory cells which is designated by cell designating information, and a read circuit unit that is configured to read out, from the memory cell designated by the cell designating information, data written in the memory cell. The memory circuit device has a configuration including a selection circuit unit that is shared by both of the write circuit unit and the read circuit unit and configured to select a memory cell to be activated from the multiple memory cells based on cell designating information, and a control circuit unit that is configured to selectively enable any one of writing of data by the write circuit unit and reading of data by the read circuit unit with respect to the memory cell selected by the selection circuit unit.

Abstract: A device includes a processor, an SBI, and a plurality of interfaces. The processor is configured to manage operations of the device. The SBI is coupled to the processor. The plurality of interfaces is associated with the SBI. The interfaces of the plurality of interfaces have different interface protocol from one another. The SBI is configured by the processor and the configuration of the SBI activates one interface of the plurality of interfaces at any given time. The active interface that is selected from the plurality of interfaces and a host have a same interface protocol. The active interface is configured to receive host data from the host. The SBI is configured to generate a flag for the processor in response to the active interface receiving the host data. The SBI is configured to transmit device data to the host.

Abstract: A method for programming a Field Programmable Gate Array (FPGA) via a network, the network being operated according to a predetermined communications protocol, can include: establishing a communication connection between the FPGA and an external master, setting the FPGA into a programming mode, the master providing an FPGA programming image to the FPGA in a sequence of frames so that the frames can be parsed and enabling the FPGA to write only during receiving the payload section of the frames. The FPGA programming image and parsing the sequence of frames can be performed by a permanently programmed or hardwired logic component. A network, FPGA, and a communication system can be configured to utilize embodiments of the method.

Abstract: Various embodiments provide for clock network generation for a circuit design using an inverting integrated clock gate (ICG). According to some embodiments, a clock network with one or more inverting ICGs is generated, after a topology of the clock network is defined, by applying a non-inverting ICG-to-inverting ICG transform to one or more nodes of the clock network that comprise a non-inverting ICG. Additionally, according to some embodiments, a clock network is generated bottom-up (from the clock sinks to the root clock signal source) using one or more inverting ICGs.

Abstract: A network interface device has an interface configured to interface with a network. The interface is configured to at least one of receive data from the network and put data onto the network. The network interface device has an application specific integrated device with a plurality of data processing pipelines to process at least one of data which has been received from the network and data which is to be put onto said network and an FPGA arranged in a path parallel to the data processing pipelines.

Abstract: In one embodiment, a method includes: receiving, in a root tile of an accelerator device having a plurality of tiles, a message from a processor, the message comprising a register write request to a register of a first remote tile of the plurality of remote tiles; decoding, in an endpoint controller of the root tile, a system address of the message to identify a destination tile for the message, based at least in part on a base address register decode of the system address; and in response to identifying the first remote tile as the destination tile, updating a first portion of an address offset field of the system address to a predetermined value and directing the message to the first remote tile coupled to the root tile via a sideband interconnect. Other embodiments are described and claimed.

Abstract: A system construction support device includes a storage unit, an operation receiving unit, a setting unit, and an arrangement control unit. The storage unit stores a system configuration file having a base area including a plurality of objects hierarchized, the plurality of objects each being design information on an instrument of a factory automation system. The setting unit sets identification information for at least one of the plurality of objects on the basis of the user operation received by the operation receiving unit. The arrangement control unit moves the object for which the identification information has been set by the setting unit, to a different location within the system configuration file or to an external file, and places a dummy object at an original location of the object moved to the different location, the dummy object including the identification information set for the object moved and information on a destination of the object moved.

Abstract: Various embodiments provide for clock network generation for a circuit design using a negative-edge integrated clock gate (ICG). According to some embodiments, a clock network with one or more negative-edge ICGs is generated, after a topology of the clock network is defined, by applying a positive-edge ICG-to-negative-edge ICG transform to one or more nodes of the clock network that comprise a positive-edge ICG. Additionally, according to some embodiments, a clock network is generated bottom-up (from the clock sinks to the root clock signal source) using one or more negative-edge ICGs.

Abstract: A method and apparatus for dynamically monitoring, measuring, and adjusting a clock duty cycle of an operating storage device is disclosed. A storage device includes a measuring circuit comprising a plurality of flip flop registers coupled to a first input line, with each flip flop register having a first input and a second input. One or more delay taps are coupled to each flip flop register, and are disposed on a second input line. While the device operates, a clock signal is input directly into the first input of each flip flop register via the first input line. Simultaneously, the clock signal is input into the second input of each flip flop register through the one or more delay taps via the second input line. The flip flop registers are then read to determine the clock duty cycle of the device, and the clock frequency is adjusted as needed.

Abstract: Circuitry is provided that includes programmable fabric with fine-grain routing wires and a separate programmable coarse-grain routing network that provides enhanced bandwidth, low latency, and deterministic routing behavior. The programmable coarse-grain routing network may be implemented on an active interposer die. The programmable fabric may be implemented on a top die that is stacked on the active interposer die. A protocol-based network on chip (NoC) may be overlaid on the coarse-grain routing network. Although the NoC protocol is nondeterministic, the coarse-grain routing network includes an array of programmable switch boxes linked together using a predetermined number of routing channels to provide deterministic routing. Pipeline registers may be interposed within the routing channels at fixed locations to guarantee timing closure.

Abstract: The present disclosure includes apparatuses and methods for providing indications associated with power management events. An example apparatus may include a plurality of memory units coupled to a shared power management signal. In this example apparatus, each of the plurality of memory units may be configured to provide to the other of the plurality of memory units, via the shared power management signal, an indication of whether the one of the plurality of memory units is entering a power management event. Further, each of the plurality of memory units may be configured to, if the one of the plurality of memory units is entering the power management event, an indication of a particular operation type associated with the power management event.

Abstract: The present disclosure relates to modular transceiver-based network circuitries that may include internal configurable interfaces or gaskets. The configurable gaskets may facilitate integration of the network circuitries in electronic devices by providing a transparent interface to processing circuitries coupled to the network circuitries. Moreover, the configurable gaskets may also have a floorplan layout (e.g., a chiplet layout) that may facilitate coupling of multiple network circuitries to a single processing circuitry, in a modular manner.

Abstract: Program source code defined in a multi-threaded imperative programming language can be compiled into a circuit description for a synchronous digital circuit (“SDC”) that includes pipelines and queues. During compilation, data defining a debugging network for the SDC can be added to the circuit description. The circuit description can then be used to generate the SDC such as, for instance, on an FPGA. A CPU connected to the SDC can utilize the debugging network to query the pipelines for state information such as, for instance, data indicating that an input queue for a pipeline is empty, data indicating the state of an output queue, or data indicating if a wait condition for a pipeline has been satisfied. A profiling tool can execute on the CPU for use in debugging the SDC.

Abstract: Methods and apparatus are disclosed for programming reconfigurable logic devices such as FPGAs in a networked server environment. In one example, a system hosting a network service providing field programmable gate array (FPGA) services includes a network service provider configured to receive a request to implement application logic in a plurality of FPGAs, allocate a computing instance comprising the FPGAs in responses to receiving the request, produce configuration information for programming the FPGAs, and send the configuration information to an allocated computing instance. The system further includes a computing host that is allocated by the network service provider as a computing instance which includes memory, processors configured to execute computer-executable instructions stored in the memory, and the programmed FPGAs.