Abstract: To provide a highly reliable and low-power-consumption semiconductor device functioning as a programmable logic device. A monitor circuit is provided to monitor a change in the potential of a configuration memory in which a transistor is turned off to hold charge and a potential corresponding to the charge is stored as configuration data. The reset of the configuration data is controlled in accordance with the potential change. With such a structure, the configuration memory can be reconfigured before the configuration data is lost, resulting in improved reliability of the semiconductor device. In addition, reconfiguration can be performed every time data is lost. Accordingly, power consumption can be reduced as compared with the structure where reconfiguration is performed periodically.

Abstract: A method can include forming a plurality of access transistors, including forming second semiconductor regions over an integrated circuit substrate that are doped to a second conductivity type, the second semiconductor regions being over and in contact with first semiconductor regions doped to a first conductivity type, and forming third semiconductor regions doped to the first conductivity type in contact with the second semiconductor regions; forming a plurality of conductive structures, over and in contact with the third semiconductor regions; and forming programmable impedance memory cells over and in contact with the conductive structures.

Abstract: Dynamically controlling voltage for access (i.e., read and/or write) operations to magneto-resistive random access memory (MRAM) bit cells to account for process variations is disclosed. An MRAM bit cell process variation measurement circuit (PVMC) is configured to measure process variations in MTJs that affect MTJ resistance, which can change write current at a given fixed supply voltage applied to an MRAM bit cell. The MRAM bit cell PVMC may also be configured to measure process variations in logic circuits representing process variations in access transistors employed in MRAM bit cells. These measured process variations in MTJs and/or logic circuits are used to dynamically determine a supply voltage for access operations to MRAM.

Abstract: Circuits, methods, and apparatus are directed to an integrated circuit having a disabling element that can disable a reading of data from the circuit. Once the disabling element is set to not allow a reading of the data, the disabling element cannot be changed to allow a reading of the data. The data may be configuration data or internal data stored within the integrated circuit. Examples of the disabling element include a memory element, a break in a circuit line, and an input pad configuration.

Abstract: An apparatus such as a system-on-a-chip includes memory that is distributed through multiple functional hardware circuits. Each functional hardware circuit includes memory, and each functional hardware circuit can be configured to have its memory used either by the respective functional hardware circuit or by the apparatus' master device (e.g., main processor). For those functional hardware circuits that are not needed for a given application, their memories can be repurposed for use by the master device. Related methods are also disclosed.

Abstract: This technology relates generally to integrated circuit technologies, and more particularly, to methods and systems for configuring a field programmable device. In one embodiment, a method for configuring a field programmable device is provided. The method comprises: identifying information associated with a plurality of logic functions associated with a plurality of subsystems to be implemented on a field programmable device; determining, based on the information, a set of attributes associated with each of the plurality of subsystems; determining, based on the set of attributes, a first value indicative of an estimation of a total number of the sequential logic blocks, and a second value indicative of an estimation of a total number of the combinational logic blocks, for implementing the plurality of logic functions; determining, based on the first and second values, to configure a first field programmable device for implementing the plurality of logic functions.

Abstract: There is provided a logic device including memory cell units. Each of the memory cell units includes a pair of bit lines arranged corresponding to a column of memory cells, a word line, and an inverter unit connected to the pair of bit lines. The inverter unit includes a first CMOS and a second CMOS. The first CMOS is configured to receive an input signal from one of the pair of bit lines. The first CMOS includes a first MOS transistor and a second MOS transistor. The second CMOS is configured to receive an input signal from the other of the pair of bit lines. The second CMOS includes a third MOS transistor and a fourth MOS transistor. The inverter unit is configured to output a first differential signal and a second differential signal as a data signal.

Abstract: A programmable device, having an analog component coupled with an analog bus and a digital component coupled with a digital bus together with a set of 10 pads, each of which capable of being coupled to a bus line of one segment of the analog bus as well as to at least one digital bus line, and where the analog bus is capable of being used to connect a pair of the pads to each other.

Abstract: A function programmable circuit and an operation method thereof are provided. The function programmable circuit includes a micro-controller unit (MCU) and a field programmable gate array (FPGA). The FPGA is coupled to the MCU, and is capable of being configured to execute a first function and work with the MCU in a first period, while the FPGA is being programmed a second function by the MCU in the same first period. The FPGA is controlled by a function switch pulse output from the MCU to terminate the first period, and switched from the first function to the second function, and then executes the second function and works with the MCU in a second period.

Abstract: Testing of integrated circuits is achieved by a test architecture utilizing a scan frame input shift register, a scan frame output shift register, a test controller, and a test interface comprising a scan input, a scan clock, a test enable, and a scan output. Scan frames input to the scan frame input shift register contain a test stimulus data section and a test command section. Scan frames output from the scan frame output shift register contain a test response data section and, optionally, a section for outputting other data. The command section of the input scan frame controls the test architecture to execute a desired test operation.

Abstract: A method and system to perform physical synthesis in a chip design process using hierarchical wire-pin co-optimization are described. The method includes providing boundary conditions to each of a plurality of macros of the chip design from a unit level controller, the boundary conditions including initial pin locations and an indication of which of the pins are movable pins for each of the plurality of macros, performing macro-level physical synthesis at each of the plurality of macros, and providing feedback to the unit level controller based on the macro-level physical synthesis performed at each of the plurality of macros, the feedback including a proposed new location for the movable pins of each of the plurality of blocks. The method also includes performing hierarchical co-optimization at the unit level controller based on the feedback from each of the plurality of macros to determine locations for the movable pins.

Abstract: A processing device includes a plurality of non-volatile logic element array domains having two or more non-volatile logic element arrays to store 2006 a machine state of the processing device stored in a plurality of volatile store elements. Configuration bits are read to direct which non-volatile logic element array domains are enabled first and to direct an order in which the first enabled non-volatile logic element array domains are restored or backed up in response to entering a wakeup or backup mode. Configuration bits can be read to direct an order of and a parallelism of how individual non-volatile logic element arrays in a first enabled non-volatile logic element array domain are restored or backed up. The order of restoration or backing up can be controlled by instructions from non-volatile arrays of the first enabled of the plurality of non-volatile logic element array domains.

Abstract: An apparatus for updating a device, includes: a card configured to include a first device; a controller configured to acquire first circuit data from the card and to update a second device by using the first circuit data; and a storage unit configured to store, from the card, second circuit data for updating the first device, wherein the controller acquires the second circuit data stored in the storage unit and updates the first device by using the second circuit data.

Abstract: A plurality of writing transistors are connected in series, and a gate of a pass transistor, an input terminal of an inverter, or the like is directly or indirectly connected to each connection portion of the writing transistors. For example, a signal processing device includes first to third pass transistors, one semiconductor layer, and first to third wirings that overlap with the semiconductor layer and do not overlap with each other. Potentials of the first to third wirings can each change conductivities of at least portions of the semiconductor layer that overlap with the respective wirings. Gates of the first to third pass transistors are electrically connected to the semiconductor layer and are brought into a floating state depending on the conductivities of the portions of the semiconductor layer. Conduction between sources and drains of the pass transistors is controlled by potentials of the gates in the floating state.

Abstract: A method and system to perform physical synthesis in a chip design process using hierarchical wire-pin co-optimization are described. The method includes providing boundary conditions to each of a plurality of macros of the chip design from a unit level controller, the boundary conditions including initial pin locations and an indication of which of the pins are movable pins for each of the plurality of macros, performing macro-level physical synthesis at each of the plurality of macros, and providing feedback to the unit level controller based on the macro-level physical synthesis performed at each of the plurality of macros, the feedback including a proposed new location for the movable pins of each of the plurality of blocks. The method also includes performing hierarchical co-optimization at the unit level controller based on the feedback from each of the plurality of macros to determine locations for the movable pins.

Abstract: A method for controlling an electronic circuit by means of the first, second and third operating parameters, comprises: determining a range of variation of the third parameter for each value of the first parameter by varying the second parameter, said ranges being different; determining a target value of the third parameter; if the target value is within one of the ranges, operating the electronic circuit by setting the third parameter to the target value; and in the opposite case, selecting the two ranges framing the target value and operating the electronic circuit by consecutively bringing the third parameter into each one of the selected ranges.

Abstract: Techniques and mechanisms to provide common interface logic for multiple protocol engines to access physical layer circuitry at different times. In an embodiment, a state machine of an interface device is to participate in exchanges with physical layer resources on behalf of any of various protocol engines coupled to the interface device via different respective interfaces. Based on state transitions by the state machine, circuitry corresponding to a particular one of such interfaces may selectively send a clock signal for operation of a port controller attempting to access the physical layer circuitry. In some embodiments, multiple interface devices are configured to provide an hierarchical interface architecture for more than two port controllers that variously support at least two protocols.

Abstract: In a first mode, a control circuit generates a circuit design implementation with storage circuits in an integrated circuit by programming configuration memory bits via configuration resources. The storage circuits can be accessed for read and write operations during the execution of the circuit design implementation with the integrated circuit. In a second mode, the control circuit can perform read and write access operations at the storage circuits via configuration resources or via an interface circuit and interconnect resources that are allocated to the circuit design implementation. Typical applications for performing access operations at the storage circuits include fault injection and observation, statistical monitoring of the circuit design, initialization and distribution of certain signals including reset signals, event sampling, just to name a few.

Abstract: A device for generating a reference voltage includes a first non-volatile memory cell provided with a control-gate transistor and a reading transistor. The control-gate transistor includes a gate terminal, a body, a first conduction terminal and a second conduction terminal. The first conduction terminal and the second conduction terminal are connected together to form a control-gate terminal. The reading transistor includes a gate terminal that is connected to the gate terminal of the control-gate transistor to form a floating-gate terminal, a body, a third conduction terminal and a fourth conduction terminal. The device also includes a second, equivalent, memory cell. The source terminal of the first non-volatile memory cell and the source terminal of the second equivalent memory cell are connected together.

Abstract: A device is configured to obtain backlog information from a network device. The backlog information indicates a backlog of a queue included in the network device. The device obtains settings information for the network device. The settings information indicates a setting of the queue. The device determines an adjustment to the setting of the queue based on the backlog information and the settings information. The device provides adjustment information, indicating the adjustment to the setting of the queue, to the network device for the network to adjust the setting of the queue.

Abstract: A host system receives a description of a design under test (DUT) that includes multiple IP units and is to be emulated by an emulator. The host system compiles the description of the DUT, which includes synthesizing the description, partitioning the DUT, and mapping the partitions to FPGAs included in the emulator that will emulate the DUT. Each IP unit is part of a single partition or partitioned into multiple partitions and mapped to a different set of FPGAs. The host system identifies connections in the DUT between IP units. The host system designates one or more FPGAs of the emulator that have not been allocated to emulate IP units as interface FPGAs. The host system determines a route for each of the identified connections through one of the interface FPGAs. The connections are routed so that there are no direct connections between the sets of FPGAs of two IP units.

Abstract: Examples of techniques for enabling a field programmable device on demand are disclosed. In one example implementation according to aspects of the present disclosure, a method may include: determining, by a processing device, whether to enable a disabled field programmable device; responsive to determining to enable the disabled field programmable device, identifying, by the processing device, the field programmable device from a plurality of disabled FPDs; sending an authorization request to an authorization authority to request an authorization to enable the disabled field programmable device; responsive to receiving the authorization from the authorization authority, enabling the disabled field programmable device as an enabled field programmable device; loading computer readable instructions to the enabled field programmable device; and bringing the enabled field programmable device online.

Abstract: A technique for configuring an integrated circuit includes receiving configuration data from an external element with an interface circuit. The configuration data may include an identification field and an instruction for configuring a logic block. Configuration circuitry may be used to identify the logic block to be configured based on the identification field. A storage element in the identified logic block is configured by the configuration circuitry based on the instruction.

Abstract: Disclosed are methods and devices, among which is a device that includes a finite state machine lattice. The lattice may include a counter suitable for counting a number of times a programmable element in the lattice detects a condition. The counter may be configured to output in response to counting the condition was detected a certain number of times. For example, the counter may be configured to output in response to determining a condition was detected at least (or no more than) the certain number of times, determining the condition was detected exactly the certain number of times, or determining the condition was detected within a certain range of times. The counter may be coupled to other counters in the device for determining high-count operations and/or certain quantifiers.

Abstract: Embodiments of a near optimal configurable adder tree for arbitrary shaped 2D block sum of absolute differences (SAD) calculation engine are generally described herein. Other embodiments may be described and claimed. In some embodiments, a configurable two-dimensional adder tree architecture for computing a sum of absolute differences (SAD) for various block sizes up to 16 by 16 comprises a first stage of one-dimensional adder trees and a second stage of one-dimensional adder trees, wherein each one-dimensional adder tree comprises an input routing network, a plurality of adder units, and an output routing network.

Abstract: A method of booting a system on chip (SoC) includes using an on-chip MRAM located in the SoC, to store a boot software that includes a start-up software, boot loaders, and kernel and user-personalized information in an on-chip magnetic random access memory (MRAM) located in and residing on the same semiconductor as the SoC. The method further includes directly executing the boot software from the on-chip MRAM by the SoC and directly accessing the user-personalized information from the MRAM by the SoC.

Abstract: One embodiment relates to an integrated circuit including multiple PMA modules, a plurality of multiple-purpose PLLs, multiple reference clock signal inputs, and a programmable clock network. Another embodiment relates to a fracture-able PLL circuit. The fracture-able PLL circuit includes a first phase-locked loop circuit generating a first frequency output, a second phase-locked loop circuit; arranged to generate a second frequency output, and a plurality of shared output resources. Reconfigurable circuitry is arranged so that either of the first and second frequency outputs is receivable by each of the plurality of shared output resources. Another embodiment relates to an integrated circuit including a first strip of PLL circuits on a first side of the integrated circuit, and a second strip of PLL circuits on a second side of the integrated circuit which is opposite from the first side. Other embodiments and features are also disclosed.

Abstract: Analog-to-digital converters (ADCs) can have errors which can affect their performance. To improve the performance, many techniques have been used to compensate or correct for the errors. When the ADCs are being implemented with sub-micron technology, ADCs can be readily and easily equipped with an on-chip microprocessor for performing a variety of digital functions. The on-chip microprocessor and any suitable digital circuitry can implement functions for reducing those errors, enabling certain undesirable artifacts to be reduced, and providing a flexible platform for a highly configurable ADC. The on-chip microprocessor is particularly useful for a randomized time-interleaved ADC. Moreover, a randomly sampling ADC can be added in parallel to a main ADC for calibration purposes. Furthermore, the overall system can include an efficient implementation for correcting errors in an ADC.

Abstract: A write-assist memory includes a memory supply voltage and a column of SRAM cells that is controlled by a pair of bit lines, during a write operation. Additionally, the write-assist memory includes a write-assist unit that is coupled to the memory supply voltage and the column of SRAM cells and has a separable conductive line located between the pair of bit lines that provides a collapsible SRAM supply voltage to the column of SRAM cells based on a capacitive coupling of a control signal in the pair of bit lines, during the write operation. A method of operating a write-assist memory is also provided.

Abstract: An image signal modifying method is disclosed. In one aspect, the image signal modifying method includes inputting a gray level interval of a first dynamic capacitance compensation (DCC) lookup table to a current gray level which is a target in a previous image signal when it is overdriven (DTG) and 0 to a gray level of the previous image signal (PIG). The method also includes searching for a data value in an adaptive color correction (ACC) lookup table corresponding to a gray level equal to a numerical value of the DTG (ALT) and performing an algorithm based on the DTG, the ALT, and the gray level interval of the first DCC lookup table. The method further includes generating a second DCC lookup table based on the algorithm, and performing second DCC processing on the input image signal based on the second DCC lookup table.

Abstract: Asynchronous circuits and techniques are described for asynchronous processing without synchronization to a common clock. Two specific energy-efficient pipeline templates for high throughput asynchronous circuits are provided as examples based on single-track handshake protocol. Each pipeline contains multiple stages of logic. The handshake overhead is minimized by eliminating validity and neutrality detection logic gates for all input tokens as well as for all intermediate logic nodes. Both of these templates can pack significant amount of logic within each pipeline block, while still maintaining a fast cycle time.

Abstract: A method for generating a circuit description for a multi-die field-programmable gate array, FPGA, comprising a first FPGA die and at least one further FPGA die is described. The method is performed in an FPGA design tool and comprises automatically evaluating a first and a second partition of a partitioned circuit description, the partitions being associated with respective ones of the FPGA dies. At least one multiplexing element is inserted into the first partition and a corresponding de-multiplexing element is inserted into the second partition based on the automated evaluation.

Abstract: Technologies are generally described for systems and methods for reconfiguring a programmable circuit. An accelerator reconfiguration device may detect a trigger. The trigger may indicate that a command has been sent to a processor to switch from execution of a first virtual machine to a second virtual machine. In response to detecting the trigger, the reconfiguration device may identify a programmable circuit and program for the programmable circuit associated with the second virtual machine. The reconfiguration device may further generate a write command to write the program to the programmable circuit.

Abstract: Methods for control block size reduction of a controller of an integrated circuit (IC) device through intellectual property (IP) migration in the IC device are disclosed. A disclosed method includes receiving configuration data for the IC device and determining whether IP construction data is defined in the configuration data. The IP construction data contains instruction sets for implementing logical operations of a controller-based IP core in a core region of the IC device. Such data creates flexibility to configure the controller-based IP core in a core logic circuit as a soft IP core, when required. In this scenario, the controller-based IP core can be removed from the controller of the IC device during IC device fabrication. As a result, the footprint (e.g., area) of the controller of the IC device can be reduced, which subsequently increases cost-savings for the IC device fabrication.

Abstract: In an information processing system, plural information processing devices are mutually connected by an SMP connection mechanism. Each of the information processing devices includes a control device (FPGA) having a synchronous register that shows the state of a control signal of the information processing device and an internode communication access control unit that transmits first synchronous packets with the content of the synchronous register reflected to the other information processing devices at predetermined time intervals, receives second synchronous packets from the other information processing devices, and reflects the content of the received second synchronous packets on the synchronous register.

Abstract: Methods, systems, and devices for preventing disturb of untargeted memory cells during repeated access operations of target memory cells are described for a non-volatile memory array. Multiple memory cells may be in electronic communication with a common conductive line, and each memory cell may have an electrically non-linear selection component. Following an access operation (e.g., a read or write operation) of a target memory cell, untargeted memory cells may be discharged by applying a discharge voltage to the common conductive line. The discharge voltage may, for example, have a polarity opposite to the access voltage. In other examples, a delay may be instituted between access attempts in order to discharge the untargeted memory cells.

Abstract: Systems, circuits, and methods are disclosed for charge sharing. In one such example system, a first line is configured to be driven to a first voltage representative of data to be placed on the first line and then precharged to a first precharge voltage. A second line is configured to be driven to a second voltage representative of data to be placed on the second line and then precharged to a second precharge voltage. A charge sharing device is coupled between the first line and the second line. The charge sharing device is configured to selectively allow charge from the first line to flow to the second line after the first and second lines are driven to the respective first and second voltages representative of data to be placed on the respective lines.

Abstract: In an example, a LUT for a programmable integrated circuit (IC) includes a plurality of input terminals, and a cascading input coupled to at least one other LUT in the programmable IC. The LUT further includes LUT logic having a plurality of LUTs each coupled to a common set of the input terminals. The LUT further includes a plurality of multiplexers having inputs coupled to outputs of the plurality of LUTs, and an output multiplexer having inputs coupled to outputs of the plurality of multiplexers. The LUT further includes a plurality of cascading multiplexers each having an output coupled to a control input of a respective one of the plurality of multiplexers, each of the plurality of cascading multiplexers comprising a plurality of inputs, at least one of the plurality of inputs coupled to the cascading input.

Abstract: Systems and methods are provided to enhance the functionality of an integrated circuit. Such an integrated circuit may include a primary circuitry and an embedded programmable logic programmable to adjust the functionality of the primary circuitry. Specifically, the embedded programmable logic may be programmed to adjust the functionality of the primary circuitry to complement and/or support the functionality of another integrated circuit. Accordingly, the embedded programmable logic may be programmed with functions such as data/address manipulation functions, configuration/testing functions, computational functions, or the like.

Abstract: A processing device is provided. A cluster includes a plurality of groups of processing elements. A multi-word device is connected to the processing elements within the groups. Each processing element in a particular group is in communication with all other processing elements within the particular group, and only one of the processing elements within other groups in the cluster. Each processing element is limited to operations in which input bits can be processed and an output obtained without reference to other bits. The multi-word device is configured to cooperate with at least two other processing elements to perform processing that requires reference to other bits to obtain a result.

Abstract: A memory array has a NVM element with a plurality of FETs. A first set of FETs of the plurality of FETs is coupled to a bitline true of the memory array. The first set of FETs has a first channel width. A second set of FETs of the plurality of FETs is coupled to a bitline complement of the memory array. The second set of FETs has a second channel width. The first channel width is greater than the second channel width. The channel width disparity provides the NVM element of the unprogrammed memory array with a default state.

Abstract: A common boot sequence facility is provided that enables a control utility (e.g., operating system, control program, or other standalone tool, as examples) to be booted in a plurality of configurations without changing the boot sequence. An operating system or other control utility uses the common boot sequence to be able to be booted in either a first architecture configuration that initializes in one architecture, e.g., ESA/390 and then switches to, for instance, another architecture, e.g., z/Architecture, for processing; or in a second architectural configuration that initializes and processes in the another architecture, e.g., z/Architecture.

Abstract: A determination is made that a configuration architectural mode facility is installed in a computing environment that is configured for a plurality of architectural modes and has a defined power-on sequence that is to power-on the computing environment in one architectural mode of the plurality of architectural modes. Based on determining that the configuration architectural mode facility is installed, the computing environment is reconfigured to restrict use of the one architectural mode. The reconfiguring includes selecting a different power-on sequence to power-on the computing environment in another architectural mode of the plurality of architectural modes, wherein the another architectural mode is different from the one architectural mode, and executing the different power-on sequence to power-on the computing environment in the another architectural mode in place of the one architectural mode restricting use of the one architectural mode.

Abstract: A packet processing system having a barrel compactor that extracts a desired data subset from an input dataset (e.g. an incoming packet). The barrel compactor is able to selectively shift one or more of the input data units of the input dataset based on individual shift values for those data units. Additionally, in some embodiments one or more of the data units are able to be logically combined to produce a desired logical output unit.

Abstract: Systems and methods for generating and deploying integrated circuit (IC) applications are provided. Partial reconfiguration functionality of an IC may be used to build reconfigurable application platforms that enable application execution on the IC. These apps may include partial reconfiguration bitstreams that allow ease of access to programming without cumbersome compilation via a set of complex tools. The apps may be acquired via a purchasing website or other mechanism, where the bitstreams may be downloaded to the IC, thus increasing usability of the IC as well providing addition revenue streams.

Abstract: A method includes clearing configuration bits of a plurality of latches of an integrated circuit. The method also includes implementing an initialization routing pattern of the plurality of latches by configuring the configuration bits of the plurality of latches. The method further includes storing initialization data in a set of the plurality of latches based on the initialization routing pattern. The method includes clearing the configurations bit of the plurality of latches, wherein the initialization data remains stored in the set of the plurality of latches. The method also includes implementing a user-designed routing pattern of the plurality of latches by configuring the configuration bits of the plurality of latches.

Abstract: Various techniques are provided to implement user specified test registers locally on a PLD for use while the PLD is configured with a user design and tested. In one example, a machine-implemented method includes receiving, from an external test application, a data value at a programmable logic device (PLD) running configured user logic. The method also includes writing the data value into a test register of the PLD. The method also includes providing a control signal from the test register to the configured user logic in response to the data value. The method also includes switching operation of the configured user logic from a first test implementation to a second test implementation in response to the control signal.

Abstract: A computer-implemented method includes identifying an electronic circuit, which includes a plurality of circuit elements and is based on a circuit design. The circuit design includes structural information and logical information. The method generates a first verification model for the circuit design. The verification model includes a plurality of error report signal paths for each of the plurality of circuit elements. The method identifies a first circuit element output based on the plurality of error report signal paths. The method sets output for at least one of the first plurality of circuit elements to a fixed value. The method generates a second circuit element output based on the plurality of error report signal paths and setting output for at least one of the first plurality of circuit elements to a fixed value. The method determines a difference between the first circuit element output and the second circuit element output.

Abstract: A Field-Programmable Gate Array device is provided with programmable interconnect points in the form of interconnect circuits comprising one or more pass transistors, wherein at least some components of the interconnect circuits are implemented in the Back-End-Of-Line part of the Field-Programmable Gate Array device's production process. The memory element in an interconnect point is not produced as a Static Random Access Memory cell, but as a Dynamic Random Access Memory cell, requiring only a single select transistor and a storage capacitor for each memory element. The fabrication of at least the select transistor and the pass transistor involves the use of a thin film semiconductor layer, e.g., Indium Gallium Zinc Oxide, enabling production of transistors with low leakage in the Back-End-Of-Line.

Abstract: Different functional elements are all located on a same integrated circuit wherein at least one of the functional elements comprises a micro-controller. Configuration registers or configuration memory in the integrated circuit store configuration values loaded by the micro-controller. Connectors are configured to connect the integrated circuit to external signals A system level interconnect also located in the integrated circuit programmably connects together the different functional elements and different connectors according to the configuration values loaded into the configuration registers.