Abstract: A chip package includes a first integrated-circuit (IC) chip; a second integrated-circuit (IC) chip over the first integrated-circuit (IC) chip; a connector over the first integrated-circuit (IC) chip and on a same horizontal level as the second integrated-circuit (IC) chip, wherein the connector comprises a substrate over the first integrated-circuit (IC) chip and a plurality of through vias vertically extending through the substrate of the connector; a polymer layer over the first integrated-circuit (IC) chip, wherein the polymer layer has a portion between the second integrated-circuit (IC) chip and connector, wherein the polymer layer has a top surface coplanar with a top surface of the second integrated-circuit (IC) chip, a top surface of the substrate of the connector and a top surface of each of the plurality of through vias; and an interconnection scheme on the top surface of the polymer layer, the top surface of the second integrated-circuit (IC) chip, the top surface of the connector and the top sur

Abstract: A memory controller monitors memory command selected for dispatch to the memory and sends commands controlling a read clock state. A memory includes a read clock circuit and a mode register. The read clock circuit has an output for providing a hybrid read clock signal in response to a clock signal and a read clock mode signal. The mode register provides the read clock mode signal in response to a read clock mode, wherein the read clock circuit provides the hybrid read clock signal as a free-running clock signal that toggles continuously when the read clock mode is a first mode, and as a strobe signal that is active only in response to the memory receiving a read command when the read clock mode is a second mode.

Abstract: Provided are a dielectric thin film, an integrated device including the same, and a method of manufacturing the dielectric thin film. The dielectric thin film includes an oxide having a perovskite-type crystal structure represented by Formula 1 below and wherein the dielectric thin film comprises 0.3 at % or less of halogen ions or sulfur ions. A2-xB3-yO10-z??<Formula 1> In Formula 1, A, B, x, y, and z are disclosed in the specification.

Abstract: Significantly optimized multi-stage networks, useful in wide target applications, with VLSI layouts using only horizontal and vertical links to route large scale sub-integrated circuit blocks having inlet and outlet links, and laid out in an integrated circuit device in a two-dimensional grid arrangement of blocks are presented. The optimized multi-stage networks in each block employ several rings of stages of switches with inlet and outlet links of sub-integrated circuit blocks connecting to rings from either left-hand side only, or from right-hand side only, or from both left-hand side and right-hand side; and employ shuffle exchange links where outlet links of cross links from switches in a stage of a ring in one sub-integrated circuit block are connected to either inlet links of switches in the another stage of a ring in the same or another sub-integrated circuit block.

Abstract: A system and method for detecting the presence of a Bluetooth or Zigbee signal within a short period of time is disclosed. The signal identification circuit has two stages, a first stage that processes windows to determine whether noise is present, and a second stage that processes long windows to determine whether the signal is a particular lower-power network protocol. The signal identification circuit can be configured to detect Bluetooth at 1 Mbps, Bluetooth at 2 Mbps or Zigbee. The signal identification signal may be used to allow a lower-power network controller to coexist with a high duty cycle WiFi controller. The signal identification circuit may also be used for other functions, such as powering on a lower-power network controller, determining CCA, or determining which channel a packet is being transmitted on.

Abstract: A static random access memory (SRAM) includes fast SRAM bit cells and fast multiplexer circuits that are formed in a first row of fast cells in a hybrid standard cell architecture. Slow SRAM bit cells and slow multiplexer circuits are formed in a second row of slow cells. The slow multiplexer circuits provide a column output for the fast SRAM bit cells and the fast multiplexer circuits provide a column output for the slow SRAM bit cells. Thus, one SRAM column has fast bit cells and slow multiplexer stages while the adjacent SRAM column has slow bit cells and fast multiplexer stages to thereby provide an improved performance balance when reading the SRAM.

Abstract: There is provided an apparatus for receiving a request from a master to access an input address. Coarse grain access circuitry stores and provides a reference to an area of an output address space in dependence on the input address. One or more fine grain access circuits, each store and provide a reference to a sub-area in the area of the output address space in dependence on the input address. The apparatus forwards the request from the coarse grain access circuitry to one of the one fine grain access circuits in dependence on the input address.

Abstract: A computer-implemented method for programming an integrated circuit includes receiving a program design and determining one or more addition operations based on the program design. The method also includes performing geometric synthesis based on the one or more addition operations by determining a plurality of bits associated with the one or more addition operations and defining a plurality of counters that includes the plurality of bits. Furthermore, the method includes generating instructions configured to cause circuitry configured to perform the one or more addition operations to be implemented on the integrated circuit based on the plurality of counters. The circuitry includes first adder circuitry configured to add a portion of the plurality of bits and produce a carry-out value. The circuitry also includes second adder circuitry configured to determine a sum of a second portion of the plurality of bits and the carry-out value.

Abstract: A processing apparatus is described. The apparatus includes a plurality of processing cores, including a first processing core and a second processing core a first field programmable gate array (FPGA) coupled to the first processing core to accelerate execution of graphics workloads processed at the first processing core and a second FPGA coupled to the second processing core to accelerate execution of workloads processed at the second processing core.

Abstract: A multi-logic device system, an electronic engine controller, and a method of operating the multi-logic device system. The multi-logic device system includes a primary logic device which is more resilient to single event effects, and one or more secondary logic devices, each secondary logic device being powered by a respective power supply unit and being more susceptible to single event effects. The primary logic device is configured to run, for each secondary logic device, a respective watchdog timer. Each watchdog timer is restarted upon receipt of a restart signal from the respective secondary logic device. The primary logic device is also configured, in response to a watchdog timer timing out, to identify and reset the secondary logic device corresponding to the timed out watchdog timer.

Abstract: An n-number of input ports, a plurality of output ports equal to ?k=2n+1(k?1), and a plurality of switches selectively connecting the n input ports to the plurality of output ports. A combiner network comprising n?1 combiners is connected to the plurality of output ports and one input port is directly connected to an output port to provide n output ports of the combiner network. A second stage switching matrix comprising n input ports is connected to the n output ports of the combiner network for selectively connecting one of the n output ports of the combiner network to an output load.

Abstract: A one-time programmable memory device is provided in the invention. The one-time programmable memory device includes a one-time programmable memory and a memory controller. The one-time programmable memory includes a first block and a second block. The first block includes a plurality of initial address units and each initial address unit corresponds to a variable to record the storage address of its corresponding variable, and wherein the second block includes a plurality of storage units and each storage unit has a corresponding storage address. The memory controller is coupled to the one-time programmable memory. The memory controller allocates the storage address to the variable. The content of each variable is stored in the storage unit corresponding to the storage address corresponding to the variable. The number of initial address units is smaller than the number of storage units.

Abstract: Embodiments of the disclosure may be drawn to wireless afterloaders. Exemplary afterloaders may include a central processing unit, a first complex programmable logic device having a memory, a transceiver operably connected to the complex programmable logic device, wherein the transceiver is configured to wirelessly receive data from a second complex programmable logic device separate from the wireless afterloader, and a battery.

Abstract: Disclosed is data communication between a microcontroller and a source readout circuit, in which the clock circuit of a slave is not needed, and the size of a slave circuit and the amount of power consumed may be reduced.

Abstract: A system and method for soft locking on an ingress port of a networking device in a network, such as a network-on-chip (NoC). Once a soft lock is established, the port is given transmitting priority so long has the port has an available packet or packet parts that can make forward progress in the network. When the soft lock port's packet parts, which can make forward progress in the network, are not available, the networking device may choose another port. The system transmits packet parts from the other port until the soft locked port has packet parts available that can make forward progress in the network. Any arbitration scheme may be used to select the port that is soft locked and to select the other ports to transmit from when the soft locked port does not have packet parts that can make forward progress in the network. Once the packet (or all the packet parts) on the soft locked port has completed transmission, the soft lock of the soft locked port is released.

Abstract: There is provided a method for implementing an electronic card. The method can include providing the electronic card with a printed circuit board. The method further includes selecting one of a first side and a second side as a specified side on which only connection hardware is to be mounted. The first side is located at a first x-y plane and the second side is located at a second x-y plane, the first and second x-y planes being separated by a length equal to a thickness of the PCB. The first and second x-y planes are parallel.

Abstract: A semiconductor device of an embodiment includes a first electrode, a second electrode, a first metallic region provided between the first electrode and the second electrode and includes at least one metallic element selected from the group consisting of indium (In), gallium (Ga), zinc (Zn), aluminum (Al), magnesium (Mg), manganese (Mn), titanium (Ti), tungsten (W), molybdenum (Mo), and tin (Sn), a second metallic region provided between the first metallic region and the second electrode and includes the at least one metallic element, a semiconductor region provided between the first metallic region and the second metallic region and includes the at least one metallic element and oxygen (O), an insulating region provided between the first metallic region and the second metallic region and is surrounded by the semiconductor region, a gate electrode surrounding the semiconductor region, and a gate insulating layer provided between the semiconductor region and the gate electrode.

Abstract: A method is provided for automatically or semi-automatically analyzing process hazards and validating protection mechanisms for an industrial process. The method can involve establishing communication between a simulation tool and a process hazard analysis tool. The simulation tool simulates operation of the process according to a process model. The method can further involve creating, using the process hazard analysis tool, conditions for hazards in the process based on information learned about the industrial process from the simulation tool; for each of the hazards, simulating the hazards using the simulation tool and attempting to prevent the hazards using the process hazard analysis tool by introducing protective mechanism(s) to the process; and evaluating effectiveness of the introduced protective mechanisms for each of the hazards and creating safety requirements for the process based on the evaluated effectiveness.

Abstract: A data sequence including pieces of data having one attribute is transmitted with a data sequence including pieces of data having another attribute. An acquisition unit acquires a plurality of data pieces having attributes differing from each other. An addition unit, when connected with the server apparatus establishes, adds, to each piece of data included in each of a plurality of data sequences including different pieces of data of the plurality of data pieces acquired, an identifier identifies a data group wherein the data piece belongs, of a plurality of data groups, and is associated with the connection. A transmission unit transmits the plurality of data sequences where the identifier is added, to the server apparatus via the connection, by inserting, between data pieces included in one data sequence of the plurality of data sequences, a piece of data included in another data sequence of the plurality of data sequences.

Abstract: A method is provided for automatically or semi-automatically analyzing process hazards and validating protection mechanisms for an industrial process. The method can involve establishing communication between a simulation tool and a process hazard analysis tool. The simulation tool simulates operation of the process according to a process model. The method can further involve creating, using the process hazard analysis tool, conditions for hazards in the process based on information learned about the industrial process from the simulation tool; for each of the hazards, simulating the hazards using the simulation tool and attempting to prevent the hazards using the process hazard analysis tool by introducing protective mechanism(s) to the process; and evaluating effectiveness of the introduced protective mechanisms for each of the hazards and creating safety requirements for the process based on the evaluated effectiveness.

Abstract: An integrated circuit device may include programmable logic fabric disposed on a first integrated circuit die and having configuration memory. The integrated circuit device may also include a base die that may provide memory and/or operating supporting circuitry. The first die and the second die may be coupled using a high-speed parallel interface. The interface may employ microbumps. The first die and the second die may also include controllers for the interface.

Abstract: Apparatus and methods to cross-connect large numbers of fiber optic ports using a multi-tiered fiber interconnection system incorporating physical aggregation are disclosed. Robotic reconfiguration of multi-fiber trunk lines enables scalability and software management from hundreds of connections up to and including 100,000 connections. Examples of two-tiered automated cross-connect systems are described.

Abstract: A plurality of computing devices, in a set of computing devices, each perform one or more tasks. A program monitors the tasks performed on each of the computing devices and determines a usage pattern. Based on the usage pattern the program determines one or more programs available for one or more of the computing devices. The program outputs a recommendation to install one or more of the available programs on one or more of the computing devices.

Abstract: A N×M non-blocking switch matrix, where N and M are integers, includes an input stage having a plurality of m/2-way multiport switches, where quotient m/2 is a positive integer less than M, and an output stage having a plurality of n/2-way multiport switches, where quotient n/2 is a positive integer less than N. The switch matrix further includes a transfer stage having a plurality of transfer switches operatively connected between the input stage and output stage, and selectively applying outputs of the m/2-way multiport switches to inputs of the n/2-way multiport switches such that any given input to the m/2-way multiport switches is connectable to any given output of the n/2-way multiport switches.

Abstract: The camouflage technique described herein introduces programmed configuration inputs to Micro Netlists, creating Programmable Micro Netlists (PMNLs). PMNLs are a group of camouflaged and non-camouflaged cells that may be configured to perform one of several possible logic functions. They retain all the protective properties of non-programmable MNLs, but also allow for secure post-manufacture configuration of their aggregate logic function.

Abstract: An interface for a semiconductor device includes a master device and a plurality of slave devices. The interface includes a master interface and a slave interface. The master interface is implemented in the master device and includes a master bond pattern of master bonds arranged as a first array. The slave interface is implemented each slave device and includes a slave bond pattern of slave bonds arranged as a second array. The first array of the master bonds includes a first central row and first data rows in two parts being symmetric to the first central row. The second array of the slave bonds includes a second central row and second data rows in two parts being symmetric to the second central row. The first central row and the second central row are aligned in connection, and the first data rows are connected to the second data rows.

Abstract: Various techniques are disclosed herein for storing and managing master data in hierarchical data systems. Several related concepts, embodiments, and examples are disclosed, including techniques for incremental rationalization in a hierarchical data model, techniques for implementing governance pools in a hierarchical data model, techniques for application materialization in a hierarchical data model, techniques for data intersection mastering in a hierarchical data model, techniques for change request visualization in a hierarchical data model, and techniques for hierarchy preparation in a hierarchical data model.

Abstract: A signal transmission apparatus has several serially-connected signal distribution modules, wherein interfaces of two adjacent signal distribution modules are each interconnected by a signal bridge. The signal transmission apparatus also has at least one direct connection between two signal distribution modules, which is routed through all signal bridges arranged between the two adjacent signal distribution modules and interconnects the interfaces of the adjacent signal bridges. In addition, a signal transmission bus is routed through all signal bridges and via all interfaces. The interfaces of all signal distribution modules have an identical design and all signal bridges connect two interfaces in the same way.

Abstract: Described herein is a system and method for dynamically scaling a stream processing system (e.g., “exactly once” data stream processing system). Various parameter(s) (e.g., user-configurable capacity, real-time load metrics, and/or performance counters) can be used to dynamically scale in and/or scale out the “exactly once” stream processing system without system restart. Delay introduced by this scaling operation can be minimized by utilizing a combination of mutable process topology (which can dynamically assign certain parts of the system to a new host machine) and controllable streaming processor movement with checkpoints and the streaming protocol controlled recovery which still enforces the “exactly once” delivery metric.

Abstract: Switchboxes are especially used in integrated circuits with programmable logic (e.g. FPGAs). They are used to establish configurable signal paths between logic blocks. The present invention is based on the task to present a switchbox with a small number of multiplexers and configuration bits, which can both forward a signal in signal direction and can implement a change of direction. The task is solved by using switchboxes consisting of direction multiplexers and at least one direction change multiplexer. Thus the signal direction can be changed arbitrarily without increasing the size of the direction change multiplexers.

Abstract: A power grid of an integrated circuit (IC) is provided. The power grid includes a plurality of first power lines formed in a first metal layer, a plurality of second power lines formed in the first metal layer, a plurality of third power lines formed in a second metal layer and a plurality of fourth power lines formed in the second metal layer. The second power lines are parallel to the first power lines, and the first and second power lines are interlaced in the first metal layer. The third power lines are perpendicular to the first power lines. The fourth power lines are parallel to the third power lines, and the third and fourth power lines are interlaced in the second metal layer. A first power pitch between two adjacent third power lines is greater than a second power pitch between two adjacent fourth power lines.

Abstract: When a host computer determines that a firmware version to be loaded is higher than a firmware version of each chip to be loaded, the host computer sends a loading flag to the chips to be loaded to enable the chips to be loaded enters a loading mode. The host computer redefines multiple controllable physical connections between each chip to be loaded entering the loading mode and a master controller chip connected thereto so that they act as loading buses. Each chip to be loaded executes a loading process according to a frame period and a frame count to receive the load file completely and then executes the IAP command to program its ROM. When each chip to be loaded finishes the loading process, each chip to be loaded jumps out of the load mode, and the host computer restores the definitions of the plurality of controllable physical connections.

Abstract: A crossbar switch is disclosed having a first port, a second port, a third port, and a fourth port, the crossbar switch comprising: a first switching element coupled between the first port and the third port; a second switching element coupled between the first port and the fourth port; a third switching element coupled between the second port and the third port; and a fourth switching element coupled between the second port and the fourth port, wherein the first switching element, the second switching element, the third switching element, and the fourth switching element are configured to couple only one of the first port and the second port to the third port, at any given time.

Abstract: Method for creating gates and circuits for computing apparatus with greatly improved characteristics of size, weight, power consumption, reliability, environmental tolerance, radiation hardiness, and operational speed at reduced costs by using symbol transformer, is provided. The symbol transformer having at least a first multiplicity of symbol ports coupled to a first variety of symbols, and a second multiplicity of symbol ports coupled to a second variety of symbols, associates an arbitrary one or plurality of the first multiplicity of symbol ports to and with any one or any plurality of the second or other multiplicities of symbol ports. The symbols represent static, dynamic, or both type of variables, and are used to operations of reversible, irreversible, randomized and quantum gates, circuits, and apparatus. Examples of code-controlled symbol transformer circuits embodiments demonstrate amenability for down scaling and manufacturing in silicon and other main-line processings.

Abstract: An apparatus for measuring round-trip time of a test signal using a programmable logic device comprises a pattern generator generating a test signal and measuring a round-trip time of the test signal, a programmable logic device of which internal circuits are configured to transmit the test signal in a predetermined manner, and bidirectional bus lines connecting the pattern generator and the programmable logic device. The round-trip time of the test signal is measured by a time difference between a starting time at which the pattern generator outputs the test signal and an arrival time at which the test signal is fed back to the pattern generator.

Abstract: A processing apparatus is described. The apparatus includes a plurality of processing cores, including a first processing core and a second processing core a first field programmable gate array (FPGA) coupled to the first processing core to accelerate execution of graphics workloads processed at the first processing core and a second FPGA coupled to the second processing core to accelerate execution of workloads processed at the second processing core.

Abstract: Disclosed approaches for creating a circuit design involving a network-on-chip (NoC) include instantiating in a memory of a computer system logic blocks and logical NoC (LNoC) blocks. Each logic block specifies a function of the circuit design and is communicatively coupled to another logic block through an LNoC block. The LNoC blocks are aggregated into a traffic specification that specifies connections between ingress circuits and egress circuits of the NoC. The traffic specification is compiled into configuration parameters for circuits of the NoC, and the logic blocks are compiled into implementation data for the target IC by the computer processor. The target IC can then be configured with the configuration parameters and implementation data.

Abstract: VLSI layouts of generalized multi-stage and pyramid networks for broadcast, unicast and multicast connections are presented using only horizontal and vertical links with spacial locality exploitation. The VLSI layouts employ shuffle exchange links where outlet links of cross links from switches in a stage in one sub-integrated circuit block are connected to inlet links of switches in the succeeding stage in another sub-integrated circuit block so that said cross links are either vertical links or horizontal and vice versa. Furthermore the shuffle exchange links are employed between different sub-integrated circuit blocks so that spatially nearer sub-integrated circuit blocks are connected with shorter links compared to the shuffle exchange links between spatially farther sub-integrated circuit blocks. In one embodiment the sub-integrated circuit blocks are arranged in a hypercube arrangement in a two-dimensional plane.

Abstract: A method for designing an FPGA may include determining blocks required for each of a plurality of applications; determining a size of the FPGA accommodating the determined blocks for each of the plurality of applications; and laying out the determined blocks for each of the plurality of applications in a block array of the FPGA.

Abstract: The present disclosure provides a testing method and a testing system. The testing method is performed by at least one processor and includes the following operations: converting a circuit data of a scan test to a program, in which the program is configured to observe an untested part of a circuitry that is unable to be tested in the scan test; generating a waveform data associated with the untested part; generating a look-up table according to the program and a netlist file, in which the netlist file indicates the circuitry; and testing the untested part of the circuitry according to the waveform data and the look-up table.

Abstract: An apparatus includes a first processor that generates first control signals to control a first circuit to perform memory operations on memory cells. A first number of first physical signal lines delivers the first control signals to a conversion circuit. A second number of second physical signal lines delivers converted control signals to the first circuit. The conversion circuit is coupled by the first number of first physical signal lines to the first processor and by the second number of second physical signal lines to the first circuit. The conversion circuit converts the first control signals to the converted control signals, and outputs the converted control signals to the first circuit. The first number of first physical signal lines is less than the second number of second physical signal lines to reduce the first number of first physical signal lines coupled between the first processor and the first circuit.

Abstract: A method of controlling a flight device includes receiving, by a controller of the flight device, a control request from a target device for requesting a control of the flight device, receiving control data sent from the target device, and converting the control data into an executable instruction for controlling the flight device.

Abstract: A reconfigurable circuit comprising: crossbar switches; wires, each of which is coupled to one output port of one crossbar switch and input ports of the other crossbar switches; at least one inverter inserted on each wire for driving long-distance signal transfer, wherein one or less first inverter is inserted on the wire between two adjacent crossbar switches; one or two second inverters inserted between a crossbar switch input port and its connected wire.

Abstract: A programmable logic device including an asynchronous circuit is provided. The programmable logic device includes a lookup table, a first circuit, and a second circuit. The first circuit receives a first signal and a second signal. The second circuit sends a third signal. The first circuit sends a fourth signal and a fifth signal, when receiving the third signal. The fourth signal has the same logic as the first signal. The fifth signal has the same logic as the second signal. The lookup table sends a sixth signal and a seventh signal, when receiving the fourth signal and the fifth signal. The second circuit sends an eighth signal, when receiving the sixth signal and the seventh signal. The first circuit sends a ninth signal, when receiving the eighth signal. The lookup table includes a memory. The sixth signal and the seventh signal are generated from data stored in the memory.

Abstract: One example of a device includes a sensor, a memristor code comparator, and a controller. The sensor is to provide a sensor signal. The memristor code comparator is to compare the sensor signal to a reference signal. The controller is to determine a status of the sensor signal based on the comparison.

Abstract: A method for visualizing system models in a model management environment, which includes the steps of opening the system model in the model editor, receiving a user input for rescaling a block, determining a relative horizontal position and a relative vertical position for each port in the block, calculating a new absolute horizontal and vertical position of each port in the block based on the relative horizontal and vertical position and the new size preset for the block, and displaying the block and each port in the block.

Abstract: A weight cell including first and second bi-directional memory elements each configured to switch between a first resistance state and a second resistance state different than the first resistance state. A first input line is connected to a first terminal of the first bi-directional memory element, and a second input line is connected to the first terminal of the second bi-directional memory element. A first diode in forward bias connects the second terminal of the first bi-directional memory element to a first output line, a second diode in reverse bias connects the second terminal of the second bi-directional memory element to a second output line, a third diode in reverse bias connects the second terminal of the first bi-directional memory element to the second output line, and a fourth diode in forward bias connects the second terminal of the second bi-directional memory element to the first output line.

Abstract: A system comprises a pair of configurable logic blocks (CLBs) placed adjacent to each other wherein each of the CLBs includes a plurality of configurable logic elements. A plurality sets of inodes are configured to accept signals to and/or from the CLBs, wherein a first set of inodes is positioned to the left of the adjacent CLBs and a second set of inodes is positioned to the right of the adjacent CLBs. A plurality of bnodes are embedded in the middle of the adjacent CLBs, wherein each bnode is configured to establish a first connection between the bnode and one of the first set of inodes on the left of the CLBs and a second connection between the bnode and one of the second set of inodes on the right of the CLBs. Both the first and second routing connections are localized within the pair of adjacent CLBs.

Abstract: An integrated circuit comprising an FPGA including programmable/configurable logic circuitry having a periphery, wherein resources (e.g., memory (e.g., high-speed local RAM), one or more busses, and/or circuitry external to the FPGA (e.g., a processor, a controller and/or system/external memory), is/are disposed outside the periphery of the programmable/configurable logic circuitry which includes a plurality of logic tiles, wherein at least one logic tile is located completely within the interior of the periphery and wherein each logic tile of the array of logic tiles includes a plurality of I/Os located on the perimeter of the logic tile wherein a first portion of the I/Os are located on a perimeter of the logic tile that is interior to the periphery, and the first portion of I/Os of each logic tile of the plurality of the logic tiles are directly connected to the bus to provide communication between the resources and the logic tiles.

Abstract: A semiconductor integrated circuit includes: a main-interconnect to which supply voltage or reference voltage is applied; a plurality of sub-interconnects; a plurality of circuit cells configured to be connected to the plurality of sub-interconnects; a power supply switch cell configured to control, in accordance with an input control signal, connection and disconnection between the main-interconnect and the sub-interconnect to which a predetermined one of the circuit cells is connected, of the plurality of sub-interconnects; and an auxiliary interconnect configured to connect the plurality of sub-interconnects to each other.