Significant Integrated Structure, Layout, Or Layout Interconnections Patents (Class 326/41)
  • Patent number: 10686447
    Abstract: An integrated circuit comprising an FPGA including programmable/configurable logic circuitry having a periphery, wherein resources (e.g., memory (e.g., high-speed local RAM), one or more busses, and/or circuitry external to the FPGA (e.g., a processor, a controller and/or system/external memory), is/are disposed outside the periphery of the programmable/configurable logic circuitry which includes a plurality of logic tiles, wherein at least one logic tile is located completely within the interior of the periphery and wherein each logic tile of the array of logic tiles includes a plurality of I/Os located on the perimeter of the logic tile wherein a first portion of the I/Os are located on a perimeter of the logic tile that is interior to the periphery, and the first portion of I/Os of each logic tile of the plurality of the logic tiles are directly connected to the bus to provide communication between the resources and the logic tiles.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: June 16, 2020
    Assignee: Flex Logix Technologies, Inc.
    Inventors: Cheng C. Wang, Anthony Kozaczuk, Geoffrey R. Tate
  • Patent number: 10672709
    Abstract: A power grid of an integrated circuit (IC) is provided. The power grid includes a plurality of first power lines formed in a first metal layer, a plurality of second power lines formed in the first metal layer and parallel to the first power lines, a plurality of third power lines formed in a second metal layer, and a plurality of fourth power lines formed in the second metal layer and parallel to the third power lines. The first and second power lines are interlaced in the first metal layer. The third and fourth power lines are interlaced in the second metal layer. Distances from the individual first power line to the two adjacent second power lines are the same, and distances from the individual third power line to the two adjacent fourth power lines are different.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: June 2, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Hiranmay Biswas, Kuo-Nan Yang, Chung-Hsing Wang
  • Patent number: 10664565
    Abstract: A method (of expanding a set of standard cells which comprise a library, the library being stored on a non-transitory computer-readable medium) includes: selecting one ad hoc group amongst ad hoc groups of elementary standard cells which are recurrent resulting in a selected group such that the elementary standard cells in the selected group having connections so as to represent a corresponding logic circuit, each elementary standard cell representing a logic gate, and the selected group corresponding providing a selected logical function which is representable correspondingly as a selected Boolean expression; generating, in correspondence to the selected group, one or more macro standard cells; and adding the one or more macro standard cells to, and thereby expanding, the set of standard cells; and wherein at least one aspect of the method is executed by a processor of a computer.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: May 26, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Lin Liu, Sheng-Hsiung Chen, Jerry Chang-Jui Kao, Fong-Yuan Chang, Lee-Chung Lu, Shang-Chih Hsieh, Wei-Hsiang Ma
  • Patent number: 10666261
    Abstract: Systems and methods related to multi-die integrated circuits that may include dies having high-speed core interconnects. The high-speed core interconnects may be used to directly connect two adjacent dies.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: May 26, 2020
    Assignee: Intel Corporation
    Inventors: Lai Guan Tang, Ankireddy Nalamalpu, Dheeraj Subbareddy
  • Patent number: 10666262
    Abstract: A programmable array logic includes a plurality of first signal lines, a plurality of second signal lines coupled to input terminals of a plurality of programmable AND gates, a plurality of first control units coupled to the first signal lines and second signal lines, a plurality of third signal lines coupled to output terminals of the programmable AND gates, a plurality of fourth signal lines coupled to input terminals of a plurality of programmable OR gates, and a plurality of second control units coupled to the third signal lines and the fourth signal lines. Each of the first control units has at least a first resistive memory for setting voltage level relationship between the first signal lines and the second signal lines. Each of second control units has a second resistive memory for setting voltage level relationship between the third signal lines and the fourth signal lines.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: May 26, 2020
    Assignee: Nuvoton Technology Corporation
    Inventor: Cheng-Chih Wang
  • Patent number: 10659052
    Abstract: Devices and methods for reconfiguring a programmable fabric include identifying resources in a programmable fabric of the programmable device as belonging to a partition. Reconfiguring the programmable fabric also includes creating a mask for the partition that indicates that the identified resources belong to the partition. Reconfiguring the partition also includes reconfiguring resources, via a configuration controller, in programmable fabric associated with the partition using the mask without changing resources associated with other partitions in the programmable fabric.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: May 19, 2020
    Assignee: Intel Corporation
    Inventors: Sean R. Atsatt, Andrew Draper
  • Patent number: 10630269
    Abstract: Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a programmable logic device (PLD) includes a plurality of programmable logic blocks (PLBs) and at least first and second logic cells within at least one of the PLBs, where each logic cell includes a lookup table (LUT) and associated mode logic configured to receive a LUT output signal from the LUT. The associated mode logic is configured to use a single physical signal output to provide a logic cell output signal corresponding to a selected logic function operational mode, ripple arithmetic operational mode, or extended logic function operational mode for each logic cell.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: April 21, 2020
    Assignee: Lattice Semiconductor Corporation
    Inventors: Brad Sharpe-Geisler, Senani Gunaratna, Ting Yew
  • Patent number: 10608642
    Abstract: A field-programmable-gate-array (FPGA) integrated-circuit (IC) chip configured to perform a logic function based on a look-up table (LUT), includes: multiple non-volatile memory cells therein configured to store multiple resulting values of the look-up table (LUT); and a programmable logic block therein having multiple static-random-access-memory (SRAM) cells configured to store the resulting values passed from the non-volatile memory cells, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values stored in the static-random-access-memory (SRAM) cells into its output.
    Type: Grant
    Filed: January 21, 2019
    Date of Patent: March 31, 2020
    Assignee: iCometrue Company Ltd.
    Inventors: Jin-Yuan Lee, Mou-Shiung Lin
  • Patent number: 10591543
    Abstract: Provided are a test board and a test system for efficiently testing a semiconductor package, and a manufacturing method for the semiconductor package using the same. A test apparatus includes a field programmable gate array (FPGA) configured to output a first data signal to be transmitted to the semiconductor device and a second data signal to be transmitted to the semiconductor device and a memory configured to store a test result. The FPGA includes a first input/output block configured to output the first data signal, a second input/output block configured to output the second data signal, a serializer/deserializer (SerDes) circuit configured to generate a strobe signal, and a skew calibration input/output block configured to receive the first data signal from the first input/output block, the second data signal from the second input/output block, and the strobe signal from the SerDes circuit.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: March 17, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joo-sung Yun, Soon-il Kwon, Byeong-min Yu
  • Patent number: 10578799
    Abstract: Disclosed herein are designs, structures and techniques for advanced packaging of multi-function photonic integrated circuits that allow such high-performance multi-function photonic integrated circuits to be co-packaged with a high-performance multi-function ASIC thereby significantly reducing strenuous interconnect challenges and lowering costs, power and size of the overall devices.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: March 3, 2020
    Assignee: Acaia Communications
    Inventors: Christopher Doerr, Eric Swanson, Diedrik Vermeulen, Saeid Azemati, Jon Stahl
  • Patent number: 10574237
    Abstract: An application specific integrated circuit (ASIC) and a method for its design and fabrication is disclosed. In one embodiment, the camouflaged application specific integrated circuit (ASIC), comprises a plurality of interconnected functional logic cells that together perform one or more ASIC logical functions, wherein the functional logic cells comprise a camouflage cell including: a source region of a first conductivity type, a drain region of the first conductivity type, and a camouflage region of a second conductivity type disposed between the source region and the drain region. The camouflage region renders the camouflage cell always off in a first camouflage cell configuration and always on in a second camouflage cell configuration having a planar layout substantially indistinguishable from the first configuration.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: February 25, 2020
    Assignee: VERIMATRIX
    Inventors: Ronald P. Cocchi, Lap Wai Chow, James P. Baukus, Bryan J. Wang
  • Patent number: 10566301
    Abstract: A reconfigured semiconductor logic device includes a semiconductor logic device comprising a plurality of input/output (I/O) pads formed on an active surface thereof and a redistribution layer. The redistribution layer comprises an insulating layer formed atop the active surface of the semiconductor logic device such that the insulating layer does not extend beyond an outer perimeter of the active surface and a patterned conductive wiring layer positioned above the insulating layer. The patterned conductive wiring layer includes a plurality of terminal buses formed on a top surface of the insulating layer. Each terminal bus of the plurality of terminal buses is electrically coupled to multiple I/O pads of the plurality of I/O pads through vias formed in the insulating layer.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: February 18, 2020
    Assignee: General Electric Company
    Inventors: Raymond Albert Fillion, Kaustubh Ravindra Nagarkar
  • Patent number: 10534625
    Abstract: Disclosed herein is an apparatus and method for emulating hardware. The apparatus includes a data array configured to store input data for an emulation cycle and a carry chain coupled to the data array receives one or more inputs from the data array. The carry chain is configured to generate output data in response to performing an arithmetic operation by a set of configurable logic gates using the one or more inputs in a pre-determined number of clock cycles. One or more processors are coupled to the carry chain and the data array, and are configured to emulate a logic gate function using at least the input data from the data array or the output data from the carry chain.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: January 14, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventor: Beshara Elmufdi
  • Patent number: 10528513
    Abstract: An integrated circuit comprises programmable resources; a plurality of hard blocks; and a programmable connector coupled to the programmable resources, the plurality of hard blocks; wherein the programmable connector is configurable to route signals between a first hard block and a second hard block in a first mode of operation and to route signals between the first hard and the programmable resources in a second mode of operation.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: January 7, 2020
    Assignee: Xilinx, Inc.
    Inventors: Chee Chong Chan, Warren E. Cory, Jason R. Bergendahl
  • Patent number: 10511479
    Abstract: A service deployment method and a network functions acceleration platform are provided. The method includes: when an FPGA is powered on, loading, by the FPGA, an FPGA framework file, so that the FPGA includes M partial reconfigurable PR areas, a configuration module, and a data flow forwarding module; when receiving a service configuration instruction, generating, by a physical machine, a VM, and selecting at least one PR area from the M PR areas to establish a correspondence with the VM; performing, by a configuration module, service resource configuration on the selected PR area according to a PR configuration resource, so that the selected PR area has a service processing capability; adding, by the configuration module, a forwarding entry corresponding to the PR area in a forwarding flow table, so that the data flow forwarding module forwards a received network packet to the corresponding PR area.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: December 17, 2019
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Yuming Xie, Liang Zhang, Jun Wu, Fan Yang
  • Patent number: 10505522
    Abstract: A standard cell layout for a flip-flop includes a flip-flop circuit and an initialization circuit. Metallization levels over the standard cell layout support circuit interconnections. At least one metallization level is provided for metal programming of an initialization configuration of the flip-flop. The at least one metallization level may have: a first wiring layout for interconnecting the initialization circuit to the flip-flop circuit for configuration programming of the flip-flop as an initialization in reset device (assertion of an initialization signal causing the flip-flop data output to be reset), or a second wiring layout for interconnecting the initialization circuit to the flip-flop circuit for configuration programming of the flip-flop as an initialization in set device (assertion of the initialization signal causing the flip-flop data output to be set).
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: December 10, 2019
    Assignee: STMicroelectronics SA
    Inventors: Sylvain Engels, Alain Aurand, Etienne Maurin
  • Patent number: 10489324
    Abstract: Systems and methods for port management are disclosed. In one aspect, the system may consolidate port management functions as well as power conversion, protection features, and signal conditioning circuitry into a single integrated circuit (IC) for a device without a battery. Further exemplary aspects allow for arbitration between ports to handle power supply versus power sink functions. Still further exemplary aspects provide an indication when a weak power source is coupled to the computing device to alert a user that the weak power source may not provide sufficient power for full operation. Such consolidated functionality allows a single form factor to be used for all ports whether the ports are used as a power port or an output port. Further, such consolidated functionality helps mitigate possible damage caused by improper activity.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: November 26, 2019
    Assignee: Qualcomm Incorporated
    Inventors: Christian Gregory Sporck, Georgios Konstantinos Paparrizos
  • Patent number: 10409604
    Abstract: An apparatus and method are provided for performing multiply-and-accumulate-products (MAP) operations. The apparatus has processing circuitry for performing data processing, the processing circuitry including an adder array having a plurality of adders for accumulating partial products produced from input operands. An instruction decoder is provided that is responsive to a MAP instruction specifying a first J-bit operand and a second K-bit operand, to control the processing circuitry to enable performance of a number of MAP operations, where the number is dependent on a parameter. For each performed MAP operation, the processing circuitry is arranged to generate a corresponding result element representing a sum of respective E×F products of E-bit portions within an X-bit segment of the first operand with F-bit portions within a Y-bit segment of the second operand, where E<X?J and F<Y?K.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: September 10, 2019
    Assignee: ARM Limited
    Inventors: Michael Alexander Kennedy, Neil Burgess
  • Patent number: 10402366
    Abstract: Briefly, an efficient and scalable processor device is disclosed that uses multi-value voltages for operands, results, and signaling. An array of cells is arranged in rows and columns, and one or more multi-value operands are used to select a cell from the array. A row driver may be used to select a row of cells, and a column driver is used to select a particular column from the selected row. Once a particular cell is selected, a voltage value associated with that cell is passed as an output, which is typically a multi-value result. The multi-value processor is constructed such that the row driver and column driver can be substantially identical, and have a structure that enables significant circuit reuse, provides substantial reduction in size for a circuit layout, has increased layout symmetry, simple scalability, and advantageous power conservation.
    Type: Grant
    Filed: October 25, 2011
    Date of Patent: September 3, 2019
    Inventor: Benjamin J. Cooper
  • Patent number: 10404255
    Abstract: A device for automatic configuration of a semiconductor integrated circuit includes a memory that stores circuit data representing a structure of a logic circuit including a first clock gating circuit, and a processor. The processor is configured to retrieve the circuit data from the memory, determine first and second logical elements from each of which an enable signal is output to the first clock gating circuit, calculate a delay time of each of the first and second logical elements, separate the first and second logical elements on the basis of the calculated delay time, and add a second clock gating circuit for the first logical element after separating the first and second logical elements.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: September 3, 2019
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Hironori Sato, Hiroaki Muraoka
  • Patent number: 10396800
    Abstract: A memory block integrated in a programmable logic device (PLD) is disclosed. The memory block includes: one or more lookup tables storing pre-populated data. The PLD includes a programmable fabric and a signal wrapper configured to provide signals between the memory block and the programmable fabric. The memory block is configured to receive input signals from the signal wrapper and generate output signals to the signal wrapper by looking up the pre-populated data corresponding to the input signals. The pre-populated data stored in the one or more lookup tables are programmably changed by programming a plurality of parameters of the programmable fabric and loading the pre-populated data to the one or more lookup tables via the signal wrapper.
    Type: Grant
    Filed: October 9, 2018
    Date of Patent: August 27, 2019
    Assignee: AnDAPT, Inc.
    Inventors: Kapil Shankar, Herman Cheung, John Birkner, Patrick J. Crotty
  • Patent number: 10384447
    Abstract: In a liquid ejection head, an ejection unit of a channel member includes an ejection hole, a pressurizing chamber connected to the ejection hole, a first channel and a second channel each connecting the pressurizing chamber and a first common channel, and a third channel connecting the pressurizing chamber and a second common channel. The first common channel, in the channel direction, includes a plurality of first portions, and a plurality of second portions each located between each two of the plurality of first portions and having smaller cross-sectional areas than those of the first portions in front and back of the same. In each of the plurality of ejection units, the first channel and the second channel are individually connected to two positions in the first common channel which sandwich at least one of the second portions between them.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: August 20, 2019
    Assignee: Kyocera Corporation
    Inventors: Naoki Kobayashi, Hiroyuki Kawamura, Wataru Ikeuchi
  • Patent number: 10371802
    Abstract: Systems and methods for performing optical distance measurement are provided. In one aspect, a system for measuring a distance to an object comprises a light emitter configured to emit an outbound light pulse, and a light sensor configured to receive a returning light pulse reflected from the object and output an analog pulse signal representing the returning light pulse. The system also comprises a field-programmable gate array (FPGA) coupled to the light sensor. The FPGA is configured to convert the analog pulse signal to a plurality of digital signal values, and generate a plurality of time measurements corresponding to the plurality of digital signal values. The system also comprises a controller configured to calculate the distance to the object based on the plurality of digital signal values and the plurality of time measurements.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: August 6, 2019
    Assignee: SZ DJI Technology Co., Ltd.
    Inventors: Xiang Liu, Mingming Gao, Xiaoping Hong, Di Wu
  • Patent number: 10331837
    Abstract: Rendering a graphical representation of an integrated circuit can include determining, using a processor, a tile of a device model at least partially within a viewport, determining, using the processor, an owning tile having a fly-over wire passing over the tile, determining, using the processor, a predetermined shape of the fly-over wire, and drawing, using the processor, the fly-over wire within the viewport based upon the shape.
    Type: Grant
    Filed: November 17, 2016
    Date of Patent: June 25, 2019
    Assignee: XILINX, INC.
    Inventors: Jennifer D. McEwen, Ian L. McEwen, Chong M. Lee, Bart Reynolds
  • Patent number: 10318468
    Abstract: An FPGA-based interface signal remapping method, relates to the technical field of nuclear power system, and solves the technical problems of poor reliability, readability and debuggability in the prior art. The method comprises dividing an internal programmable logic of an FPGA chip into two independent modules, with one module being an I/O module and the other module being a Core module, using the I/O module to process signal excursion occurring when an external signal is input to or output from the FPGA chip, signal collision caused by line multiplexing, metastable state in a data transmission process, and a data transmission error between asynchronous clock domains, using the Core module to implement logical processing and computing; and introducing a master clock signal outside the FPGA chip into the FPGA chip through a global clock pin of the FPGA chip. The method provided in the invention is suitable for a nuclear power protection system platform.
    Type: Grant
    Filed: January 4, 2016
    Date of Patent: June 11, 2019
    Assignee: STATE NUCLEAR POWER AUTOMATION SYSTEM ENGINEERING CO., LTD.
    Inventors: Jian Zhang, Qunxing Jiang, Xiaokai Wang
  • Patent number: 10310868
    Abstract: A processor includes a core within a package and layers of programmable fabric within the same package as the core. The core includes logic to execute an instruction by loading a configuration file to one of the layers of programmable fabric. The configuration is to program an identified execution functionality. The execution functionality is to execute at least part of the instruction.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: June 4, 2019
    Assignee: Intel Corporation
    Inventor: Leo A. Linsky
  • Patent number: 10236888
    Abstract: Disclosed are a circuit and method for implementing a switching function. In an embodiment, the circuit includes a first logic circuit, a second logic circuit, and a Correlated electron switch (CES) element. The CES element is configurable to have a non-volatile state to enable or disable an electrical connection between the first logic circuit and the second logic circuit.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: March 19, 2019
    Assignee: ARM Ltd.
    Inventors: Vikas Chandra, Robert Campbell Aitken
  • Patent number: 10230375
    Abstract: The present invention discloses a configurable gate array comprising three-dimensional printed memory (3D-P). It comprises an array of configurable computing elements, an array of configurable logic elements and a plurality of configurable interconnects. Each configurable computing element can selectively realize a basic function in a math library. It comprises a plurality of 3D-P arrays storing the look-up tables (LUT) for the basic functions in the math library.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: March 12, 2019
    Assignees: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao Zhang
  • Patent number: 10211833
    Abstract: An integrated circuit includes a circuit block, a storage circuit that stores a static power gating control signal, a logic gate circuit that receives a dynamic power gating control signal and the static power gating control signal from the storage circuit, and a transistor coupled between the circuit block and a supply node at a supply voltage. A conductive state of the transistor is determined by an output signal of the logic gate circuit. The transistor is turned off to provide power gating to the circuit block in response to a change in the output signal of the logic gate circuit that is caused by the static power gating control signal or by the dynamic power gating control signal.
    Type: Grant
    Filed: September 20, 2016
    Date of Patent: February 19, 2019
    Assignee: Altera Corporation
    Inventor: Lai Guan Tang
  • Patent number: 10211836
    Abstract: The present invention discloses a configurable computing array based on three-dimensional printed memory (3D-P). It comprises an array of configurable computing elements, an array of configurable logic elements and a plurality of configurable interconnects. Each configurable computing element can selectively realize a basic function in a math library. It comprises a plurality of 3D-P arrays storing the look-up tables (LUT) for the basic functions in the math library.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: February 19, 2019
    Assignees: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao Zhang
  • Patent number: 10186305
    Abstract: Systems and methods are provided herein for implementing a programmable integrated circuit device that enables high-speed FPGA boot-up through a significant reduction of configuration time. By enabling high-speed FPGA boot-up, the programmable integrated circuit device will be able to accommodate applications that require faster boot-up time than conventional programmable integrated circuit devices are able to accommodate. In order to enable high-speed boot-up, dedicated address registers are implemented for each data line segment of a data line, which in turn significantly reduces configuration random access memory (CRAM) write time (e.g., by a factor of at least two).
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: January 22, 2019
    Assignee: ALTERA CORPORATION
    Inventors: Jun Pin Tan, Kiun Kiet Jong, Lai Pheng Tan
  • Patent number: 10171169
    Abstract: A software programmable optical transceiver includes one or more Field Programmable Gate Arrays (FPGAs); and an electro-optical front end communicatively coupled to the one or more FPGAs, wherein the electro-optical front end comprises a transmitter and a receiver, wherein the transmitter is adapted to transmit a transmit signal from the one or more FPGAs and the receiver is adapted to receive a receive signal and provide to the one or more FPGAs, wherein one or more applications are utilized to dynamically configure the one or more FPGAs for digital functionality to operate the software programmable optical transceiver in an associated mode. The one or more applications are loaded as needed to configure the software programmable optical transceiver in the associated mode, without requiring pre-programmed hardware in the software programmable optical transceiver for operation in a plurality of operating modes.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: January 1, 2019
    Assignee: Ciena Corporation
    Inventors: Michael Y. Frankel, Stephen B. Alexander
  • Patent number: 10156603
    Abstract: The present invention provides an apparatus for adding jitters to the edges of a pulse sequence, the pulse sequence which edges is needed to adding jitters to is sent to a first edge-pulse converter and a second edge-pulse converter respectively, and be converted into a rising edge pulse signal and a falling edge pulse signal. The rising edge pulse signal and the falling edge pulse signal are delayed by different fixed times, and for the edge pulse signal which is delayed shorter, it should be further delayed by a programmable delay circuit, thus the edge to which the jitter is added can be adjusted to a leading position or a lagging position according to a jitter data read out from a jitter data storage, so the synthesized pulse sequence with jitter-added edges can be used as test signal for jitter tolerance measurement.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: December 18, 2018
    Assignee: UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA
    Inventors: Zaiming Fu, Hanglin Liu, Jianguo Huang, Yijiu Zhao
  • Patent number: 10158525
    Abstract: A method performed by a radio base station, the method including determining a link configuration of a first communication link, the first communication link being a current communication link between a first radio equipment control (REC) device and a radio equipment (RE) device. The method further including in response to determining that a second communication link between a second REC device and the RE device is to replace the current communication link, instead of the first communication link, establishing, by the second REC device, the second communication link based on the determined link configuration of the first communication link.
    Type: Grant
    Filed: August 12, 2015
    Date of Patent: December 18, 2018
    Assignee: NXP USA, Inc.
    Inventors: Roi Menahem Shor, Avraham Horn, Shay Shpritz
  • Patent number: 10135447
    Abstract: A memory block integrated in a programmable logic device (PLD) is disclosed. The memory block includes: one or more lookup tables storing pre-populated data. The PLD includes a programmable fabric and a signal wrapper configured to provide signals between the memory block and the programmable fabric. The memory block is configured to receive input signals from the signal wrapper and generate output signals to the signal wrapper by looking up the pre-populated data corresponding to the input signals. The pre-populated data stored in the one or more lookup tables are programmably changed by programming a plurality of parameters of the programmable fabric and loading the pre-populated data to the one or more lookup tables via the signal wrapper.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: November 20, 2018
    Assignee: ANDAPT, INC.
    Inventors: Kapil Shankar, Herman Cheung, John Birkner, Patrick J. Crotty
  • Patent number: 10121006
    Abstract: A system and methods are disclosed for securely booting a processing system using a three step secure booting process. Several embodiments are presented, wherein upon power-on-reset, the first boot step uses a secure boot device comprising of a programmable device or an FPGA which boots up first, validates its configuration file and then validates the processor(s) configuration data before presenting the configuration data to the processor(s). This enables validation of ‘pre-boot’ information, such as the Reset Control Word and pre-boot processor configuration data. The second and third boot steps validate the internal secure boot code and external boot code respectively using one or more of secure validation techniques, such as encryption/decryption, Key mechanisms, privilege checking, pointer hashing or signature correlation schemes.
    Type: Grant
    Filed: December 5, 2016
    Date of Patent: November 6, 2018
    Assignee: Raytheon Company
    Inventors: Brandon Woolley, Norman Cramer, Brian McFarland, Matthew Hammond
  • Patent number: 10068047
    Abstract: A method of designing an integrated circuit using a computer implemented circuit design application is disclosed. The method may involve receiving a user-provided value specifying a number of output components to be connected to an input component in the integrated circuit, connecting the input component to each output component of the number of output components in the integrated circuit using computer-implemented fan-out circuit blocks. In addition, generating a circuit design such that one of the fan-out circuit blocks is replaced in the circuit design with connecting components according to a set of parameters.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: September 4, 2018
    Assignee: Altera Corporation
    Inventor: Simon Finn
  • Patent number: 10068045
    Abstract: A programmable logic design is generated for a programmable logic device (PLD) containing configurable logic blocks (CLBs) each having a plurality of multiplexers and look-up-table (LUT) circuits. A first subset of multiplexers are identified from the plurality of multiplexers based upon an analysis of design definitions for input signals of the plurality of multiplexers. The first subset of multiplexers are transformed into LUT logic. Configuration data is generated that is designed to be loaded into the PLD to configure the CLBs. The configuration data includes the LUT logic.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: September 4, 2018
    Assignee: XILINX, INC.
    Inventors: Sabyasachi Das, Chiwei Huang
  • Patent number: 10031765
    Abstract: A processor includes a core within a package and layers of programmable fabric within the same package as the core. The core includes logic to execute an instruction by loading a configuration file to one of the layers of programmable fabric. The configuration is to program an identified execution functionality. The execution functionality is to execute at least part of the instruction.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: July 24, 2018
    Assignee: Intel Corporation
    Inventor: Leo A. Linsky
  • Patent number: 10020812
    Abstract: An integrated circuit includes first and second circuit blocks. The first circuit block includes a first storage circuit. A first data path passes through the first storage circuit and a first multiplexer circuit to a first input of a first logic circuit. The first multiplexer circuit is coupled to the first storage circuit. A second storage circuit is coupled between the first storage circuit and the first multiplexer circuit. A second data path passes through the second circuit block to a second input of the first logic circuit. The first multiplexer circuit is configurable to bypass or to couple the second storage circuit in the first data path based on an indication of whether a redundant third circuit block is coupled between the first and second circuit blocks in at least one of the first data path or the second data path.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: July 10, 2018
    Assignee: Intel Corporation
    Inventors: Martin Langhammer, Dongdong Chen, Jung Ko
  • Patent number: 9985636
    Abstract: To provide a memory element where a desired potential can be stored as data without an increase in the number of power source potentials. The memory element stores data in a node which is brought into a floating state by turning off a transistor a channel of which is formed in an oxide semiconductor layer. The potential of a gate of the transistor can be increased by capacitive coupling between the gate and a source of the transistor. With the structure, a desired potential can be stored as data without an increase in the number of power source potentials.
    Type: Grant
    Filed: January 7, 2015
    Date of Patent: May 29, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Takayuki Ikeda
  • Patent number: 9946826
    Abstract: In server virtualization, the resources of an integrated circuit are partitioned into smaller portions, and each of these smaller portions is then operated independently. Software is used to represent the smaller portions as virtual environments. For the purpose of server virtualization, an integrated circuit may include several different circuit designs, each implemented in a secure partition in the integrated circuit. The operation of the circuit design implementations in the integrated circuit may require that each circuit design implementation can be verified as un-altered and from the respective user or owner and as having been approved by the integrated circuit owner and/or the circuit design implementation owner. The operation of the circuit design implementations in the integrated circuit may require that each circuit design implementation can be operated securely and independently of the other circuit design implementations in the integrated circuit.
    Type: Grant
    Filed: September 2, 2015
    Date of Patent: April 17, 2018
    Assignee: Altera Corporation
    Inventors: Sean Atsatt, Ting Lu, Dana How, Herman Schmit
  • Patent number: 9904749
    Abstract: A method of emulating a circuit design using an emulator is presented. The method includes allocating one or more spare routing resources to one or more field programmable gate array (FPGA) routing sockets when compiling a plurality of FPGAs disposed in the emulator in preparation for emulating the circuit design, and using the one or more spare routing resources to provide one or more routings among the FPGAs in response to one or more changes made to the circuit design.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: February 27, 2018
    Assignee: SYNOPSYS, INC.
    Inventor: Etienne Lepercq
  • Patent number: 9880596
    Abstract: An integrated circuit includes a global power supply node. A first power domain has a first power management circuit, which includes a local power supply node. A first power control circuit is capable of receiving an input signal. A second power control circuit has a higher current capacity than the first power control circuit. The first power control circuit and the second power control circuit are coupled to the local power supply node and the global power supply node. The input signal is configured to initiate a power sequence, e.g., a power up process or a power down process, in the first power control circuit. A first control signal generated by the first power control circuit is configured to initiate a power sequence in the second power control circuit.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: January 30, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hank Cheng, Bharath Upputuri
  • Patent number: 9874688
    Abstract: Disclosed herein are designs, structures and techniques for advanced packaging of multi-function photonic integrated circuits that allow such high-performance multi-function photonic integrated circuits to be co-packaged with a high-performance multi-function ASIC thereby significantly reducing strenuous interconnect challenges and lowering costs, power and size of the overall devices.
    Type: Grant
    Filed: April 26, 2013
    Date of Patent: January 23, 2018
    Assignee: Acacia Communications, Inc.
    Inventors: Christopher Doerr, Eric Swanson, Diedrik Vermeulen, Saeid Azemati, Jon Stahl
  • Patent number: 9838021
    Abstract: The present invention discloses a configurable gate array based on three-dimensional writable memory (3D-W). It comprises an array of configurable computing elements, an array of configurable logic elements and an array of configurable interconnects. Each configurable computing element comprises at least a 3D-W array, which is electrically programmable and can be loaded with a look-up table (LUT) for a math function.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: December 5, 2017
    Assignees: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao Zhang
  • Patent number: 9825633
    Abstract: A method and apparatus is disclosed herein for segmented and direct routing in a programmable gate array. In one embodiment, the programmable gate array comprises a plurality of programmable tiles, including at least one SHLRT having: a block configurable as a logic function or a routing function; and one or more switching blocks coupled to programmable tiles in the plurality of programmable tiles for segmented routing.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: November 21, 2017
    Assignee: EFINIX, INC.
    Inventor: Tony Kai-Kit Ngai
  • Patent number: 9729153
    Abstract: A device includes a multiplexer circuit with a plurality of input circuits. Each input circuit is connected to a respective input node and a shared output node. The input circuits are configured to pass, in response to a respective control signal, a signal between the respective input and shared output node. An output circuit is configured to store data from the shared output node in a latch mode and to act as a buffer in a pass-through mode. A control circuit is configured to switch, in response to a configuration signal, the output circuit between the latch mode and the pass-through mode.
    Type: Grant
    Filed: August 11, 2016
    Date of Patent: August 8, 2017
    Assignee: XILINX, INC.
    Inventors: Ilya K. Ganusov, Benjamin S. Devlin
  • Patent number: 9684754
    Abstract: Various implementations described herein are directed to providing standard cell architecture layout design. A request to activate a grid is received. A request to place at least one edge of a shape at a particular location on the grid is received from an input device. The at least one edge of the shape is automatically placed in an allowed location based on pre-defined rules.
    Type: Grant
    Filed: October 2, 2015
    Date of Patent: June 20, 2017
    Assignee: ARM Limited
    Inventor: Alexis Cassard
  • Patent number: 9665677
    Abstract: A system including a configurable memory controller, a memory interface, and a configurable high speed communications fabric comprising a plurality of interconnect stations arranged in an array and operable to implement a plurality of pipelined buses, where the configurable memory controller is operably coupled to the configurable high speed communications fabric using a first interconnect station of the plurality of interconnect stations, where the memory interface is operably coupled to the configurable high speed communications fabric using a second interconnect station of the plurality of interconnect stations, where the plurality of interconnect stations are configured to satisfy a timing requirement of the memory interface, and where the configurable memory controller, the memory interface, and the configurable high speed communications fabric are associated with a configurable integrated circuit.
    Type: Grant
    Filed: June 3, 2015
    Date of Patent: May 30, 2017
    Assignee: Agate Logic, Inc.
    Inventors: Suresh Subramanian, Mukunda Krishnappa, Pohrong R. Chu, Jason Golbus, Dana L. How