Significant Integrated Structure, Layout, Or Layout Interconnections Patents (Class 326/41)
  • Patent number: 11144485
    Abstract: An interface for a semiconductor device includes a master device and a plurality of slave devices. The interface includes a master interface and a slave interface. The master interface is implemented in the master device and includes a master bond pattern of master bonds arranged as a first array. The slave interface is implemented each slave device and includes a slave bond pattern of slave bonds arranged as a second array. The first array of the master bonds includes a first central row and first data rows in two parts being symmetric to the first central row. The second array of the slave bonds includes a second central row and second data rows in two parts being symmetric to the second central row. The first central row and the second central row are aligned in connection, and the first data rows are connected to the second data rows.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: October 12, 2021
    Assignees: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Igor Elkanovich, Amnon Parnass, Pei Yu, Li-Ken Yeh, Yung-Sheng Fang, Sheng-Wei Lin, Tze-Chiang Huang, King Ho Tam, Ching-Fang Chen
  • Patent number: 11144512
    Abstract: Various techniques are disclosed herein for storing and managing master data in hierarchical data systems. Several related concepts, embodiments, and examples are disclosed, including techniques for incremental rationalization in a hierarchical data model, techniques for implementing governance pools in a hierarchical data model, techniques for application materialization in a hierarchical data model, techniques for data intersection mastering in a hierarchical data model, techniques for change request visualization in a hierarchical data model, and techniques for hierarchy preparation in a hierarchical data model.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: October 12, 2021
    Assignee: Oracle International Corporation
    Inventors: Matthew Lawrence Lontchar, Douglas R. Cosby, Anurag Garg, Rahul R. Kamath, Narayan Madhavan Nayar
  • Patent number: 11140000
    Abstract: A signal transmission apparatus has several serially-connected signal distribution modules, wherein interfaces of two adjacent signal distribution modules are each interconnected by a signal bridge. The signal transmission apparatus also has at least one direct connection between two signal distribution modules, which is routed through all signal bridges arranged between the two adjacent signal distribution modules and interconnects the interfaces of the adjacent signal bridges. In addition, a signal transmission bus is routed through all signal bridges and via all interfaces. The interfaces of all signal distribution modules have an identical design and all signal bridges connect two interfaces in the same way.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: October 5, 2021
    Assignee: Siemens Aktiengesellschaft
    Inventors: Ludwig Kraus, Christian Maul, Volker Müller
  • Patent number: 11095522
    Abstract: Described herein is a system and method for dynamically scaling a stream processing system (e.g., “exactly once” data stream processing system). Various parameter(s) (e.g., user-configurable capacity, real-time load metrics, and/or performance counters) can be used to dynamically scale in and/or scale out the “exactly once” stream processing system without system restart. Delay introduced by this scaling operation can be minimized by utilizing a combination of mutable process topology (which can dynamically assign certain parts of the system to a new host machine) and controllable streaming processor movement with checkpoints and the streaming protocol controlled recovery which still enforces the “exactly once” delivery metric.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: August 17, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Xindi Zhang, Boris Shulman, Alexander Alperovich, Patrick Chung
  • Patent number: 11095288
    Abstract: Switchboxes are especially used in integrated circuits with programmable logic (e.g. FPGAs). They are used to establish configurable signal paths between logic blocks. The present invention is based on the task to present a switchbox with a small number of multiplexers and configuration bits, which can both forward a signal in signal direction and can implement a change of direction. The task is solved by using switchboxes consisting of direction multiplexers and at least one direction change multiplexer. Thus the signal direction can be changed arbitrarily without increasing the size of the direction change multiplexers.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: August 17, 2021
    Inventor: Michael Gude
  • Patent number: 11068638
    Abstract: A power grid of an integrated circuit (IC) is provided. The power grid includes a plurality of first power lines formed in a first metal layer, a plurality of second power lines formed in the first metal layer, a plurality of third power lines formed in a second metal layer and a plurality of fourth power lines formed in the second metal layer. The second power lines are parallel to the first power lines, and the first and second power lines are interlaced in the first metal layer. The third power lines are perpendicular to the first power lines. The fourth power lines are parallel to the third power lines, and the third and fourth power lines are interlaced in the second metal layer. A first power pitch between two adjacent third power lines is greater than a second power pitch between two adjacent fourth power lines.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: July 20, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Hiranmay Biswas, Kuo-Nan Yang, Chung-Hsing Wang
  • Patent number: 11061665
    Abstract: When a host computer determines that a firmware version to be loaded is higher than a firmware version of each chip to be loaded, the host computer sends a loading flag to the chips to be loaded to enable the chips to be loaded enters a loading mode. The host computer redefines multiple controllable physical connections between each chip to be loaded entering the loading mode and a master controller chip connected thereto so that they act as loading buses. Each chip to be loaded executes a loading process according to a frame period and a frame count to receive the load file completely and then executes the IAP command to program its ROM. When each chip to be loaded finishes the loading process, each chip to be loaded jumps out of the load mode, and the host computer restores the definitions of the plurality of controllable physical connections.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: July 13, 2021
    Assignees: INVENTEC (PUDONG) TECHNOLOGY CORPORATION, INVENTEC CORPORATION
    Inventor: Ming Yang
  • Patent number: 11050680
    Abstract: A crossbar switch is disclosed having a first port, a second port, a third port, and a fourth port, the crossbar switch comprising: a first switching element coupled between the first port and the third port; a second switching element coupled between the first port and the fourth port; a third switching element coupled between the second port and the third port; and a fourth switching element coupled between the second port and the fourth port, wherein the first switching element, the second switching element, the third switching element, and the fourth switching element are configured to couple only one of the first port and the second port to the third port, at any given time.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: June 29, 2021
    Assignee: Raytheon Company
    Inventor: Ravash Eliassi
  • Patent number: 11037069
    Abstract: Method for creating gates and circuits for computing apparatus with greatly improved characteristics of size, weight, power consumption, reliability, environmental tolerance, radiation hardiness, and operational speed at reduced costs by using symbol transformer, is provided. The symbol transformer having at least a first multiplicity of symbol ports coupled to a first variety of symbols, and a second multiplicity of symbol ports coupled to a second variety of symbols, associates an arbitrary one or plurality of the first multiplicity of symbol ports to and with any one or any plurality of the second or other multiplicities of symbol ports. The symbols represent static, dynamic, or both type of variables, and are used to operations of reversible, irreversible, randomized and quantum gates, circuits, and apparatus. Examples of code-controlled symbol transformer circuits embodiments demonstrate amenability for down scaling and manufacturing in silicon and other main-line processings.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: June 15, 2021
    Inventor: Tegze P. Haraszti
  • Patent number: 11031091
    Abstract: An apparatus for measuring round-trip time of a test signal using a programmable logic device comprises a pattern generator generating a test signal and measuring a round-trip time of the test signal, a programmable logic device of which internal circuits are configured to transmit the test signal in a predetermined manner, and bidirectional bus lines connecting the pattern generator and the programmable logic device. The round-trip time of the test signal is measured by a time difference between a starting time at which the pattern generator outputs the test signal and an arrival time at which the test signal is fed back to the pattern generator.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: June 8, 2021
    Assignee: UNITEST INC.
    Inventor: Ho Sang You
  • Patent number: 11010858
    Abstract: A processing apparatus is described. The apparatus includes a plurality of processing cores, including a first processing core and a second processing core a first field programmable gate array (FPGA) coupled to the first processing core to accelerate execution of graphics workloads processed at the first processing core and a second FPGA coupled to the second processing core to accelerate execution of workloads processed at the second processing core.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: May 18, 2021
    Assignee: Intel Corporation
    Inventors: Carsten Benthin, Sven Woop, Ingo Wald
  • Patent number: 10977401
    Abstract: Disclosed approaches for creating a circuit design involving a network-on-chip (NoC) include instantiating in a memory of a computer system logic blocks and logical NoC (LNoC) blocks. Each logic block specifies a function of the circuit design and is communicatively coupled to another logic block through an LNoC block. The LNoC blocks are aggregated into a traffic specification that specifies connections between ingress circuits and egress circuits of the NoC. The traffic specification is compiled into configuration parameters for circuits of the NoC, and the logic blocks are compiled into implementation data for the target IC by the computer processor. The target IC can then be configured with the configuration parameters and implementation data.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: April 13, 2021
    Assignee: XILINX, INC.
    Inventors: Jeffrey M. Arnold, Stephen L. Bade, Srinivas Beeravolu, Chukwuweta Chukwudebe, Anindita Patra, Nabeel Shirazi
  • Patent number: 10977413
    Abstract: VLSI layouts of generalized multi-stage and pyramid networks for broadcast, unicast and multicast connections are presented using only horizontal and vertical links with spacial locality exploitation. The VLSI layouts employ shuffle exchange links where outlet links of cross links from switches in a stage in one sub-integrated circuit block are connected to inlet links of switches in the succeeding stage in another sub-integrated circuit block so that said cross links are either vertical links or horizontal and vice versa. Furthermore the shuffle exchange links are employed between different sub-integrated circuit blocks so that spatially nearer sub-integrated circuit blocks are connected with shorter links compared to the shuffle exchange links between spatially farther sub-integrated circuit blocks. In one embodiment the sub-integrated circuit blocks are arranged in a hypercube arrangement in a two-dimensional plane.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: April 13, 2021
    Assignee: Konda Technologies Inc.
    Inventor: Venkat Konda
  • Patent number: 10924117
    Abstract: A method for designing an FPGA may include determining blocks required for each of a plurality of applications; determining a size of the FPGA accommodating the determined blocks for each of the plurality of applications; and laying out the determined blocks for each of the plurality of applications in a block array of the FPGA.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: February 16, 2021
    Assignees: SK hynix Inc., INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
    Inventors: Jeongbin Kim, Kitae Kim, Kyungseon Cho, Seungjin Lee, Daehyung Cho, Eui-Young Chung, Hongil Yoon
  • Patent number: 10914785
    Abstract: The present disclosure provides a testing method and a testing system. The testing method is performed by at least one processor and includes the following operations: converting a circuit data of a scan test to a program, in which the program is configured to observe an untested part of a circuitry that is unable to be tested in the scan test; generating a waveform data associated with the untested part; generating a look-up table according to the program and a netlist file, in which the netlist file indicates the circuitry; and testing the untested part of the circuitry according to the waveform data and the look-up table.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: February 9, 2021
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Chihtung Chen, Hsing-Han Tseng, Yi-Te Yeh, Yung-Jen Chen, Te-Ming Kuo
  • Patent number: 10908817
    Abstract: An apparatus includes a first processor that generates first control signals to control a first circuit to perform memory operations on memory cells. A first number of first physical signal lines delivers the first control signals to a conversion circuit. A second number of second physical signal lines delivers converted control signals to the first circuit. The conversion circuit is coupled by the first number of first physical signal lines to the first processor and by the second number of second physical signal lines to the first circuit. The conversion circuit converts the first control signals to the converted control signals, and outputs the converted control signals to the first circuit. The first number of first physical signal lines is less than the second number of second physical signal lines to reduce the first number of first physical signal lines coupled between the first processor and the first circuit.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: February 2, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Tai-Yuan Tseng, Hiroyuki Mizukoshi, Chi-Lin Hsu, Yan Li
  • Patent number: 10895874
    Abstract: A method of controlling a flight device includes receiving, by a controller of the flight device, a control request from a target device for requesting a control of the flight device, receiving control data sent from the target device, and converting the control data into an executable instruction for controlling the flight device.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: January 19, 2021
    Assignee: SZ DJI TECHNOLOGY CO., LTD.
    Inventors: Shuo Yang, Jiahang Ying, Zhaoliang Peng
  • Patent number: 10855283
    Abstract: A reconfigurable circuit comprising: crossbar switches; wires, each of which is coupled to one output port of one crossbar switch and input ports of the other crossbar switches; at least one inverter inserted on each wire for driving long-distance signal transfer, wherein one or less first inverter is inserted on the wire between two adjacent crossbar switches; one or two second inverters inserted between a crossbar switch input port and its connected wire.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: December 1, 2020
    Assignee: NEC CORPORATION
    Inventors: Xu Bai, Toshitsugu Sakamoto, Yukihide Tsuji, Makoto Miyamura, Ayuka Tada, Ryusuke Nebashi
  • Patent number: 10797706
    Abstract: A programmable logic device including an asynchronous circuit is provided. The programmable logic device includes a lookup table, a first circuit, and a second circuit. The first circuit receives a first signal and a second signal. The second circuit sends a third signal. The first circuit sends a fourth signal and a fifth signal, when receiving the third signal. The fourth signal has the same logic as the first signal. The fifth signal has the same logic as the second signal. The lookup table sends a sixth signal and a seventh signal, when receiving the fourth signal and the fifth signal. The second circuit sends an eighth signal, when receiving the sixth signal and the seventh signal. The first circuit sends a ninth signal, when receiving the eighth signal. The lookup table includes a memory. The sixth signal and the seventh signal are generated from data stored in the memory.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: October 6, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yoshiyuki Kurokawa
  • Patent number: 10786171
    Abstract: One example of a device includes a sensor, a memristor code comparator, and a controller. The sensor is to provide a sensor signal. The memristor code comparator is to compare the sensor signal to a reference signal. The controller is to determine a status of the sensor signal based on the comparison.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: September 29, 2020
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Ning Ge, Ralph A. Morales, Terrance J. OShea, Helen A. Holder, David George, Hafid Hamadene
  • Patent number: 10761814
    Abstract: A method for visualizing system models in a model management environment, which includes the steps of opening the system model in the model editor, receiving a user input for rescaling a block, determining a relative horizontal position and a relative vertical position for each port in the block, calculating a new absolute horizontal and vertical position of each port in the block based on the relative horizontal and vertical position and the new size preset for the block, and displaying the block and each port in the block.
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: September 1, 2020
    Assignee: dSPACE digital signal processing and control engineering GmbH
    Inventors: Thomas Misch, Renate Loeffler, Joe Varghese
  • Patent number: 10739186
    Abstract: A weight cell including first and second bi-directional memory elements each configured to switch between a first resistance state and a second resistance state different than the first resistance state. A first input line is connected to a first terminal of the first bi-directional memory element, and a second input line is connected to the first terminal of the second bi-directional memory element. A first diode in forward bias connects the second terminal of the first bi-directional memory element to a first output line, a second diode in reverse bias connects the second terminal of the second bi-directional memory element to a second output line, a third diode in reverse bias connects the second terminal of the first bi-directional memory element to the second output line, and a fourth diode in forward bias connects the second terminal of the second bi-directional memory element to the first output line.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: August 11, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ryan M. Hatcher, Jorge A. Kittl, Borna J. Obradovic, Titash Rakshit
  • Patent number: 10715149
    Abstract: A system comprises a pair of configurable logic blocks (CLBs) placed adjacent to each other wherein each of the CLBs includes a plurality of configurable logic elements. A plurality sets of inodes are configured to accept signals to and/or from the CLBs, wherein a first set of inodes is positioned to the left of the adjacent CLBs and a second set of inodes is positioned to the right of the adjacent CLBs. A plurality of bnodes are embedded in the middle of the adjacent CLBs, wherein each bnode is configured to establish a first connection between the bnode and one of the first set of inodes on the left of the CLBs and a second connection between the bnode and one of the second set of inodes on the right of the CLBs. Both the first and second routing connections are localized within the pair of adjacent CLBs.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: July 14, 2020
    Assignee: XILINX, INC.
    Inventors: Eric F. Dellinger, Jay T. Young, Brian C. Gaide, Chirag Ravishankar, Davis Moore, Steven P. Young
  • Patent number: 10686447
    Abstract: An integrated circuit comprising an FPGA including programmable/configurable logic circuitry having a periphery, wherein resources (e.g., memory (e.g., high-speed local RAM), one or more busses, and/or circuitry external to the FPGA (e.g., a processor, a controller and/or system/external memory), is/are disposed outside the periphery of the programmable/configurable logic circuitry which includes a plurality of logic tiles, wherein at least one logic tile is located completely within the interior of the periphery and wherein each logic tile of the array of logic tiles includes a plurality of I/Os located on the perimeter of the logic tile wherein a first portion of the I/Os are located on a perimeter of the logic tile that is interior to the periphery, and the first portion of I/Os of each logic tile of the plurality of the logic tiles are directly connected to the bus to provide communication between the resources and the logic tiles.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: June 16, 2020
    Assignee: Flex Logix Technologies, Inc.
    Inventors: Cheng C. Wang, Anthony Kozaczuk, Geoffrey R. Tate
  • Patent number: 10672709
    Abstract: A power grid of an integrated circuit (IC) is provided. The power grid includes a plurality of first power lines formed in a first metal layer, a plurality of second power lines formed in the first metal layer and parallel to the first power lines, a plurality of third power lines formed in a second metal layer, and a plurality of fourth power lines formed in the second metal layer and parallel to the third power lines. The first and second power lines are interlaced in the first metal layer. The third and fourth power lines are interlaced in the second metal layer. Distances from the individual first power line to the two adjacent second power lines are the same, and distances from the individual third power line to the two adjacent fourth power lines are different.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: June 2, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Hiranmay Biswas, Kuo-Nan Yang, Chung-Hsing Wang
  • Patent number: 10666262
    Abstract: A programmable array logic includes a plurality of first signal lines, a plurality of second signal lines coupled to input terminals of a plurality of programmable AND gates, a plurality of first control units coupled to the first signal lines and second signal lines, a plurality of third signal lines coupled to output terminals of the programmable AND gates, a plurality of fourth signal lines coupled to input terminals of a plurality of programmable OR gates, and a plurality of second control units coupled to the third signal lines and the fourth signal lines. Each of the first control units has at least a first resistive memory for setting voltage level relationship between the first signal lines and the second signal lines. Each of second control units has a second resistive memory for setting voltage level relationship between the third signal lines and the fourth signal lines.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: May 26, 2020
    Assignee: Nuvoton Technology Corporation
    Inventor: Cheng-Chih Wang
  • Patent number: 10666261
    Abstract: Systems and methods related to multi-die integrated circuits that may include dies having high-speed core interconnects. The high-speed core interconnects may be used to directly connect two adjacent dies.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: May 26, 2020
    Assignee: Intel Corporation
    Inventors: Lai Guan Tang, Ankireddy Nalamalpu, Dheeraj Subbareddy
  • Patent number: 10664565
    Abstract: A method (of expanding a set of standard cells which comprise a library, the library being stored on a non-transitory computer-readable medium) includes: selecting one ad hoc group amongst ad hoc groups of elementary standard cells which are recurrent resulting in a selected group such that the elementary standard cells in the selected group having connections so as to represent a corresponding logic circuit, each elementary standard cell representing a logic gate, and the selected group corresponding providing a selected logical function which is representable correspondingly as a selected Boolean expression; generating, in correspondence to the selected group, one or more macro standard cells; and adding the one or more macro standard cells to, and thereby expanding, the set of standard cells; and wherein at least one aspect of the method is executed by a processor of a computer.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: May 26, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Lin Liu, Sheng-Hsiung Chen, Jerry Chang-Jui Kao, Fong-Yuan Chang, Lee-Chung Lu, Shang-Chih Hsieh, Wei-Hsiang Ma
  • Patent number: 10659052
    Abstract: Devices and methods for reconfiguring a programmable fabric include identifying resources in a programmable fabric of the programmable device as belonging to a partition. Reconfiguring the programmable fabric also includes creating a mask for the partition that indicates that the identified resources belong to the partition. Reconfiguring the partition also includes reconfiguring resources, via a configuration controller, in programmable fabric associated with the partition using the mask without changing resources associated with other partitions in the programmable fabric.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: May 19, 2020
    Assignee: Intel Corporation
    Inventors: Sean R. Atsatt, Andrew Draper
  • Patent number: 10630269
    Abstract: Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a programmable logic device (PLD) includes a plurality of programmable logic blocks (PLBs) and at least first and second logic cells within at least one of the PLBs, where each logic cell includes a lookup table (LUT) and associated mode logic configured to receive a LUT output signal from the LUT. The associated mode logic is configured to use a single physical signal output to provide a logic cell output signal corresponding to a selected logic function operational mode, ripple arithmetic operational mode, or extended logic function operational mode for each logic cell.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: April 21, 2020
    Assignee: Lattice Semiconductor Corporation
    Inventors: Brad Sharpe-Geisler, Senani Gunaratna, Ting Yew
  • Patent number: 10608642
    Abstract: A field-programmable-gate-array (FPGA) integrated-circuit (IC) chip configured to perform a logic function based on a look-up table (LUT), includes: multiple non-volatile memory cells therein configured to store multiple resulting values of the look-up table (LUT); and a programmable logic block therein having multiple static-random-access-memory (SRAM) cells configured to store the resulting values passed from the non-volatile memory cells, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values stored in the static-random-access-memory (SRAM) cells into its output.
    Type: Grant
    Filed: January 21, 2019
    Date of Patent: March 31, 2020
    Assignee: iCometrue Company Ltd.
    Inventors: Jin-Yuan Lee, Mou-Shiung Lin
  • Patent number: 10591543
    Abstract: Provided are a test board and a test system for efficiently testing a semiconductor package, and a manufacturing method for the semiconductor package using the same. A test apparatus includes a field programmable gate array (FPGA) configured to output a first data signal to be transmitted to the semiconductor device and a second data signal to be transmitted to the semiconductor device and a memory configured to store a test result. The FPGA includes a first input/output block configured to output the first data signal, a second input/output block configured to output the second data signal, a serializer/deserializer (SerDes) circuit configured to generate a strobe signal, and a skew calibration input/output block configured to receive the first data signal from the first input/output block, the second data signal from the second input/output block, and the strobe signal from the SerDes circuit.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: March 17, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joo-sung Yun, Soon-il Kwon, Byeong-min Yu
  • Patent number: 10578799
    Abstract: Disclosed herein are designs, structures and techniques for advanced packaging of multi-function photonic integrated circuits that allow such high-performance multi-function photonic integrated circuits to be co-packaged with a high-performance multi-function ASIC thereby significantly reducing strenuous interconnect challenges and lowering costs, power and size of the overall devices.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: March 3, 2020
    Assignee: Acaia Communications
    Inventors: Christopher Doerr, Eric Swanson, Diedrik Vermeulen, Saeid Azemati, Jon Stahl
  • Patent number: 10574237
    Abstract: An application specific integrated circuit (ASIC) and a method for its design and fabrication is disclosed. In one embodiment, the camouflaged application specific integrated circuit (ASIC), comprises a plurality of interconnected functional logic cells that together perform one or more ASIC logical functions, wherein the functional logic cells comprise a camouflage cell including: a source region of a first conductivity type, a drain region of the first conductivity type, and a camouflage region of a second conductivity type disposed between the source region and the drain region. The camouflage region renders the camouflage cell always off in a first camouflage cell configuration and always on in a second camouflage cell configuration having a planar layout substantially indistinguishable from the first configuration.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: February 25, 2020
    Assignee: VERIMATRIX
    Inventors: Ronald P. Cocchi, Lap Wai Chow, James P. Baukus, Bryan J. Wang
  • Patent number: 10566301
    Abstract: A reconfigured semiconductor logic device includes a semiconductor logic device comprising a plurality of input/output (I/O) pads formed on an active surface thereof and a redistribution layer. The redistribution layer comprises an insulating layer formed atop the active surface of the semiconductor logic device such that the insulating layer does not extend beyond an outer perimeter of the active surface and a patterned conductive wiring layer positioned above the insulating layer. The patterned conductive wiring layer includes a plurality of terminal buses formed on a top surface of the insulating layer. Each terminal bus of the plurality of terminal buses is electrically coupled to multiple I/O pads of the plurality of I/O pads through vias formed in the insulating layer.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: February 18, 2020
    Assignee: General Electric Company
    Inventors: Raymond Albert Fillion, Kaustubh Ravindra Nagarkar
  • Patent number: 10534625
    Abstract: Disclosed herein is an apparatus and method for emulating hardware. The apparatus includes a data array configured to store input data for an emulation cycle and a carry chain coupled to the data array receives one or more inputs from the data array. The carry chain is configured to generate output data in response to performing an arithmetic operation by a set of configurable logic gates using the one or more inputs in a pre-determined number of clock cycles. One or more processors are coupled to the carry chain and the data array, and are configured to emulate a logic gate function using at least the input data from the data array or the output data from the carry chain.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: January 14, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventor: Beshara Elmufdi
  • Patent number: 10528513
    Abstract: An integrated circuit comprises programmable resources; a plurality of hard blocks; and a programmable connector coupled to the programmable resources, the plurality of hard blocks; wherein the programmable connector is configurable to route signals between a first hard block and a second hard block in a first mode of operation and to route signals between the first hard and the programmable resources in a second mode of operation.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: January 7, 2020
    Assignee: Xilinx, Inc.
    Inventors: Chee Chong Chan, Warren E. Cory, Jason R. Bergendahl
  • Patent number: 10511479
    Abstract: A service deployment method and a network functions acceleration platform are provided. The method includes: when an FPGA is powered on, loading, by the FPGA, an FPGA framework file, so that the FPGA includes M partial reconfigurable PR areas, a configuration module, and a data flow forwarding module; when receiving a service configuration instruction, generating, by a physical machine, a VM, and selecting at least one PR area from the M PR areas to establish a correspondence with the VM; performing, by a configuration module, service resource configuration on the selected PR area according to a PR configuration resource, so that the selected PR area has a service processing capability; adding, by the configuration module, a forwarding entry corresponding to the PR area in a forwarding flow table, so that the data flow forwarding module forwards a received network packet to the corresponding PR area.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: December 17, 2019
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Yuming Xie, Liang Zhang, Jun Wu, Fan Yang
  • Patent number: 10505522
    Abstract: A standard cell layout for a flip-flop includes a flip-flop circuit and an initialization circuit. Metallization levels over the standard cell layout support circuit interconnections. At least one metallization level is provided for metal programming of an initialization configuration of the flip-flop. The at least one metallization level may have: a first wiring layout for interconnecting the initialization circuit to the flip-flop circuit for configuration programming of the flip-flop as an initialization in reset device (assertion of an initialization signal causing the flip-flop data output to be reset), or a second wiring layout for interconnecting the initialization circuit to the flip-flop circuit for configuration programming of the flip-flop as an initialization in set device (assertion of the initialization signal causing the flip-flop data output to be set).
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: December 10, 2019
    Assignee: STMicroelectronics SA
    Inventors: Sylvain Engels, Alain Aurand, Etienne Maurin
  • Patent number: 10489324
    Abstract: Systems and methods for port management are disclosed. In one aspect, the system may consolidate port management functions as well as power conversion, protection features, and signal conditioning circuitry into a single integrated circuit (IC) for a device without a battery. Further exemplary aspects allow for arbitration between ports to handle power supply versus power sink functions. Still further exemplary aspects provide an indication when a weak power source is coupled to the computing device to alert a user that the weak power source may not provide sufficient power for full operation. Such consolidated functionality allows a single form factor to be used for all ports whether the ports are used as a power port or an output port. Further, such consolidated functionality helps mitigate possible damage caused by improper activity.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: November 26, 2019
    Assignee: Qualcomm Incorporated
    Inventors: Christian Gregory Sporck, Georgios Konstantinos Paparrizos
  • Patent number: 10409604
    Abstract: An apparatus and method are provided for performing multiply-and-accumulate-products (MAP) operations. The apparatus has processing circuitry for performing data processing, the processing circuitry including an adder array having a plurality of adders for accumulating partial products produced from input operands. An instruction decoder is provided that is responsive to a MAP instruction specifying a first J-bit operand and a second K-bit operand, to control the processing circuitry to enable performance of a number of MAP operations, where the number is dependent on a parameter. For each performed MAP operation, the processing circuitry is arranged to generate a corresponding result element representing a sum of respective E×F products of E-bit portions within an X-bit segment of the first operand with F-bit portions within a Y-bit segment of the second operand, where E<X?J and F<Y?K.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: September 10, 2019
    Assignee: ARM Limited
    Inventors: Michael Alexander Kennedy, Neil Burgess
  • Patent number: 10402366
    Abstract: Briefly, an efficient and scalable processor device is disclosed that uses multi-value voltages for operands, results, and signaling. An array of cells is arranged in rows and columns, and one or more multi-value operands are used to select a cell from the array. A row driver may be used to select a row of cells, and a column driver is used to select a particular column from the selected row. Once a particular cell is selected, a voltage value associated with that cell is passed as an output, which is typically a multi-value result. The multi-value processor is constructed such that the row driver and column driver can be substantially identical, and have a structure that enables significant circuit reuse, provides substantial reduction in size for a circuit layout, has increased layout symmetry, simple scalability, and advantageous power conservation.
    Type: Grant
    Filed: October 25, 2011
    Date of Patent: September 3, 2019
    Inventor: Benjamin J. Cooper
  • Patent number: 10404255
    Abstract: A device for automatic configuration of a semiconductor integrated circuit includes a memory that stores circuit data representing a structure of a logic circuit including a first clock gating circuit, and a processor. The processor is configured to retrieve the circuit data from the memory, determine first and second logical elements from each of which an enable signal is output to the first clock gating circuit, calculate a delay time of each of the first and second logical elements, separate the first and second logical elements on the basis of the calculated delay time, and add a second clock gating circuit for the first logical element after separating the first and second logical elements.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: September 3, 2019
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Hironori Sato, Hiroaki Muraoka
  • Patent number: 10396800
    Abstract: A memory block integrated in a programmable logic device (PLD) is disclosed. The memory block includes: one or more lookup tables storing pre-populated data. The PLD includes a programmable fabric and a signal wrapper configured to provide signals between the memory block and the programmable fabric. The memory block is configured to receive input signals from the signal wrapper and generate output signals to the signal wrapper by looking up the pre-populated data corresponding to the input signals. The pre-populated data stored in the one or more lookup tables are programmably changed by programming a plurality of parameters of the programmable fabric and loading the pre-populated data to the one or more lookup tables via the signal wrapper.
    Type: Grant
    Filed: October 9, 2018
    Date of Patent: August 27, 2019
    Assignee: AnDAPT, Inc.
    Inventors: Kapil Shankar, Herman Cheung, John Birkner, Patrick J. Crotty
  • Patent number: 10384447
    Abstract: In a liquid ejection head, an ejection unit of a channel member includes an ejection hole, a pressurizing chamber connected to the ejection hole, a first channel and a second channel each connecting the pressurizing chamber and a first common channel, and a third channel connecting the pressurizing chamber and a second common channel. The first common channel, in the channel direction, includes a plurality of first portions, and a plurality of second portions each located between each two of the plurality of first portions and having smaller cross-sectional areas than those of the first portions in front and back of the same. In each of the plurality of ejection units, the first channel and the second channel are individually connected to two positions in the first common channel which sandwich at least one of the second portions between them.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: August 20, 2019
    Assignee: Kyocera Corporation
    Inventors: Naoki Kobayashi, Hiroyuki Kawamura, Wataru Ikeuchi
  • Patent number: 10371802
    Abstract: Systems and methods for performing optical distance measurement are provided. In one aspect, a system for measuring a distance to an object comprises a light emitter configured to emit an outbound light pulse, and a light sensor configured to receive a returning light pulse reflected from the object and output an analog pulse signal representing the returning light pulse. The system also comprises a field-programmable gate array (FPGA) coupled to the light sensor. The FPGA is configured to convert the analog pulse signal to a plurality of digital signal values, and generate a plurality of time measurements corresponding to the plurality of digital signal values. The system also comprises a controller configured to calculate the distance to the object based on the plurality of digital signal values and the plurality of time measurements.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: August 6, 2019
    Assignee: SZ DJI Technology Co., Ltd.
    Inventors: Xiang Liu, Mingming Gao, Xiaoping Hong, Di Wu
  • Patent number: 10331837
    Abstract: Rendering a graphical representation of an integrated circuit can include determining, using a processor, a tile of a device model at least partially within a viewport, determining, using the processor, an owning tile having a fly-over wire passing over the tile, determining, using the processor, a predetermined shape of the fly-over wire, and drawing, using the processor, the fly-over wire within the viewport based upon the shape.
    Type: Grant
    Filed: November 17, 2016
    Date of Patent: June 25, 2019
    Assignee: XILINX, INC.
    Inventors: Jennifer D. McEwen, Ian L. McEwen, Chong M. Lee, Bart Reynolds
  • Patent number: 10318468
    Abstract: An FPGA-based interface signal remapping method, relates to the technical field of nuclear power system, and solves the technical problems of poor reliability, readability and debuggability in the prior art. The method comprises dividing an internal programmable logic of an FPGA chip into two independent modules, with one module being an I/O module and the other module being a Core module, using the I/O module to process signal excursion occurring when an external signal is input to or output from the FPGA chip, signal collision caused by line multiplexing, metastable state in a data transmission process, and a data transmission error between asynchronous clock domains, using the Core module to implement logical processing and computing; and introducing a master clock signal outside the FPGA chip into the FPGA chip through a global clock pin of the FPGA chip. The method provided in the invention is suitable for a nuclear power protection system platform.
    Type: Grant
    Filed: January 4, 2016
    Date of Patent: June 11, 2019
    Assignee: STATE NUCLEAR POWER AUTOMATION SYSTEM ENGINEERING CO., LTD.
    Inventors: Jian Zhang, Qunxing Jiang, Xiaokai Wang
  • Patent number: 10310868
    Abstract: A processor includes a core within a package and layers of programmable fabric within the same package as the core. The core includes logic to execute an instruction by loading a configuration file to one of the layers of programmable fabric. The configuration is to program an identified execution functionality. The execution functionality is to execute at least part of the instruction.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: June 4, 2019
    Assignee: Intel Corporation
    Inventor: Leo A. Linsky
  • Patent number: 10236888
    Abstract: Disclosed are a circuit and method for implementing a switching function. In an embodiment, the circuit includes a first logic circuit, a second logic circuit, and a Correlated electron switch (CES) element. The CES element is configurable to have a non-volatile state to enable or disable an electrical connection between the first logic circuit and the second logic circuit.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: March 19, 2019
    Assignee: ARM Ltd.
    Inventors: Vikas Chandra, Robert Campbell Aitken