Abstract: A memory array has a plurality of conductor structures. Each conductor structure has a top wire segment extending in a first direction, a middle wire segment extending in a second direction at an angle from the first direction, a bottom wire segment extending in a direction opposite to the first direction, and a via connecting the top, middle, and bottom wire segments. A plurality of memory cells in an upper plane of the memory array are formed at intersections of the middle wire segment of each conductor structure with the top wire segments of neighboring conductor structures, and a plurality of memory cells in a lower plane are formed at intersections of the middle wire segment of each conductor structure with the bottom wire segments of neighboring conductor structures.

Abstract: Path transistor malfunction is reduced. A path gate circuit includes transistors MP, MW, and MC. The transistor MP functions as a path transistor that connects a signal line INL to a signal line OUTL. The transistor MW connects a signal line BL for inputting a signal for setting the on or off state of the transistor MP and a node SN (gate of the transistor MP). When a high-level potential is written to the node SN, the potential of BL is set higher than a normal high-level potential if the potential of INL is high. Thus, even when the potential of the node SN is dropped in accordance with transition of INL from a high level to a low level, the potential drop does not influence the operation of the transistor MP because a high potential is written in advance.

Abstract: There is provided a strata manager within a 3D chip stack having two or more strata. The strata manager includes a plurality of scannable configuration registers, each being arranged on a respective one of the two or more strata for storing a set of bits. The set of bits is configured to program an operation of a corresponding one of the two or more strata on which the set of bits is stored or a device thereon. Additionally, a stratum identifier within a 3D stack and stack-wide scan circuit within a 3D stack are provided.

Abstract: An integrated circuit (“IC”) that includes a configurable routing fabric with controllable storage elements is described. The routing fabric provides a communication pathway that routes signals to and from source and destination components. The routing fabric may provide the ability to selectively store the signals passing through the routing fabric within the storage elements of the routing fabric. In this manner, a source or destination component may continually perform operations (e.g., computational or routing) irrespective of whether a previous signal from or to such a component is stored within the routing fabric. The source and destination components include configurable logic circuits, configurable interconnect circuits, and various other circuits that receive or distribute signals throughout the IC.

Abstract: Testing power domains of a circuit design includes correlating, using a processor, a selected power domain of a circuit design having a plurality of power domains with a partial reconfiguration partition and implementing the circuit design within an integrated circuit. The partial reconfiguration partition is implemented within a reconfigurable region of the integrated circuit. A power off state for the selected power domain of the circuit design is emulated by partially reconfiguring the reconfigurable region of the integrated circuit.

Abstract: An integrated circuit die stack comprises a first die and a second die connected to each other. Each of the first and second dies comprise a functional circuitry, a plurality of first contacts on a first surface of the respective die, a plurality of second contacts on a second surface of the respective die, and a programmable array coupled to the functional circuitry and the plurality of first and second contacts. The programmable array includes a plurality of programmable connection elements in the first and second dies. The programmable connection elements are programmed to bypass one of the first and second dies.

Abstract: Approaches for configuring programmable resources of a programmable IC are disclosed. A first set of configuration data is loaded using a configuration port of the programmable IC, which also includes input/output (I/O) ports. Programmable resources are configured according to the first set of configuration data to implement a master data link circuit and at least one slave data link circuit. The master data link circuit includes a hardwired communication circuit, and a set of the programmable resources arranged to form a communication control circuit configured to control the communication circuit to provide a data link for communicating data via one of the I/O ports. A second set of configuration data is loaded using the master data link circuit. Programmable resources of the programmable IC are configured according to the second set of configuration data to implement a logic circuit configured to communicate data via the slave data link circuit.

Abstract: One embodiment relates to an integrated circuit including a multiple-voltage programmable logic fabric. The programmable logic fabric includes circuits of a first type operating in a first voltage domain and circuits of a second type operating in a second voltage domain. The second voltage domain has a lower supply voltage than the first voltage domain. The integrated circuit further includes downward level conversion circuit elements in the programmable logic fabric for driving signals from the first voltage domain to the second voltage domain and upward level conversion circuit elements in the programmable logic fabric for driving signals from the second voltage domain to the first voltage domain. Other embodiments, aspects, and features are also disclosed.

Abstract: A programmable integrated circuit is disclosed. The programmable integrated circuit comprises a plurality of circuit blocks, each circuit block of the plurality of circuit blocks comprising configurable blocks; and a routing network coupled to each circuit block of the plurality of circuit blocks, the routing network enabling asynchronous data communication with the plurality of circuit blocks. Each circuit block comprises an interface portion having routing circuits coupled to the routing network, the routing circuits enabling routing data to the configurable blocks of the circuit block. A method of asynchronously routing data in a circuit block of an integrated circuit is also disclosed.

Abstract: A system and method for reducing power consumption in a reconfigurable integrated circuit. Some embodiments provide placement and routing programs that reduce the number of bits to be reconfigured. Some embodiments provide placement and routing programs that increase the number of groups of circuits that do not need reconfiguration at some times. Some embodiments include circuits that selectively block reconfiguration.

Abstract: One embodiment provides a semiconductor integrated circuit, including: a first input wire; a second input wire; a first look-up table (LUT) comprising: a plurality of first memories; a first number of first switches connected to the first input wire; and a second number of second switches connected to the second input wire, the second number being less than the first number, the first LUT being configured to output information which is stored in one of the first memories; and a second LUT including: a plurality of second memories; a third number of third switches connected to the second input wire; and a fourth number of fourth switches connected to the first input wire, the fourth number being less than the third number, the second LUT being configured to output information which is stored in one of the second memories.

Abstract: Systems and methods can perform automatic computation developed using carbon nanotubes and graphene nanoribbons and/or InSb p-n bilayer channel avalanche diodes and wires. Spin logic can provide improvements in speed, power, and area, promising to be a high-performance logic family for the next generation of computing. The systems and methods can replace CMOS, for example, for general computing applications.

Abstract: There is described a passive heater-and-diode multiplexing network for selective addressing of thermally-coupled and electrically-disconnected fuses within a passive device network (resistor/capacitor/inductor) or within an application circuit.

Abstract: A hybrid IO cell for use with controlled collapse chip connection, wirebond core limited, wirebond IO limited, and wirebond inline chip designs is provided. A method of designing the hybrid IO cell includes designating a technology, determining a minimum pad width of the technology, and determining a minimum pad spacing of the technology. The method also includes determining a width of the hybrid IO cell based on the minimum pad width and the minimum pad spacing, setting a length of the hybrid IO cell equal to the determined width, and storing a definition of the IO cell in a library stored on a computer useable storage medium.

Abstract: A PLD comprises a substrate, an array of programmable logic elements formed in the substrate, a first columnar interface coupling to the array of logic elements and extending in the substrate substantially parallel to a first side of the substrate, and at least a second columnar interface coupling to the array of logic elements and extending in the substrate substantially parallel to the first columnar interface. The interfaces illustratively provide a plurality of interconnects, control circuits and one or more of driver circuits, rebuffering circuits, signal conditioning circuits, deskewing circuits, clock synchronization circuits, power management circuits, testing/debugging circuits, partial reconfiguration circuits, multi-plexing circuits, pipelining circuits and storage circuits. The PLD is mounted on an interposer so that its interfaces electrically couple to electrically conducting paths on the interposer.

Abstract: There is provided a field programmable gate array (FPGA) mounted apparatus included in a first node of a plurality of nodes connected on a network, the FPGA mounted housing apparatus including a printed circuit board (PCB) on which an FPGA is mounted, and a controller configured to issue a request to acquire configuration data of the FPGA to a second node of the plurality of nodes, and configure the FPGA based on the configuration data acquired from the second node in response to the request.

Abstract: A Programmable Logic Device (PLD) structure using third dimensional memory is disclosed. The PLD structure includes a switch configured to couple a polarity of a signal (e.g., an input signal applied to an input) to a routing line and a non-volatile register configured to control the switch. The non-volatile register may include a non-volatile memory element, such as a third dimension memory element. The non-volatile memory element may be a two-terminal memory element that retains stored data in the absence of power and stores data as a plurality of conductivity profiles that can be non-destructively sensed by applying a read voltage across the two terminals. New data can be written to the two-terminal memory element by applying a write voltage across the two terminals. Logic and other active circuitry can be positioned in a substrate and the non-volatile memory element can be positioned on top of the substrate.

Abstract: An IC with configuration context switchers is provided. The IC includes several configurable circuits, each of which configurably performs one of several operations at any given time, based on the configuration data set that it receives at that time. The IC includes several storage circuits for storing several configuration data sets for each of the configurable circuits. The IC also includes a context switching interconnect circuit for switchably connecting the configurable circuit to different sets of storage circuits to receive different sets of configuration data sets. The context switcher includes one or more stages for re-timing the data coming from the configuration storage elements. The stages can include interconnect circuitry or storage circuitry. Some embodiments build one of the stages in the configuration data storage elements. Some embodiments encode the configuration data bits and hence utilize a decoder in the context switcher to decode the encoded configuration data.

Abstract: New logic blocks capable of replacing the use of Look-Up Tables (LUTs) in integrated circuits, such as Field-Programmable Gate Arrays (FPGAs), are disclosed herein. In one embodiment, the new logic block is a tree structure comprised of a number of levels of cells with each cell consisting of a logic gate or the functional equivalent of a logic gate, one or more selectable inverters, and wherein the inputs of the logic block consist of the inputs to the logic gate or functional equivalent of the logic gate and inputs to the selectable inverters. The new logic blocks can map circuits more efficiently than LUTs, because they include multi-output blocks and can cover more logic depth due to the higher input and output bandwidth.

Abstract: Bidirectional buffer 20D includes: multiplexer 30 that is equipped with rewriteable variable-resistance nonvolatile switch elements for each input terminal; tristate buffer 51 that is equipped with rewriteable variable-resistance nonvolatile switch elements for each output terminal and that receives the output of multiplexer 30 as input; demultiplexer 31 that receives the output of tristate buffer 51 as input; programming transistor tr0 whose drain terminal is connected to the input terminal of tristate buffer 51; and programming transistor tr1 whose drain terminal is connected to the output terminal of tristate buffer 51. Input terminals i1 and i3 of multiplexer 30 are connected to respective output terminals t1 and t2 of demultiplexer 31.

Abstract: A semiconductor device including a PLD which can increase the execution speed of an application with low power consumption is provided. The semiconductor device includes a programmable logic device and a processor which is not dynamically reconfigured. A memory element of the programmable logic device stores a plurality of pieces of configuration data determined to have high frequency of use by a memory module among configuration data corresponding to a thread. The memory element includes a storage element and a switch in each of a plurality of memory cells. The switch is used for supplying charge whose amount is determined by the plurality of pieces of stored configuration data to the storage element, retaining the charge in the storage element, and discharging the charge from the storage element.

Abstract: A self-modifying FPGA system includes an FPGA and a configuration memory coupled to the FPGA for providing the FPGA with configuration data including SAFE configuration data and dormant configuration data. The SAFE configuration data is initially loaded to the FPGA and the FPGA is configured to a safe operating mode. Upon a determination to proceed to a next step of self modification, dormant configuration data contained in the configuration memory is loaded into the FPGA and the FPGA is configured to a secure operating mode.

Abstract: A method of layout of pattern includes the following processes. A graphic data of a first wiring in a first area of a semiconductor wafer is extracted. The first area is a semiconductor chip forming area. The first area is surrounded by a scribed area of the semiconductor wafer. The first area includes a second area. The second area is bounded with the scribed area. The second area has a second distance from a boundary between the semiconductor chip forming area and the scribed area to an boundary between the first area and the second area. A first dummy pattern in the first area is laid out. The first dummy pattern has at least a first distance from the first wiring. A second dummy pattern in the second area is laid out. The second dummy pattern has at least the first distance from the first wiring. The second dummy pattern has at least a third distance from the first dummy pattern.

Abstract: A programmable logic device having low power consumption with operation speed maintained is provided. The programmable logic device includes a first circuit; a second circuit; a first transistor making electrical connection between the first circuit and the second circuit depending on a potential of a gate of the first transistor; a first switch configured to control supply of a signal to a first node; a second switch configured to control supply of the signal to a second node; a second transistor having a gate and one of a source and a drain that are electrically connected to the first node and having the other of the source and the drain that is electrically connected to the second node; and a capacitor that holds a potential of the signal supplied to the first node.

Abstract: A signal processing device is provided. In a programmable switch in which one of a source and a drain of a first transistor is connected to a gate of a second transistor to control continuity between a source and a drain of the second transistor, a capacitance connected to the gate of the second transistor (which is indicated by CS and includes a parasitic capacitance) is less than twice a capacitance represented by the following formula: C gs + C gd ? C C gd + C , where C is a load capacitance, Cgs is a capacitance between the source and gate of the second transistor, and Cgd is a capacitance between the drain and gate of the second transistor.

Abstract: A programmable device, having an analog component coupled with an analog bus and a digital component coupled with a digital bus together with a set of IO pads, each of which capable of being coupled to a bus line of one segment of the analog bus as well as to at least one digital bus line, and where the analog bus is capable of being used to connect a pair of the IO pads to each other.

Abstract: What is disclosed is a wireless push button device. The wireless push button device includes a user interface configured to receive user input to control a process of a machine system. The wireless push button device also includes a first transceiver coupled to the user interface and configured to wirelessly receive input power from a second transceiver, provide user power to the user interface, and wirelessly transfer communications related to the user input to the second transceiver. The wireless push button device also includes a processing system configured to determine when a power transfer problem exists between the second transceiver and the first transceiver, and transfer an alert in response to the power transfer problem.

Abstract: A semiconductor integrated circuit including: a circuit block having an internal voltage line; an annular rail line forming a closed annular line around the circuit block and supplied with one of a power supply voltage and a reference voltage; and a plurality of switch blocks arranged around the circuit block along the annular rail line, the plurality of switch blocks each including a voltage line segment forming a part of the annular rail line and a switch for controlling connection and disconnection between the voltage line segment and the internal voltage line.

Abstract: In one aspect, a method of testing an IC is provided. In one embodiment, the method includes: programming a resistive element in the IC at an intermediate ON state, where in addition to the intermediate ON state, the resistive element has another ON state, further where at the intermediate ON state, the resistive element has a resistance that is at least 10 times greater than a resistance of the resistive element at the another ON state; and applying test data to the resistive element.

Abstract: A switch block circuit in a field programmable gate array is provided. The switch block circuit includes a configuration memory unit including first group memories and second group memories and a switching unit including first group switching transistors and second group switching transistors. The switch block circuit further includes a selection unit for correspondingly connecting the second group memories with the second group switching transistors depending on an operation mode. The switch block is efficiently reconfigurable depending on the intended use, and configuration memories unused in a specific operation mode may be applied to other purposes.

Abstract: An integrated circuit, a memory device, a method of operating an integrated circuit and a method of designing an integrated circuit are provided. An integrated circuit comprises a plurality of logical elements and a bus carrying signals for said plurality of logical elements. The integrated circuit also comprises a routing unit having an input coupled to said bus and a plurality of outputs to route signals received at said input to at least one of said outputs. The integrated circuit also comprises a plurality of lines coupled to said plurality of outputs to conduct said signals from said routing unit to at least one of said plurality of logical elements, wherein at least one of said plurality of lines couples said routing unit to only one of said logical elements.

Abstract: A method and system provide and program a nonvolatile logic device. The nonvolatile logic device includes input and output magnetic junctions and at least one magnetic junction between the input and output magnetic junctions. The input magnetic junction includes an input junction free layer having an input junction easy axis. The input magnetic junction may be switchable using a current driven through the magnetic junction. The output magnetic junction includes an output junction free layer having an output junction easy axis. Each of the magnetic junction(s) includes a free layer having an easy axis. The input magnetic junction is magnetically coupled to the output magnetic junction through the magnetic junction(s). In some aspects, the method includes switching the magnetic moment(s) of the input magnetic junction from a first state to a second state, applying and then removing magnetic field(s) along the hard axis of the at least one magnetic junction.

Abstract: Some embodiments provide a configurable integrated circuit (IC) having a routing fabric that includes configurable storage element in its routing fabric. In some embodiments, the configurable storage element includes a parallel distributed path for configurably providing a pair of transparent storage elements. The pair of configurable storage elements can configurably act either as non-transparent (i.e., clocked) storage elements or transparent configurable storage elements. In some embodiments, the configurable storage element in the routing fabric performs both routing and storage operations by a parallel distributed path that includes a clocked storage element and a bypass connection. In some embodiments, the configurable storage element perform both routing and storage operations by a pair of master-slave latches but without a bypass connection.

Abstract: A diode-switch logic circuit of the present invention is configured such that: at least one of paths between a common input-output terminal and respective individual input-output terminals is caused to become a conducting state; control voltages of control terminals are respectively applied to gates of path switching FET stages; logic synthesis voltages of the control voltages of the control terminals are respectively applied to gates of shunt FET stages; and each of the logic synthesis voltages is generated by a logical product of a logical negation of the control voltage applied to one shunt FET stage and a logical sum of the control voltages respectively applied to the remaining shunt FET stages.

Abstract: One embodiment provides a programmable logic switch in which a first nonvolatile memory and a second nonvolatile memory are formed in the same well, and in which to change the first nonvolatile memory from an erased state to a written state and leave the second nonvolatile memory being in the erased state, a first write voltage is applied to a first line connected with gate electrodes of the first and second nonvolatile memories, a second write voltage is applied to a second line connected to a source in the first nonvolatile memory, and a third write voltage lower than the second write voltage is applied to a fourth line connected to a source of the second nonvolatile memory.

Abstract: Digital signal processing (“DSP”) circuit blocks that include multipliers of a certain basic size are augmented to enable the DSP block to perform multiplications that are larger than the basic multiplier size would otherwise permit. In some embodiments, the larger multiplication can have less than full precision. In other embodiments, the larger multiplication can have full precision by making use of some capabilities of a second DSP block.

Abstract: An integrated circuit wherein all elements such as a chip area, a cost, a function to change a logic, an operating frequency, flexibility, a throughput and electric power consumption can be improved; and a reconfigurable processor wherein a function of an instruction can be changed, are provided. A high-density logic reconfigurable leaf cell is defined. The integrated circuit is characterized in that: a logic reconfigurable leaf cell module, which is integrated with high density by arranging a plurality of leaf cells regularly to minimize the connection channel area for a signal between the leaf cells, and the reconfigurable processor, which can change the function of an instruction set by inserting the logic reconfigurable leaf cell module into a data path of an instruction execution process circuit, are integrated.

Abstract: A Field Programmable Gate Array (FPGA) to implement channel equalization to mitigate group velocity dispersion in an optical system. In one embodiment, a mapping is loaded into the FPGA whereby the in-phase and quadrature components of the baseband sequence to be filtered are routed to accumulators to form various sums, where each sum is multiplied by a corresponding distinct filter tap coefficient value according to the mapping to form various products, and where the products are summed to provide the in-phase and quadrature components of the filtered output.

Abstract: A method for an FPGA includes coupling a first electrode of a first resistive element to a first input voltage, coupling a second electrode of a second resistive element to a second input voltage, applying a first programming voltage to a shared node of a second electrode of the first resistive element, a first electrode of the second resistive element, and to a gate of a transistor element, and changing a resistance state of the first resistive element to a low resistance state while maintaining a resistance state of the second resistive element, when a voltage difference between the first programming voltage at the second terminal and the first input voltage at the first terminal exceeds a programming voltage associated with the first resistive element.

Abstract: A reconfigurable circuit of the present invention is characterized in being provided with: a first programmable wiring group, which is disposed in the first direction; a second programmable wiring group, which is disposed in the second direction that intersects the first direction; a first switch element array, which connects the programmable wiring groups to each other at the intersecting points of the first programmable wiring group and the branch line group of a functional block input wiring group or at the intersecting points of the branch line group of the first programmable wiring group and the functional block input wiring group; a second switch element array, which connects the programmable wiring groups to each other at the intersecting points of the first programmable wiring group and functional block output wiring; and a third switch element array, which connects the programmable wiring groups to each other at the intersecting points of the second programmable wiring group and the first programmabl

Abstract: Disclosed is a logic element (LE) that can provide a number of advantageous features. For example, the LE can provide efficient and flexible use of LUTs and input sharing. The LE may also provide for flexible use of one or more dedicated adders and include register functionality.

Abstract: A method of evaluating a layout cell for electrostatic discharge (ESD) protection can include identifying at least one feature of the layout cell for use in implementing an integrated circuit (IC) and comparing the at least one feature of the layout cell to an ESD requirement for the IC. The method can include indicating whether the feature of the layout cell complies with the ESD requirement.

Abstract: A nonvolatile programmable logic switch according to an embodiment includes first and second cells, each of the first and second cells including: a first memory having a first to third terminals, the third terminal being receiving a control signal; a first transistor connected at one of source/drain to the second terminal; and a second transistor connected at a gate to the other of the source/drain of the first transistor, the third terminal of the first memory in the first cell and the third terminal of the first memory in the second cell being connected in common. When conducting writing into the first memory in the first cell, the third terminal is connected to a write power supply generating a write voltage, the first terminals in the first and second cells are connected to a ground power supply and a write inhibit power supply generating a write inhibit voltage respectively.

Abstract: A configurable logic block (CLB) and an operation method of the CLB are provided. The CLB includes memory units and a selecting circuit. The memory unit includes a first resistive non-volatile memory (RNVM) element and a second RNVM element. Top electrodes (TEs) of the first and second RNVM elements are coupled to an output terminal of the memory unit. Bottom electrodes (BEs) of the first and second RNVM elements are respectively coupled to a first bias terminal and a second bias terminal of the memory unit. The selecting circuit selects one of the memory units according to an input logic value and determines an output logic value of the CLB according to an output logic value of the selected memory unit.

Abstract: A semiconductor device comprises: reconfigurable logic circuit that includes plurality of resistance change elements; logical configuration of the reconfigurable logic circuit being decided depending on whether each of plurality of resistance change elements is in first resistance state or in second resistance state whose resistance value is lower than resistance value of first resistance state; resistance value monitor circuit that includes resistance change element pre-programmed to the first resistance state; the resistance value monitor circuit detecting whether or not pre-programmed resistance change element retains the first resistance state; and controller that, in case it is detected that resistance change element provided in resistance value monitor circuit doe not retain first resistance state, applies voltage used in programming from second resistance state to first resistance state to resistance change element retaining first resistance states, out of plurality of resistance change elements provid

Abstract: A Field Programmable Gate Array (FPGA) to implement channel equalization to mitigate group velocity dispersion in an optical system. In one embodiment, a mapping is loaded into the FPGA whereby the in-phase and quadrature components of the baseband sequence to be filtered are routed to accumulators to form various sums, where each sum is multiplied by a corresponding distinct filter tap coefficient value according to the mapping to form various products, and where the products are summed to provide the in-phase and quadrature components of the filtered output.

Abstract: A low-power storage device is provided. The storage device includes a first transistor, a second transistor, a logic element, and a semiconductor element. The second transistor controls supply of a first signal to a gate of the first transistor. When the potential of a second signal to be input is changed from a first potential into a second potential lower than the first potential, the logic element changes the potential of a first terminal of the first transistor from a third potential lower than the second potential into the first potential after the logic element changes the potential of the first terminal of the first transistor from the second potential into the third potential. The semiconductor element has a function of making a second terminal of the first transistor floating. The first transistor includes a channel formation region in an oxide semiconductor film.

Abstract: Integrated circuits with repairable logic regions are provided. Each logic region may be organized into a predetermined number of rows of logic circuitry, one of which serves as a spare row. A repairable region may be operable in normal mode or redundant mode. In normal mode, the spare row is deactivated. When one of the logic region rows contains defective circuitry, that logic region is operated in redundant mode so that each row below the bad row is shifted down by one row and the spare row is engaged to serve as the last row to repair that region. Each row may include a multiplexer and an associated driver that drives a corresponding vertical routing segment from one row to the next. Each vertical routing segment has the option of being driven by its logically equivalent vertical wire in the immediate preceding row by configuring the corresponding multiplexer.

Abstract: A reconfigurable instruction cell array (RICA) includes a plurality of switch boxes. Each switch box includes an instruction cell and a switch fabric configurable according to a configuration word stored in a latch array for the switch box. The switch boxes are arranged into broadcast sets such that the latch arrays in each broadcast set receive a configuration word in parallel.

Abstract: Parasitic static leakage current through input terminals of bus-accessing multiplexers is minimized by automatically forcing as many as practical of the bus lines into a high impedance state where all drivers of the lines are in a high impedance output state. Thus parasitic current sinking or current sourcing leakage paths through the bus-accessing multiplexers are cut off. The method is of particular utility in a low power FPGA that desirable has low static current leakage when in a static state.