Abstract: The present invention provides a data transmission method including: sending, by a transmitter, a source data frame to a receiver, and saving the source data frame; sending, by the transmitter, other data frames to the receiver, and saving the other data frames; receiving, by the transmitter, a data retransmission notification which is related to the source data frame and sent by the receiver; and retrieving, by the transmitter, the source data frame and other data frames from a storage space, where the other data frames are sent by the transmitter to the receiver in a time period from sending the source data frame by the transmitter to receiving the data retransmission notification by the transmitter, and retransmitting the source data frame and the other data frames to the receiver.

Abstract: A semiconductor die includes at least one flexible interface block. The flexible interface block includes at least one interconnect, and at least one buffer coupled to the at least one interconnect. The flexible interface block further includes a routing interface coupled to circuitry integrated in the semiconductor die, and a controller coupled to provide communication between the routing interface and the at least one buffer.

Abstract: An integrated circuit (IC) and fabrication method thereof is provided that include the steps of specifying a plurality of required tile modules suitable for a particular end application, each of the modular tiles being configured to perform a predetermined function and constructed to have approximately the same length and width dimensions. The modular tiles are used to form the IC in a standard IC fabrication process. In many implementations, physical layout of the IC does not include the step of routing. Capabilities also include configuring the modular tiles to have programmable performance parameters and configuring the modular tiles to cooperate usefully with one another based on a programmable parameter.

Abstract: A reconfigurable logic device includes logic units and allows logic circuits to be formed according to configuration data. The logic units each include a configuration memory that stores first and second configuration data, a first address input line through which a clock is inputted as a first address for the configuration memory, a second address input line through which an input of a data input line is inputted as a second address for the configuration memory, a register unit that, according to the clock, reads the second configuration data specified by the first address from the configuration memory and retains the second configuration data, and outputs the first configuration data in a previous state, and a multiplexer that, according to the first or second configuration data outputted from the register unit, selectively combines a data input from the data input line and a data output to a data output line.

Abstract: According to an embodiment, a reconfigurable semiconductor integrated circuit includes first and second blocks. The first block includes first memories; and second memories; a selector selecting one first memory and one second memory; a first logic circuit whose logic is determined according to data read from the selected first memory; and a first switch circuit that is connected to first wires and switches connection between the first wires according to data read from the selected second memory, a part of the first wires being connected to the first logic circuit. The second block includes third and fourth memories; a second logic circuit whose logic is determined according to data read from the third memory; and a second switch circuit that is connected to second wires and switches connection between the second wires according to data read from the fourth memory, a part of the second wires being connected to the second logic circuit.

Abstract: Disclosed herein are semiconductor device arrays, such as, Field Programmable Gate Arrays (FPGAs) and Complex Programmable Logic Arrays (CPLAs) that use high-density Spin Transfer Torque (STT)-based memory elements. STT-based memory elements can either be stand-alone FPGAs/CPLAs, or can be embedded in microprocessors and/or digital signal processing (DSP) system-on-chip (SoC) to provide design flexibility for implementing low power, scalable, secure and reconfigurable hardware architecture. Because the configuration is stored on the FPGA/CPLA die itself, the need for loading the configuration from external storage every time is eliminated when the device is powered on. In addition to instant startup, eliminating configuration I/O traffic results in power savings and possible pin count reduction. Security is greatly improved by eliminating the need to store configuration data in an external memory.

Abstract: A device having a design conversion from a field programmable gate array (FPGA) to an application specific integrated circuit (ASIC), comprising: a user configurable element in the FPGA replaced by a mask configurable element in the ASIC, wherein the FPGA and the ASIC have identical die size and identical transistor layouts.

Abstract: A method and apparatus is disclosed herein for segmented and direct routing in a programmable gate array. In one embodiment, the programmable gate array comprises a plurality of programmable tiles, including at least one SHLRT having: a block configurable as a logic function or a routing function; and one or more switching blocks coupled to programmable tiles in the plurality of programmable tiles for segmented routing.

Abstract: A system for pipelining signal flow graphs by a plurality of shared memory processors organized in a 3D physical arrangement with the memory overlaid on the processor nodes that reduces storage of temporary variables. A group function formed by two or more instructions to specify two or more parts of the group function. A first instruction specifies a first part and specifies control information for a second instruction adjacent to the first instruction or at a pre-specified location relative to the first instruction. The first instruction when executed transfers the control information to a pending register and produces a result which is transferred to an operand input associated with the second instruction. The second instruction specifies a second part of the group function and when executed transfers the control information from the pending register to a second execution unit to adjust the second execution unit's operation on the received operand.

Abstract: In a multi-context PLD (dynamically reconfigurable circuit), at the tune of rewriting configuration data on a non-selected context during circuit operation, configuration data is stably stored. At the time of rewriting configuration data on a non-selected context, writing to a row which is to be rewritten continues until input signals supplied to input terminals of routing switches in the row become “L” all that time or the input signals become “L” at least once. More specifically, a write selection signal for the row continues to be output. In addition, while the write selection signal is being output, loading of configuration data into a driver circuit is not conducted, or loading of configuration data into a driver circuit is conducted but storage thereof in a line buffer is not conducted.

Abstract: An apparatus includes a multiple time programmable (MTP) memory device. The MTP memory device includes a metal gate, a substrate material, and an oxide structure between the metal gate and the substrate material. The oxide structure includes a hafnium oxide layer and a silicon dioxide layer. The hafnium oxide layer is in contact with the metal gate and in contact with the silicon dioxide layer. The silicon dioxide layer is in contact with the substrate material. The MTP device includes a transistor, and a non-volatile state of the MTP memory device is based on a threshold voltage of the transistor.

Abstract: An apparatus is disclosed herein for a programmable gate architecture with hybrid logic/routing circuitry. In one embodiment, a programmable gate array comprises a plurality of hybrid logic or routing tiles (HLRT), each of the HLRTs having a hybrid logic-or-routing function (HLR) that is configurable as a logic function or a routing function.

Abstract: Systems, mechanisms, apparatuses, and methods are disclosed for forwarding Inter-Switch Connection (ISC) frames in a Network-to-Network Interconnect (NNI) topology, for example, via a network switch which includes a first physical switch port to receive a physical switch link from a second network switch; logic to implement a first logical ISC and a second logical ISC? connection to the second network switch via the physical switch link; a second physical switch port to receive an interface connection from a third network switch; and switch forwarding logic to forward frames received at the first network switch to the second network switch via the logical ISC or logical ISC? based on whether or not the physical switch link is part of an active topology upon which the network switch operates or is not part of the active topology upon which the network switch operates. Other embodiments are disclosed.

Abstract: In an example, a configurable logic element for a programmable integrated circuit (IC) includes a first lookup-table (LUT) including first inputs and first outputs, and first sum logic and first carry logic coupled between the first inputs and the first outputs; a second LUT including second inputs and second outputs, and second sum logic coupled between the second inputs and the second outputs; and first and second cascade multiplexers respectively coupled to the first and second LUTs, an input of the second cascade multiplexer coupled to an output of the first carry logic in the first LUT.

Abstract: Systems and methods are provided for an interposer for coupling two or more integrated circuit dies to a circuit package. A first integrated circuit portion is disposed on a first location of a single semiconductor substrate. A second integrated circuit portion is disposed on a second location of the single semiconductor substrate, where the second integrated circuit portion is electrically isolated from the first integrated circuit portion along a first axis. The first and second integrated circuit portions are configured to provide an electrical coupling to two or more corresponding top die integrated circuits across a second axis that is perpendicular to the first axis.

Abstract: An integrated circuit can include a processor system configured to execute program code. The processor system can be hard-wired and include a processor hardware resource. The IC also can include a programmable circuitry configurable to implement different physical circuits. The programmable circuitry can be coupled to the processor system. The programmable circuitry can be configurable to share usage of the processor hardware resource of the processor system. The processor system further can control aspects of the programmable circuitry such as power on and/or off and also configuration of the programmable circuitry to implement one or more different physical circuits therein.

Abstract: Disclosed herein is a semiconductor integrated circuit including: a cell layout region including circuit cells subject to power control the supply and interruption of power to which is controlled by a power switch, and always-on circuit cell groups which are always powered after the activation; a main line laid out in the cell layout region and applied with a source or reference voltage; and first and second branch lines which branch from the main line in the cell layout region.

Abstract: A data and signal interface for controlling the transfer of data and signals between a memory array and macro function such as that of a digital signal processor (DSP) core. In one embodiment, the interface comprises a plurality of memory ports which interface with X/Y memory banks, a plurality of function ports, each with a function controller, which interface with DSP functions, a crossbar connecting the memory and function ports, and an arbitration unit for arbitrating memory access by the function ports. The memory interface advantageously allows multiple simultaneous accesses of memory banks via a plurality of macro functions, each access under the control of a parent processor instruction. A standardized protocol used for memory read/write operations is also disclosed.

Abstract: A programmable semiconductor device includes a user programmable switch comprising a configurable element positioned above a transistor material layer deposited on a substrate layer.

Abstract: Disclosed is a programmable logic device (PLD) which can undergo dynamic configuration at a high speed. The PLD includes a plurality of programmable logic elements (PLEs) and a switch for selecting electrical connection between the PLEs. The switch includes a plurality of circuit groups each of which includes first and second transistors. The second transistors of the circuit groups are electrically connected in parallel with one another. In each of the circuit groups, the electrical conduction between a source and a drain of the second transistor is determined based on configuration data held at a node between the gate of the second transistor and a drain of the first transistor, which allows the selection of the electrical connection and disconnection between the programmable logic elements by the selection of one of the circuit groups.

Abstract: Systems and methods for creating fingerprints for encryption devices are described herein. In various embodiments, the system includes an encryption device operatively connected to a device management system. According to particular embodiments, the device management system: 1) receives a first payload from the encryption device, the first payload including data in a particular format; 2) creates a fingerprint for the encryption device, the fingerprint including a section format for each of one or more distinct sections of the particular format; 3) storing a record of the fingerprint for the encryption device and the unique identifier at the at least one database; and 4) comparing a format of each subsequent payload received from the encryption device to the fingerprint for the device to determine whether the device has been compromised.

Abstract: Provided is a semiconductor device where a signal-transmission speed. The semiconductor device comprises a first logic element, a first switch electrically connected to the first logic element, and a second logic element electrically connected to the first switch. The first logic element includes at least a second switch, and the second switch has a function of setting an output potential from the first logic element to a L level. The first logic element may include a memory electrically connected to a register. The memory has a function of holding data of the register, and the register has a function of setting an output potential to a L level after holding the data in the memory.

Abstract: One embodiment relates to an integrated circuit including multiple PMA modules, a plurality of multiple-purpose PLLs, multiple reference clock signal inputs, and a programmable clock network. Each PMA module includes multiple CDR circuits, receives multiple serial data signals, and outputs data from those signals in parallel form. The programmable clock network allows the reference clock signals to be selectively shared by the PMA modules and the multiple-purpose PLLs. Another embodiment relates to a method of providing clock signals for multiple purposes in an integrated circuit. Clock signals are generated by a plurality of multiple-purpose PLLs and are selectively distributed to PMA modules arranged at a side of the integrated circuit and to logic circuitry arranged in a core section of the integrated circuit. The clock signals are used by circuitry in the PMA modules for supporting a plurality of data communications channels. Other embodiments and features are also disclosed.

Abstract: A plurality of functional elements are all located on a same integrated circuit wherein at least one of the functional elements comprises a micro-controller. A configuration data store in the integrated circuit stores configuration values loaded by the micro-controller. A plurality of connectors are configured to connect the integrated circuit to external signals. A programmable interconnect also located in the integrated circuit programmably connects together the plurality of functional elements and the plurality of connectors according to the configuration values loaded into the configuration data store.

Abstract: A system and method optimizes hardware description generated from a graphical program or model automatically. The system may include a streaming optimizer, a resource sharing optimizer and a delay balancing engine. The streaming optimizer transforms one or more vector data paths in the source model to scalar data paths or to a smaller-sized vector data paths. The resource sharing optimizer may replace multiple blocks of the source model that are functionally equivalent with a single shared block. The streaming and resource sharing optimizers may also configure portions of the modified model to execute at a faster rate. The delay balancing engine may examine the modified model to determine whether any delays or latencies have been introduced. If so, the delay balancing engine may insert one or more blocks into the modified model to correct for any data path misalignment caused by the introduction of the delays or latencies.

Abstract: [Object] A novel programmable logic device is provided. [Solution] Programmable switches each include a first transistor and a second transistor. The first transistor in a first programmable switch controls conduction between a first wiring and a gate of the second transistor in the first programmable switch. The second transistor in the first programmable switch controls conduction between the first wiring and a second wiring. The first transistor in the second programmable switch controls conduction between another first wiring and a gate of the second transistor in the second programmable switch.

Abstract: A three-dimensional semiconductor device, comprising: a first module layer having a plurality of circuit blocks; and a second module layer positioned substantially above the first module layer, including a plurality of configuration circuits; and a third module layer positioned substantially above the second module layer, including a plurality of circuit blocks; wherein, the configuration circuits in the second module control a portion of the circuit blocks in the first and third module layers.

Abstract: An integrated circuit includes a substrate having a plurality of electronic devices, a plurality of interconnect layers disposed on one or both sides of the substrate, and a plurality of active electrically conductive interconnect layer structures. The plurality of interconnect layers include horizontal interconnect and vertical-interconnect-access (VIA) layers. The plurality of active electrically conductive interconnect layer structures are disposed on at least one of the plurality of interconnect layers and electrically coupled with at least one of the plurality of electronic devices. The integrated circuit also includes a plurality of spare electrically conductive interconnect layer structures disposed on at least one of the plurality of interconnect layers and electrically isolated from the plurality of active electrically conductive interconnect layer structures.

Abstract: Clock distribution circuitry for a structured ASIC device includes a deterministic portion and configurable portions. The deterministic portion employs a predetermined arrangement of conductor segments and buffers for distributing a clock signal to a plurality of predetermined locations on the device. From each predetermined location, an associated configurable portion of the clock distribution circuitry distributes the clock signal to any clock utilization circuitry needing that clock signal in a predetermined area of the structured ASIC that is served from that predetermined location.

Abstract: Methods and apparatus are provided for implementing circuitry operable to perform barrel shifting, multiplication, and rotation operations in hard coded logic on a programmable chip. A hard coded multiplier is augmented using multiplexer circuitry, a logical operation, and a bypassable 2^N functional block. Based on control signals, the multiplexer circuitry can be used to select a rotation, multiplication, or barrel shifted output. Multiplexer control signals also provide sign information associated with operands passed to the multiplier. A single augmented multiplier can perform barrel shifting, rotation, or multiplication operations. Inputs of a multiplier can also be selectively grounded to allow the multiplier to perform logic operations.

Abstract: An integrated circuit is disclosed. The integrated circuit may include an interface circuit region and logic circuitry region. The interface circuit region includes interface circuits that transfers signals in and out of the integrated circuit. The logic circuitry region includes logic circuitry that is configured to implement a logic function. The logic circuitry region surrounds the interface circuit region from at least two sides, from at least three sides, or from all four sides.

Abstract: A method and apparatus for a radio base station (300) aligns IQ data blocks for transmission over multiple radio frequency (RF) signal paths (318, 328, 338) between a base station controller (304) and a plurality of antennas (340) at the base station by determining a path delay (317, 327, 337) for each RF signal path, and then transmitting IQ data blocks from JESD 204 transmit interfaces (301-303) over each RF signal path ahead of a first predetermined time slot by an advance time period equaling the path delay for each RF signal path, thereby aligning IQ data block signaling to the first predetermined time slot at the antennas.

Abstract: Circuits, methods, and apparatus that prevent detection and erasure of encoding or encryption keys. These encoding keys may be used to encode a configuration bitstream or other data for an FPGA or other device. An exemplary embodiment of the present invention masks a first key to form an encoding key in order to prevent detection of the first key. In a specific embodiment, the first key is encoded using a second key. The encoded key is used to encode a configuration bitstream or other data. The encoded key is stored on an FPGA or other device. When the device is to be configured, the encoded key is retrieved and used to decode the bitstream or other data. A further embodiment stores an encryption key in a one-time programmable memory (OTP) array to prevent its erasure or modification. The encoding key may be further obfuscated before storage.

Abstract: An approach is presented for managing resources of a field-programmable gate array (FPGA). At runtime, first data is extracted and processed. At runtime and via a very high speed integrated circuit hardware description language (VHDL) interface, a change in a size, a structure, or a load schedule of next data is received. The change is determined by a quantitative method analyzing the first data and executing external to the FPGA. At runtime, a first bootstrap code in the FPGA executes, and in response, other bootstrap codes in the FPGA are updated. The first bootstrap code is configured to update the structure of the next data. The other bootstrap codes are configured to extract and process, and to determine an order of processing and a configuration of the next data. The next data is extracted and processed based on the updated other bootstrap codes.

Abstract: Providing for a field programmable gate array (FPGA) utilizing resistive random access memory (RRAM) technology is described herein. By way of example, the FPGA can comprise a switching block interconnect having parallel signal input lines crossed by perpendicular signal output lines. RRAM memory cells can be formed at respective intersections of the signal input lines and signal output lines. The RRAM memory cell can include a voltage divider comprising multiple programmable resistive elements arranged electrically in series across a VCC and VSS of the FPGA. A common node of the voltage divider drives a gate of a pass gate transistor configured to activate or deactivate the intersection. The disclosed RRAM memory can provide high transistor density, high logic utilization, fast programming speed, radiation immunity, fast power up and significant benefits for FPGA technology.

Abstract: A scan flip-flop for generating an output signal based on a first input signal, a clock signal, a test input signal, a Launch On Shift (LOS) signal, a test enable signal, and a reset signal includes a logic circuit, a multiplexer and a flip-flop circuit. The logic circuit receives an inverted clock signal, the test enable signal, a intermediate test enable signal, and the LOS signal, and generates an intermediate output signal that is an inherent LOS scan enable signal. The multiplexer receives the test input signal and the intermediate output signal, and outputs the test input signal. The flip-flop circuit receives the test input signal as a second input signal, the clock signal, and the reset signal, and generates the output signal.

Abstract: Systems and methods described herein are directed to solutions for Network on Chip (NoC) interconnects that automatically and dynamically determines the position of hosts of various size and shape in a NoC topology based on the connectivity, bandwidth and latency requirements of the system traffic flows and certain performance optimization metrics such as system interconnect latency and interconnect cost. The example embodiments selects hosts for relocation consideration and determines a new possible position for them in the NoC based on the system traffic specification, shape and size of the hosts and by using probabilistic function to decide if the relocation is carried out or not. The procedure is repeated over new sets of hosts until certain optimization targets are satisfied or repetition count is exceeded.

Abstract: A circuit design is created in a computer memory in response to user input to a computer processor. The circuit design has a static portion. A virtual socket is instantiated in the circuit design in response to user input, and one or more reconfigurable modules are instantiated in the virtual socket in response to user input. The static portion of the circuit design is coupled to the one or more reconfigurable modules, and configuration data are generated from the circuit design. The configuration data include a configuration bitstream corresponding to the static portion of the circuit design and one or more partial configuration bitstreams corresponding to the one or more reconfigurable modules.

Abstract: A sub-VT FPGA uses a low swing, dual-VDD interconnect scheme to reduce FPGA area per LUT, delay at a constant energy, and energy at a constant delay relative to a conventional design at low voltage. These improvements are made possible by a custom asynchronous sense amp, a separated voltage for memory cells, and an improved passgate interconnect to optimize routing delay with low energy overhead. This sub-threshold FPGA design enables energy efficient and cost effective configurable logic for a wide variety of ULP applications.

Abstract: The invention uses a new process called dynamic pin reassignment (DPR) to alter the circuitry. The system assigns input and output signals to buses that lead to a central distribution point, the crossbar, in the circuit. At the crossbar, signals are routed to the appropriate destination over one of the bus wires to the correct chip from the crossbar. At irregular intervals, the signal mapping for each in/out function is changed. The assignments or mappings, comprise the state of the circuit at any time. The period that a state is valid is determined by applying a reseeding function to a portion of a randomized stream that calculates the next state and the duration of validity. Multiple seeds or keys are used to create the states. Because each key changes independently of the other keys and without notice, the time interval for a valid state is greatly reduced, complicating any effort to reveal the internal states of chips.

Abstract: Various structures and methods are disclosed related to routing and programming circuitry on integrated circuits (“IC”) that have arrays of programmable resistive switches. In some embodiments, routing structures utilize densely populated resistive switch arrays to provide for efficient selection circuits that route into and out of logic regions. In other embodiments, programming circuitry is provided to help maintain relatively consistent programming current throughout an array of resistive switches to be programmed. In other embodiments, methods are provided for programming resistive switches without violating given power constraints. These and other embodiments are described further herein.

Abstract: A low power sub-cycle reconfigurable conduit is provided. The low power reconfigurable conduit is a clocked storage element that consumes less power when performing low-throughput operations that do not require sub-cycle rate. The low power conduit includes a first configurable routing multiplexer that is reconfigurable to select one of several inputs at a first clock rate. The low power conduit also includes an array of storage elements for storing output data from the configurable routing multiplexer at the first clock rate. Each storage element in the array of storage elements operate at a second clock rate that is slower than the first clock rate. Each storage element receives a different phase of a clock that operates at the second clock rate. The low power conduit also includes a second configurable routing multiplexer that is reconfigurable to select from the array of storage elements at the first clock rate.

Abstract: A system and method for reducing power consumption in a reconfigurable integrated circuit. Some embodiments provide placement and routing programs that reduce the number of bits to be reconfigured. Some embodiments provide placement and routing programs that increase the number of groups of circuits that do not need reconfiguration at some times. Some embodiments include circuits that selectively block reconfiguration.

Abstract: An integrated circuit (IC) and fabrication method thereof is provided that include the steps of specifying a plurality of required tile modules suitable for a particular end application, each of the modular tiles being configured to perform a predetermined function and constructed to have approximately the same length and width dimensions. The modular tiles are used to form the IC in a standard IC fabrication process. In many implementations, physical layout of the IC does not include the step of routing. Capabilities also include configuring the modular tiles to have programmable performance parameters and configuring the modular tiles to cooperate usefully with one another based on a programmable parameter.

Abstract: A circuit includes a first buffer configured to provide data on a signal line. The first buffer may be powered by a first power supply voltage. The circuit further includes a tri-state buffer coupled to receive the data provided on the signal line. The tri-state buffer may be powered by a second power supply voltage that has a magnitude greater than that of the first power supply voltage. During operation, the tri-state buffer may be activated for a predetermined period of time during which data is made available on the signal line.

Abstract: A finite state machine is provided that both serializes virtual GPIO signals and deserializes virtual GPIO signals responsive to cycles of an external clock. The finite state machine frames the serialized virtual GPIO signals into frames each demarcated by a start bit and an end bit.

Abstract: Disclosed are methods and devices, among which is a device that includes a finite state machine lattice. The lattice may includes a programmable Boolean logic cell that may be programmed to perform various logic functions on a data stream. The programmability includes an inversion of a first input to the Boolean logic cell, an inversion of a last output of the Boolean logic cell, and a selection of an AND gate or an OR gate as a final output of the Boolean logic cell. The Boolean logic cell also includes end of data circuitry configured to cause the Boolean logic cell to only output after an end of data signifying the end of a data stream is received at the Boolean logic cell.

Abstract: One embodiment relates to a circuit for pipelined direct-drive routing, the circuit including a routing multiplexer, a flip-flop, and a mode multiplexer. The output of the routing multiplexer is coupled to an input of the mode multiplexer and to the flip-flop. The output of the flip-flop is connected to another input of the mode multiplexer. The flip-flop may be directly connected to the routing multiplexer and the mode multiplexer, or, in an alternate embodiment, the flip-flop may be a member of a pipeline register pool. Another embodiment relates to a circuit for pipelined direct-drive routing which uses a pulse latch. Other embodiments relate to method for pipelined direct-drive routing which includes a degree of logical separation between logic elements and flip-flop elements. Another embodiment relates to a logic array block. Other embodiments, aspects, and features are also disclosed.

Abstract: The present invention comprises a system and method for providing a distributed wireless network. In a preferred embodiment, at least one information processor is coupled to and accessible over a communication network, such as the internet. Network bandwidth is provided to a first user of at least two end users for a first fee and to a second user of the at least two end users for a second fee. The bandwidth is provided by at least one network service provider. Further, at least two wireless gateway devices are each respectively operated by the end users, and the wireless gateway devices are configured to provide wireless access to the communication network within a transmission range and to communicate with the at one least information processor. Also, at least two wireless receiving devices are provided that are operable to receive the respective bandwidth from the at least two wireless gateway devices when in transmission range.

Abstract: A method and apparatus to provide a power segmentation architecture that substantially eliminates the routing and area penalties associated with conventional power segmentation architectures. Power switching components are configured within the external interconnect portion of the integrated circuit (IC) to reduce the number of inter-layer interconnects that must be traversed in order to programmably supply operational power to the various device segments of the IC. A system-in-package (SIP) integration approach is alternately taken, whereby the power switching components utilized within the power segmentation architecture are conveniently allocated among the base or stacked die to reduce the number of inter-layer interconnects. The power switching components may also be implemented off-chip as discrete switching components such as a transistor or a micro-miniature switch/relay.