Complementary Fet's Patents (Class 326/45)
  • Patent number: 10970453
    Abstract: The method for creating integrated circuits (IC) protects the design of a manufactured IC from being copied or counterfeited. This method protects the design of an IC chip from deliberate copying and counterfeiting by reverse engineering to gain access to the critical points in the IC chip and to siphon its functions and design. The method makes the copying, counterfeiting, and controlling by addition of Trojan circuits during manufacturing almost impossible task. It also allows chip designers to outsource the final bonding of the tiers without any fears that their design may get compromised.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: April 6, 2021
    Assignee: University of Louisiana at Lafayette
    Inventors: Siroos Madani, Mohammad R. Madani, Magdy Bayoumi
  • Patent number: 10664643
    Abstract: The method for creating integrated circuits (IC) protects the design of a manufactured IC from being copied or counterfeited. This method protects the design of an IC chip from deliberate copying and counterfeiting by reverse engineering to gain access to the critical points in the IC chip and to siphon its functions and design. The method makes the copying, counterfeiting, and controlling by addition of Trojan circuits during manufacturing almost impossible task. It also allows chip designers to outsource the final bonding of the tiers without any fears that their design may get compromised.
    Type: Grant
    Filed: February 7, 2019
    Date of Patent: May 26, 2020
    Assignee: University of Louisiana at Lafayette
    Inventors: Siroos Madani, Mohammad R. Madani, Magdy Bayoumi
  • Patent number: 9575111
    Abstract: A system configured for detecting electrical overstress events within an integrated circuit includes a comparator configured to determine whether a monitored voltage level of a monitored signal exceeds an overstress reference voltage level. The overstress reference voltage level is a predetermined amount of voltage above a nominal voltage level for the monitored signal. The system further includes a write circuit coupled to an output of the comparator. The write circuit is configured to indicate an occurrence of an electrical overstress event within the integrated circuit responsive to the comparator determining that the monitored voltage level exceeds the overstress reference voltage level.
    Type: Grant
    Filed: July 15, 2013
    Date of Patent: February 21, 2017
    Assignee: XILINX, INC.
    Inventors: James Karp, Michael J. Hart, John K. Jennings
  • Publication number: 20130293264
    Abstract: In an embodiment, a field programmable analog array (FPAA) comprises state variable filter engines arranged in parallel, each state variable filter engine comprising at least one variable attenuator and at least one variable integrator configured to operate on a wideband analog signal; and a summer configured to add outputs from the state variable filter engines.
    Type: Application
    Filed: November 1, 2011
    Publication date: November 7, 2013
    Applicant: NEWLANS, INC.
    Inventor: Dev V. Gupta
  • Publication number: 20120274355
    Abstract: An object of the present invention is to provide a programmable logic device which has short start-up time after supply of power is stopped, is highly integrated, and operates with low power. In a programmable logic device including an input/output block, a plurality of logic blocks each including a logic element, and a wiring connecting the plurality of logic blocks, the logic element has a configuration memory for holding configuration data and a look-up table including a selection circuit. The configuration memory includes a plurality of memory elements each of which includes a transistor whose channel region is in an oxide semiconductor film and an arithmetic circuit provided between the transistor and the selection circuit. Configuration data is selectively changed and output by the selection circuit in accordance with an input signal.
    Type: Application
    Filed: April 23, 2012
    Publication date: November 1, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Tatsuji NISHIJIMA
  • Publication number: 20120074984
    Abstract: A look-up table circuit according to an embodiment includes: a variable resistance circuit including variable resistance devices and selecting a variable resistance device from the variable resistance devices based on an input signal; a reference circuit having a resistance value between the largest resistance value and the smallest resistance value of the variable resistance circuit; a first n-channel MOSFET including a source connected to a terminal of the variable resistance circuit and a gate connected to a drain; a second n-channel MOSFET including a source connected to a terminal of the reference circuit and a gate connected to the gate of the first n-channel MOSFET; a first current supply circuit to supply a current to the variable resistance circuit; a second current supply circuit to supply a current to the reference circuit; and a comparator comparing voltages at a first input terminal and a second input terminal.
    Type: Application
    Filed: September 21, 2011
    Publication date: March 29, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hideyuki SUGIYAMA, Tetsufumi Tanamoto, Takao Marukame, Mizue Ishikawa, Tomoaki Inokuchi, Yoshiaki Saito
  • Patent number: 8138791
    Abstract: Integrated circuits with stressed transistors are provided. Stressing transistors may increase transistor threshold voltage without the need to increase channel doping. Stressing transistors may reduce total leakage currents. It may be desirable to compressively stress N-channel metal-oxide-semiconductor (NMOS) transistors and tensilely stress P-channel metal-oxide-semiconductor (PMOS) transistors to reduce leakage currents. Techniques that can be used to alter the amount of stressed experienced by transistors may include forming a stress-inducing layer, forming a stress liner, forming diffusion active regions using silicon germanium, silicon carbon, or standard silicon, implementing transistors in single-finger instead of multi-finger configurations, and implanting particles. Any combination of these techniques may be used to provide appropriate amounts of stress to increase the performance or decrease the total leakage current of a transistor.
    Type: Grant
    Filed: January 27, 2010
    Date of Patent: March 20, 2012
    Assignee: Altera Corporation
    Inventors: Albert Ratnakumar, Jun Liu, Jeffrey Xiaoqi Tung, Qi Xiang
  • Patent number: 7725870
    Abstract: A logic book for a programmable device such as an application-specific integrated circuit (ASIC) achieves improved radiation tolerance by providing notches in an implant well between adjacent transistors and fills the notches with complementary well regions that act as a barrier to charge migration. For example, a row of n-type field effect transistors (NFETs) is located in a Pwell region, while a row of p-type transistors is located in an Nwell region with portions of the Nwell region extending between the NFETs. More complicated embodiments of the present invention include embedded well islands to provide barriers for adjacent transistors in both rows of the book.
    Type: Grant
    Filed: August 14, 2007
    Date of Patent: May 25, 2010
    Assignee: International Business Machines Corporation
    Inventors: Mark R. Beckenbaugh, AJ KleinOsowski, Eric J. Lukes
  • Patent number: 7698681
    Abstract: A logic book for a programmable device such as an application-specific integrated circuit (ASIC) achieves improved radiation tolerance by providing transistors of the same doping type in different well regions that are physically isolated by intervening well regions with complementary doping. For example, n-type field effect transistors (NFETs) may be located in two outer rows of the book with separate Pwell regions, while p-type transistors are located in two inner rows of the book sharing a common Nwell region. Since the NFETs in separate wells are physically isolated from each other, a circuit structure which uses two NFETs in the two outer rows is much less likely to suffer multiple upsets from a single radiation strike. More complicated embodiments of the present invention include additional transistor rows in the stack with isolated Nwells and Pwells.
    Type: Grant
    Filed: August 14, 2007
    Date of Patent: April 13, 2010
    Assignee: International Business Machines Corporation
    Inventors: Mark R. Beckenbaugh, AJ KleinOsowski, Eric J. Lukes, Byron D. Scott
  • Patent number: 7671624
    Abstract: A packaged PLD solution includes a first die having a masked-Read Only Memory (ROM) that is programmed during its fabrication to store configuration data, and includes a second die having a PLD including a number of configurable resources collectively configured to implement a circuit design embodied by the configuration data. The first die is electrically connected to the second die, and both the first die and second die are stacked and encapsulated together to form the packaged PLD solution. The configuration data is programmed into the masked-ROM by a manufacturer of both the masked-ROM and the PLD.
    Type: Grant
    Filed: October 10, 2006
    Date of Patent: March 2, 2010
    Assignee: XILINX, Inc.
    Inventor: James A. Walstrum, Jr.
  • Publication number: 20090273367
    Abstract: An integrated circuit (IC) includes at least one programmable digital logic cell that includes first dedicated digital logic cell having a plurality of transistors including at least one PMOS transistor and at least one NMOS transistor configured to perform at least one digital logical function. The first dedicated digital logic cell includes a plurality of nodes including at least one input node and at least one output node that reflects performance of a digital logical function. Programmable tuning circuitry includes at least one tuning input and at least one tuning circuit output. Circuitry for coupling or decoupling the tuning input or tuning circuit output to at least one of the plurality of nodes of the first dedicated digital logical cell is provided, wherein the coupling or decoupling is operable to change the processing speed for the first reprogrammable digital logic cell.
    Type: Application
    Filed: April 30, 2009
    Publication date: November 5, 2009
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: CLIVE D. BITTLESTONE, KIT WING S. LEE, EKANAYAKE A. AMERASEKERA, ANUJ BATRA, SRINIVAS LINGAM
  • Publication number: 20090167343
    Abstract: Devices and methods are disclosed for logic gate devices to provide reduced leakage while improving performance. The device is configured for low leakage logic application where high threshold voltage devices are used to reduce leakage at the expense of reduced logic speed. Better performance is achieved than a high threshold voltage stack.
    Type: Application
    Filed: December 29, 2007
    Publication date: July 2, 2009
    Inventor: Andrew Marshall
  • Publication number: 20090045840
    Abstract: A logic book for a programmable device such as an application-specific integrated circuit (ASIC) achieves improved radiation tolerance by providing transistors of the same doping type in different well regions that are physically isolated by intervening well regions with complementary doping. For example, n-type field effect transistors (NFETs) may be located in two outer rows of the book with separate Pwell regions, while p-type transistors are located in two inner rows of the book sharing a common Nwell region. Since the NFETs in separate wells are physically isolated from each other, a circuit structure which uses two NFETs in the two outer rows is much less likely to suffer multiple upsets from a single radiation strike. More complicated embodiments of the present invention include additional transistor rows in the stack with isolated Nwells and Pwells.
    Type: Application
    Filed: August 14, 2007
    Publication date: February 19, 2009
    Inventors: Mark R. Beckenbaugh, AJ KleinOsowski, Eric J. Lukes, Byron D. Scott
  • Publication number: 20090045841
    Abstract: A logic book for a programmable device such as an application-specific integrated circuit (ASIC) achieves improved radiation tolerance by providing notches in an implant well between adjacent transistors and fills the notches with complementary well regions that act as a barrier to charge migration. For example, a row of n-type field effect transistors (NFETs) is located in a Pwell region, while a row of p-type transistors is located in an Nwell region with portions of the Nwell region extending between the NFETs. More complicated embodiments of the present invention include embedded well islands to provide barriers for adjacent transistors in both rows of the book.
    Type: Application
    Filed: August 14, 2007
    Publication date: February 19, 2009
    Inventors: Mark R. Beckenbaugh, AJ KleinOsowski, Eric J. Lukes
  • Publication number: 20080265937
    Abstract: A technique that unfolds the nMOS-tree multiplexer to improve the propagation delay and/or active power consumption is provided. The main idea is to replicate the nMOS element of the downstream buffer, where each replica is driven by a signal that originates from earlier stages of the nMOS-tree multiplexer. This way, when passing high logic values, signals from earlier stages directly drive the downstream buffer improving the delay or the slope of the transition edge (with beneficial effects for power consumption). The passing of low logic values is still performed in the original way by the nMOS tree and the pMOS element of the downstream buffer.
    Type: Application
    Filed: April 7, 2008
    Publication date: October 30, 2008
    Inventors: Mihai Sima, Scott Alexander Miller, Michael Liam McGuire
  • Publication number: 20080136447
    Abstract: A logic gate is described that implements complex logic within a memory array. The logic gate receives at least three of a first storage cell signal, a second storage cell signal, a first external signal, or a second external signal at a first input circuitry and second input circuitry. The logic gate then performs one of a set of logic functions using the first storage cell signal, the second storage cell signal, the first external signal, or the second external signal. The set of logic functions includes at least one of a matching function, an OR-AND function, or an AND function.
    Type: Application
    Filed: December 6, 2006
    Publication date: June 12, 2008
    Inventors: Andrew James Bianchi, Jose Angel Paredes
  • Patent number: 7099395
    Abstract: A pseudo-differential signaling system uses a plurality of signal lines and a single, common reference voltage. Signal line voltages are interpreted only in comparison to the reference line voltage. Within a receiving circuit, the reference line is buffered prior to its distribution to multiple comparators. The system utilizes an active buffer having a bandwidth that is significantly greater than the resonant input frequency of the receiving circuit. In an alternative embodiment, the signal lines are also buffered. In this embodiment, the buffers are implemented with transistor-based source-followers. The buffer associated with the reference line has a larger current capacity than the buffers associated with the signal lines. In yet another embodiment, a comparator produces a correction signal that is equal to the noise present on the signal lines. This noise is then subtracted from the signal voltages.
    Type: Grant
    Filed: November 7, 2000
    Date of Patent: August 29, 2006
    Assignee: Rambus Inc.
    Inventors: Stefanos Sidiropoulos, Yingxuan Li, Mark A. Horowitz
  • Patent number: 6946875
    Abstract: A universal logic module that may have a reduced off-leak current in universal logic cells (100) not used as logic circuits has been disclosed. A universal logic module may include universal logic cells (100) that may be formed with a second wiring for connecting universal logic cells (100) from a base configuration formed with a first wiring. Unused universal logic cell (100) may include transistors in basic cells (A to E) that are non-connected to a power supply (VDD) and/or a ground potential (VSS). Furthermore, unused universal logic cell (100) may include transistors in basic cells (A to E) that may provide a capacitor between a power supply (VDD) and a ground potential (VSS). In this way, off-leak current may be reduced and noise on a power line and/or a ground line may be reduced.
    Type: Grant
    Filed: December 19, 2002
    Date of Patent: September 20, 2005
    Assignee: NEC Electronics Corporation
    Inventors: Kenji Yamamoto, Masaharu Mizuno, Kazuhiro Nakajima
  • Patent number: 6882177
    Abstract: A programmable logic device architecture including tristate structures. The programmable logic device architecture provides tristate structures which may be logically or programmably controlled, or both. Through these tristate structures, the logic elements may be coupled to the programmable interconnect, where they may be coupled with other logic elements of the programmable logic device. Using these tristate structures, the signal pathways of the architecture may be dynamically reconfigured.
    Type: Grant
    Filed: April 10, 2001
    Date of Patent: April 19, 2005
    Assignee: Altera Corporation
    Inventors: Srinivas Reddy, Richard G. Cliff
  • Patent number: 6831481
    Abstract: Area-efficient power-up and enable control circuits useful in PLD interconnection arrays. A control circuit can include a driver circuit, first and second pull-ups, and first and second pull-downs. The driver circuit has an output terminal coupled to a control circuit output terminal. The first and second pull-ups are coupled in series between the control circuit output terminal and power high. The first pull-up has a gate terminal coupled to an enable terminal. The second pull-up has a gate terminal coupled to a pull-up control terminal. The first and second pull-downs are coupled in parallel between the control circuit output terminal and ground. The first pull-down has a gate terminal coupled to the enable terminal. The second pull-down has a gate terminal coupled to a pull-down control terminal. In other embodiments, the first and second pull-ups are coupled in parallel, and the first and second pull-downs are coupled in series.
    Type: Grant
    Filed: March 14, 2003
    Date of Patent: December 14, 2004
    Assignee: Xilinx, Inc.
    Inventors: Andy T. Nguyen, Shankar Lakkapragada
  • Patent number: 6809550
    Abstract: A programmable logic device (PLD) architecture includes a plurality of PLD single-bit logic cells. Each single bit logic cell is comprised of all CMOS logic devices including a programmable cell unit, a settable latch, a signal path with inverter, and an output logic gate. The single path is coupled to the cell unit, the settable latch, and the output logic gate to create a positive feedback loop to improve speed and noise immunity. Each single bit logic gate is a basic building block for a modular low power consumption, high speed, zero DC current, high noise immunity programmable logic device (PLD) which includes an array of word lines and bit lines arranged in rows and columns for addressing, an array of OR gates, and a plurality of output logic circuits.
    Type: Grant
    Filed: September 20, 2002
    Date of Patent: October 26, 2004
    Assignee: Atmel Corporation
    Inventors: Saroj Pathak, James E. Payne, Victor V. Nguyen, Harry H. Kuo
  • Patent number: 6670201
    Abstract: A manufacturing method of a semiconductor device capable of obtaining highly reliable semiconductor devices with the realization of high integration and high speed intended is provided. During processes after a desired circuit including a CMOS static type circuit is formed on a semiconductor substrate until product shipment, a first operation of feeding a predetermined input signal to the circuit and retrieving a first output signal corresponding to it and a second operation of giving an operating condition of increasing an ON resistance value of MOSFETs constituting the CMOS static type circuit and retrieving a second output signal corresponding to the condition are conducted, and a testing step of determining a failure by the first output signal varying from the second output signal.
    Type: Grant
    Filed: August 28, 2001
    Date of Patent: December 30, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Masaki Kouno, Masato Hamamoto, Atsushi Wakahara, Hideyuki Takahashi, Keiichi Higeta, Mitsugu Kusunoki, Kazutaka Mori
  • Patent number: 6664806
    Abstract: A decoder for a memory device is provided. The decoder array includes a number of address lines and a number of output lines. The address lines and the output lines form an array. The decoder includes a number of vertical pillars extending outwardly from a semiconductor substrate at intersections of output lines and address lines. Each pillar includes a single crystalline first contact layer and a second contact layer separated by an oxide layer. The decoder further includes a number of single crystalline ultra thin vertical transistor that are selectively disposed adjacent the number of vertical pillars. Each single crystalline vertical transistor includes an ultra thin single crystalline vertical first source/drain region coupled to the first contact layer, an ultra thin single crystalline vertical second source/drain region coupled to the second contact layer, and an ultra thin single crystalline vertical body region which opposes the oxide layer and couples the first and the second source/drain regions.
    Type: Grant
    Filed: August 29, 2002
    Date of Patent: December 16, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Leonard Forbes, Kie Y. Ahn
  • Patent number: 6552566
    Abstract: Logic array circuits are formed on SOI substrates. The pull-down network (130) of the logic array circuit comprises NMOS transistors (125) and PMOS transistors (120) configured in series.
    Type: Grant
    Filed: August 20, 2001
    Date of Patent: April 22, 2003
    Assignee: Texas Instruments Incorporated
    Inventor: Xiaowei Deng
  • Patent number: 6462583
    Abstract: Briefly, in accordance with one embodiment of the invention, an integrated circuit includes: a gate array architecture. The gate array architecture includes at least one base site, the at least one base site being three tracks wide and including four N-type transistors and four P-type transistors. Briefly, in accordance with another embodiment of the invention, a method of fabricating an integrated circuit chip includes: processing a semiconductor substrate to form a gate array architecture of transistors in the substrate. The gate array architecture includes at least one base site being three tracks wide and including four N-type transistors and four P-type transistors.
    Type: Grant
    Filed: July 24, 2001
    Date of Patent: October 8, 2002
    Assignee: Intle Corporation
    Inventor: Randy J. Aksamit
  • Patent number: 6384624
    Abstract: The present invention has as an object thereof to provide a logical operational circuit which is capable of realizing, with present semiconductor manufacturing technology, logical functions, the realization of which has been extremely difficult heretofore as a result of constraints in the voltage levels which are to be discriminated on the floating gate of the neuMOS.
    Type: Grant
    Filed: October 10, 1997
    Date of Patent: May 7, 2002
    Inventors: Hiroto Yasuura, Kenjiro Ike
  • Publication number: 20020027446
    Abstract: The addition of an array of transistors through areas of the circuit where active devices normally don't exist, such as under routing channels. By connecting this array of transistors such that the gates are tied to one power supply and the sources and drains to another, the transistors act as bypass capacitors between the power supplies and act to reduce noise on the supplies. Also, the transistors may later be reconnected through changes in the design to form diodes, inverters, buffers, or other logic gates to allow changes to the circuit late in the design cycle.
    Type: Application
    Filed: April 5, 2001
    Publication date: March 7, 2002
    Inventor: James O. Barnes
  • Patent number: 6346827
    Abstract: A programmable input/output circuit for a programmable logic device input/output pin can be configured in a standard I/O mode, or in a reference voltage mode. The circuit includes a tristatable, but otherwise standard I/O buffer as well as a reference voltage clamp circuit. In reference voltage mode, the I/O circuit is tristated, and the reference voltage clamp circuit passes a reference voltage from the I/O pin to a reference voltage bus. In standard I/O mode, the I/O buffer is operational. The reference voltage clamp circuit isolates the I/O pin from the reference voltage bus and may include undervoltage and overvoltage protection to prevent disturbance of the reference voltage bus by an out-of-range I/O signal.
    Type: Grant
    Filed: August 4, 1999
    Date of Patent: February 12, 2002
    Assignee: Altera Corporation
    Inventors: Wayne Yeung, Chiakang Sung, Myron W. Wong, Khai Nguyen, Bonnie I. Wang, Xiaobao Wang, Joseph Huang, In Whan Kim
  • Patent number: 6314549
    Abstract: The present invention provides novel power saving methods for programmable logic array (PLA) circuits. One method is to store the results of a previous PLA operation, and bypass a new operation if the inputs are the same as previous operation. Another method is to reset the PLA outputs when the correct results can be achieved by resetting output latches. A large PLA is divided into smaller sub-PLA's while individual sub-PLA's are controlled separately. It is therefore possible to save power by bypassing unrelated sub-PLA's. PLA's of the present invention consume less power than equivalent prior art PLA's by orders of magnitudes. For most cases, PLA's of the present invention also have better performance and better cost efficiency. The design procedures are completely controlled by user-friendly computer aid design tools. The regular structures of PLA and the simplicity in connections allow us to avoid RC effects of conductor lines.
    Type: Grant
    Filed: January 9, 1998
    Date of Patent: November 6, 2001
    Inventor: Jeng-Jye Shau
  • Patent number: 6236232
    Abstract: The addition of an array of transistors through areas of the circuit where active devices normally don't exist, such as under routing channels. By connecting this array of transistors such that the gates are tied to one power supply and the sources and drains to another, the transistors act as bypass capacitors between the power supplies and act to reduce noise on the supplies. Also, the transistors may later be reconnected through changes in the design to form diodes, inverters, buffers, or other logic gates to allow changes to the circuit late in the design cycle.
    Type: Grant
    Filed: October 15, 1999
    Date of Patent: May 22, 2001
    Assignee: Agilent Technologies, Inc.
    Inventor: James Oliver Barnes
  • Patent number: 6222383
    Abstract: A programmable logic array (PLA) AND plane receives data input signals from input registers and generates corresponding minterms. The minterms are OR-ed together to form a sum of products, which are provided to output latches and clocked out before the end of each clock cycle by an internal self-timed signal as PLA output data. The OR plane (or the AND plane, or both) includes NOR gates that include a plurality of NMOS transistors. Each NMOS transistor in a gate has its drain connected to a common NOR gate output node, its source connected to ground and its gate connected to receive a corresponding minterm from the AND plane.
    Type: Grant
    Filed: December 26, 1996
    Date of Patent: April 24, 2001
    Assignee: Micro Magic, INc.
    Inventors: David Minoru Murata, Mark Ronald Santoro, Lee Stuart Tavrow
  • Patent number: 6154049
    Abstract: A programmable logic device, such as a field programmable gate array (FPGA) which includes an array of configurable logic elements (CLEs) and a corresponding array of multiplier tiles. The CLEs can be operated as conventional configurable logic elements, completely disconnected from the array of multiplier tiles. However, selected CLEs can also be coupled to selected multiplier tiles, thereby creating a relatively high density multiplier circuit. Each of the multiplier tiles includes a multiplier array having a predetermined size (e.g., a 2.times.4 bit multiplier array). The multiplier tiles can be selectively coupled to one another, such that the multiplier arrays are connected to form a relatively large multiplier circuit. The desired multiplier and multiplicand bits are routed into the multiplier tiles from associated CLEs. Similarly, the resulting product bits are routed from the multiplier tiles to associated CLEs.
    Type: Grant
    Filed: March 27, 1998
    Date of Patent: November 28, 2000
    Assignee: Xilinx, Inc.
    Inventor: Bernard J. New
  • Patent number: 6124729
    Abstract: A field programmable logic array with vertical transistors having single or split control lines is used to provide logical combinations responsive to an input signal. The transistor is a field-effect transistor (FET) having an electrically isolated (floating) gate that controls electrical conduction between source regions and drain regions. If a particular floating gate is charged with stored electrons, then the transistor will not turn on and will act as the absence of a transistor at this location in a logic array within the field programmable logic array. The field programmable logic array is programmed in the field to select a particular logic combination responsive to a received input signal. A logic array includes densely packed logic cells, each logic cell having a semiconductor pillar providing shared source and drain regions for two vertical floating gate transistors that have individual floating gates and control lines distributed on opposing sides of the pillar.
    Type: Grant
    Filed: February 27, 1998
    Date of Patent: September 26, 2000
    Assignee: Micron Technology, Inc.
    Inventors: Wendell P. Noble, Leonard Forbes
  • Patent number: 6111428
    Abstract: There is provided a programmable logic array in which a precharge circuit is provided separately from precharge transistors. The precharge circuit can connect the one of wirings connecting memory cell transistors out of the memory cell transistor group constituting an AND plane to a power supply voltage at a same timing as that of the precharge transistors. Accordingly, the programmable logic array having the AND plane which can prevent variation of an output by improving charge share tolerance can be provided.
    Type: Grant
    Filed: July 21, 1998
    Date of Patent: August 29, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Shingo Hanatani
  • Patent number: 6066959
    Abstract: A logic array includes an AND plane, a first OR plane, and a second OR plane. The AND plane is adapted to receive a plurality of logic array inputs and provide a plurality of minterms. Each minterm represents a logical combination of a subset of the plurality of logic array inputs. The first OR plane is adapted to receive the minterms and provide a plurality of intermediate outputs. Each intermediate output represents a logical combination of a subset of the minterms. The second OR plane is adapted to receive the intermediate outputs and provide a plurality of logic array outputs. Each logic array output represents a logical combination of a subset of the intermediate outputs. A method for programming a logic array includes providing a plurality of minterms. A plurality of subsets of the minterms are logically combined to define a plurality of intermediate outputs. A plurality of subsets of the intermediate outputs are logically combined to define a plurality of logic array outputs.
    Type: Grant
    Filed: December 9, 1997
    Date of Patent: May 23, 2000
    Assignee: Intel Corporation
    Inventors: Frederick R. Gruner, Ralph Portillo
  • Patent number: 5986466
    Abstract: A programmable gate array is disclosed for implementing asynchronous logic. In one embodiment, the array includes a set of cells, at least one of which includes a threshold gate having a plurality of inputs, an output, and a threshold value. Signals may assume an ASSERTED state having a logic meaning and a NULL state that has no logic meaning. The gate output switches to NULL when all inputs are NULL, and switches to the ASSERTED state when the number of ASSERTED inputs exceeds the threshold value. In the preferred embodiment, the gate exhibits hysteresis such that the output remains ASSERTED while the number of ASSERTED inputs remains greater than zero, and less than the threshold value. In an alternate embodiment, an array of simplified threshold elements is used to form more complex threshold gates.
    Type: Grant
    Filed: October 8, 1997
    Date of Patent: November 16, 1999
    Assignee: Theseus Logic, Inc.
    Inventors: Gerald Edward Sobelman, David Parker
  • Patent number: 5959465
    Abstract: A method is provided for operating a programmable logic array in an integrated circuit. Each stage of the circuit is enabled only during the time necessary for that stage to propagate an incoming signal. Enable signals are generated for the stages of the circuit, using a dummy circuit which replicates elements of the circuit in dimension, orientation and connectivity. These elements provide a delay path, such that an input signal applied coincidentally to the programmable logic array circuit and the dummy circuit produces outputs of the dummy circuit which define times for applying and removing the enable signals from stages of the programmable logic array circuit.
    Type: Grant
    Filed: December 29, 1995
    Date of Patent: September 28, 1999
    Assignee: STMicroelectronics Ltd.
    Inventor: Robert Beat
  • Patent number: 5926039
    Abstract: An active load (12) is provided for an N channel logic network (10). The active load (12) includes a P channel device (28) coupled to the output node (14) of the N channel network (10). A clock circuit (16) of the active load (12) determines whether the N channel network (10) is in a steady state or a switching mode. If the N channel network (10) is in a switching mode, an intermediate voltage level, V.sub.bias, is applied at the gate of the P channel device (28) to facilitate fast switching at the output node (14) with low quiescent power consumption and without compromising compact semiconductor layout.
    Type: Grant
    Filed: March 19, 1997
    Date of Patent: July 20, 1999
    Assignee: Texas Instruments Incorporated
    Inventors: Shivaling S. Mahant-Shetti, Kameshwar C. Rao
  • Patent number: 5872462
    Abstract: A PLA whose slowest product terms are located as close as possible to the true/complement generators or input buffers. The associated input buffers and product terms are partitioned into two or more sections. A modified gap cell recombines the product terms before propagating the signal into an array.
    Type: Grant
    Filed: November 26, 1997
    Date of Patent: February 16, 1999
    Assignee: International Business Machines Corporation
    Inventors: Gary Stephen Ditlow, Paul David Kartschoke
  • Patent number: 5867038
    Abstract: A ratio-logic system having an input sensing device and a resetable delay device is disclosed. The input sensing device receives an input having a first logic state and a second input having a second logic state. The input sensing device then asynchronously outputs a first state-change signal if the first logic state differs from the logic state of a previous input, and a second state-change signal if the second logic state differs from the first logic state. The resetable delay device receives the first and second state-change signals and asynchronously outputs a power-up signal to a ratio-logic device for a predetermined amount of time after the first state-change signal is received. The resetable delay device then powers-down the ratio-logic device after the predetermined amount of time is over. The predetermined amount of time is reset if the input sensing device receives the second state-change signal before the predetermined amount of time is over.
    Type: Grant
    Filed: December 20, 1996
    Date of Patent: February 2, 1999
    Assignee: International Business Machines Corporation
    Inventors: Paul David Kartschoke, Norman Jay Rohrer, Timothy Sulzbach
  • Patent number: 5852365
    Abstract: A variable logic circuit comprises a memory cell, a transistor which turns on or off depending on data stored in the memory cell, a transistor which is connected in series to the above-mentioned transistor and is turned on or off by an input signal, a transistor which produces a voltage depending on the conduction states of the above-mentioned transistors, and transfer means which conducts or does not conduct the produced voltage to the output terminal depending on a select signal.
    Type: Grant
    Filed: September 13, 1996
    Date of Patent: December 22, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Nobuo Tamba, Mitsugu Kusunoki, Takeshi Miyazaki, Akira Masaki, Akira Yamagiwa
  • Patent number: 5821770
    Abstract: A method for varying the type of function selected on a chip (for example, after completion of manufacturing) may include the steps of providing predetermined fuse arrangements which individually or in combination correspond to each type of function on the chip and providing disable control lines having fuses to each of the predetermined fuse arrangements. When one of the types of circuits is selected, the predetermined fuse arrangement individually or in combination corresponding to that selected type of function is blown. The blowing of fuses may change the functionality of the chip directly or may perform a complex procedure such as controlling a portion of a decoding scheme which may radically change the function of the chip. To prevent further blowing of predetermined fuse arrangements, the fuses in disable control lines to each of the predetermined fuse arrangements may be blown, eliminating further selection of types of function.
    Type: Grant
    Filed: April 30, 1996
    Date of Patent: October 13, 1998
    Assignee: Cypress Semiconductor Corporation
    Inventor: David Rees
  • Patent number: 5818261
    Abstract: A bus mechanism mitigates programmable device performance and power consumption issues by utilizing a small swing transmitter at the source end of an interconnect network and a high gain differential amplifier at the receiver end of the interconnect network. The signal is generated as a small swing voltage differential compared to a reference voltage and the reference voltage is set at a magnitude close to the negative power supply signal (near ground or GND). Because the performance of NMOS cross point switches with signals close to GND is very good, virtually no signal swing is lost in these NMOS cross point switches. The small swing signal voltages also significantly reduce the power dissipated when transmitting data. Transmitter pre-charge, differential amplifier equalization and a PMOS differential amplifier further enhance performance and reduce power consumption.
    Type: Grant
    Filed: August 8, 1996
    Date of Patent: October 6, 1998
    Assignee: Hewlett Packard Company
    Inventor: Frederick A. Perner
  • Patent number: 5751165
    Abstract: A very high speed customizable logic array device comprising:a substrate having at least one gate layer and at least first, second and third metal layers formed thereon, the gate layer including a multiplicity of identical unit logic cells,the customizable logic array device including at least three of the following functionalities:NAND, NOR, inverter, AND and ORand further being characterized in that the ratio between the rise time and the fall time of the logic cells embodying each of the at least three functionalities is constant.
    Type: Grant
    Filed: August 18, 1995
    Date of Patent: May 12, 1998
    Assignee: Chip Express (Israel) Ltd.
    Inventors: Uzi Yoeli, Eran Rotem, Meir Janai, Zvi Orbach
  • Patent number: 5719505
    Abstract: A reduced power programmable logic array is disclosed. The circuit includes an AND array, coupled through product term lines to an output OR array. Pull-up devices in the OR array are gated to one of the active product term lines. Also disclosed is method for choosing a product term line for gating pull-up devices such that power consumption in the pull-up devices is minimized.
    Type: Grant
    Filed: April 11, 1995
    Date of Patent: February 17, 1998
    Assignee: International Business Machines Corporation
    Inventors: Gary Stephen Ditlow, Paul David Kartschoke
  • Patent number: 5666071
    Abstract: An integrated circuit incorporating programmable pullup and pulldown devices into each input/output (I/O) pad is described. Each I/O pad may be individually programmed to include a pullup or pulldown function. Pullup and pulldown resistors may be removed from a system employing the present integrated circuit. Programming of the I/O pads may be accomplished in a number of ways. Following the deassertion of a reset signal, high impedance states may be transferred into a shift data storage within the integrated circuit. Once the states are received, they are shifted to the respective I/O pads through a serial chain connection of the pullup and pulldown devices within each I/O pad. The states are then maintained by each pullup and pulldown device until a subsequent reprogramming. Software programs may also reprogram the pullup and pulldown states by storing appropriate values into the shift data storage. The program then sets an appropriate value into a status register included within the integrated circuit.
    Type: Grant
    Filed: December 1, 1995
    Date of Patent: September 9, 1997
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Keith G. Hawkins, Harikumar B. Nair, Shivachandra I. Javalagi
  • Patent number: 5617041
    Abstract: In an EPLD, a feedback switching circuit is provided on a feedback line connected between a macrocell output line and a interconnect matrix wordline, the switching circuit including a memory element and a switch for passing a macrocell output signal from the output line to the interconnect matrix wordline when the memory element is in a first state, and for blocking the macrocell output signal when the memory element is in a second state. This prevents coupling noise in the interconnect matrix because unnecessary feedback signals are prevented from entering the interconnect matrix. In another embodiment, a method is provided in which unused macrocells produce counteractive switching signals in the interconnect matrix to reduce the coupling effect caused by a multiple concurrent switching event. In another embodiment, a sense amplifier is provided in which an EPROM shields coupling between wordlines and bitlines in an interconnect matrix.
    Type: Grant
    Filed: June 2, 1995
    Date of Patent: April 1, 1997
    Assignee: Xilinx, Inc.
    Inventors: Napoleon W. Lee, Wei-Yi Ku, Hy V. Nguyen, Sholeh Diba
  • Patent number: 5610535
    Abstract: A programmable two-line, two-phase logic array has a plurality of inputs, each having two input signals operating in two phases and memory cells provided at an intersection of the input signal lines and output lines corresponding to at least one function that cross the input lines. The memory cells are capable of being written in the fabrication process or by a field programming process that addresses the contact points at which the input and output lines cross. The two-line, two-phase logic circuit can be attained by the same technique as that used for attaining a conventional PLA without designing circuitry based on a conventional synchronous logic beforehand followed by replacing it with a two-line, two-phase circuit.
    Type: Grant
    Filed: September 27, 1995
    Date of Patent: March 11, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Akira Masaki, Makoto Kuwata, Ryuichi Satomura, Nobuo Tamba
  • Patent number: 5587945
    Abstract: A CMOS memory cell including PMOS and NMOS transistors with a common floating gate. The CMOS memory cell includes a first capacitor connecting a first control voltage to the common floating gate and a second tunneling capacitor connected from the common floating gate to the source of the NMOS transistor. The tunneling capacitor includes a tunneling oxide region utilized to charge or discharge the floating gate during program or erase. The CMOS cell further includes a pass transistor with a source to drain path connecting the source of the NMOS transistor to a second control voltage.
    Type: Grant
    Filed: November 6, 1995
    Date of Patent: December 24, 1996
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jonathan Lin, Jack Z. Peng, Radu Barsan, Sunil Mehta
  • Patent number: 5568067
    Abstract: A configurable XNOR/XOR logic element is used, in an exemplary embodiment, in an array of spare gates included in a processor or other integrated circuit. The XNOR/XOR logic element (FIG. 4, 60) is configurable as either an XNOR or an XOR gate by a C (configuration) input (that can be metal configurable as either asserted or deasserted). Inverted and noninverted C inputs control two coupling circuits: (a) coupling circuit C10 includes p-transistors C11, C12, C13, and C14, and (b) coupling circuit C20 includes n-transistors C21, C22, C23, and C24. Depending on whether the C input is deasserted or asserted (and the inverted C input is correspondingly asserted or deasserted), these configuration transistors series or cross couple parallel stacked p- and n-transistors that receive inverted and noninverted A and B inputs to effect the selected configuration. Specifically, deasserting C provides the XOR configuration, while asserting C provides the XNOR configuration.
    Type: Grant
    Filed: June 30, 1995
    Date of Patent: October 22, 1996
    Assignee: Cyrix Corporation
    Inventors: Mark W. McDermott, John E. Turner