Abstract: A CMOS memory cell including PMOS and NMOS transistors with a common floating gate. The CMOS memory cell includes a first capacitor connecting a first control voltage to the common floating gate and a second tunneling capacitor connected from the common floating gate to the source of the NMOS transistor. The tunneling capacitor includes a tunneling oxide region utilized to charge or discharge the floating gate during program or erase. The CMOS cell further includes a pass transistor with a source to drain path connecting the source of the NMOS transistor to a second control voltage.

Abstract: A configurable XNOR/XOR logic element is used, in an exemplary embodiment, in an array of spare gates included in a processor or other integrated circuit. The XNOR/XOR logic element (FIG. 4, 60) is configurable as either an XNOR or an XOR gate by a C (configuration) input (that can be metal configurable as either asserted or deasserted). Inverted and noninverted C inputs control two coupling circuits: (a) coupling circuit C10 includes p-transistors C11, C12, C13, and C14, and (b) coupling circuit C20 includes n-transistors C21, C22, C23, and C24. Depending on whether the C input is deasserted or asserted (and the inverted C input is correspondingly asserted or deasserted), these configuration transistors series or cross couple parallel stacked p- and n-transistors that receive inverted and noninverted A and B inputs to effect the selected configuration. Specifically, deasserting C provides the XOR configuration, while asserting C provides the XNOR configuration.

Abstract: A semiconductor integrated circuit adaptable to any logic circuits using a common mask with the exception of a mask of metallic wirings so as to drastically improve performance of custom LSIs. The semiconductor integrated circuit comprises a logic circuit having a plurality of input terminals and at least one output terminal. The logic circuit includes a plurality of circuit blocks of the same circuit construction. Each of the circuit blocks has at least two stages of inverter formed by MOS semiconductor devices and at least one layer of a wiring pattern having a different pattern. The output signal of each block is defined by a predetermined function of an input signal.

Abstract: A base cell for a CMOS gate array is provided with a plurality of N-channel transistors 10, 12, 14 with all such N-channel transistors coupled in series. A plurality of P-channel transistors 16, 18 coupled in series. These transistors are interconnected at the transistor level to form a partially prewired circuit. Specifically, the gates of two of the N-channel transistors 12, 14 are connected by polysilicon lead 28 to the gate of transistor 16. This configuration forms a circuit primitive which is well adapted for use as a base cell in a programmable array device.

Abstract: In an input level converter for TTL--CMOS level conversion (or other conversion to CMOS) for an internal logic block operating with CMOS levels, an output transistor for executing the charge or discharge of the output capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the input level converter can be lessened. Similarly, in an output level converter for CMOS--TTL level conversion (or other conversion from CMOS) for the internal logic block operating with the CMOS levels, an output transistor for executing the charge or discharge of the output load capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the output level converter can also be lessened.

Abstract: An FPGA having a plurality of logic modules with configurable output drivers (8) to enable outputs (y) of several logic modules to be wired together. The output driver (8) comprises a n-channel and a p-channel driver transistor (16, 20) which are connected to a signal (I/O) when no wired outputs (y) are desired. If two or more outputs (y) are to be connected to enable a wired logic function, p-channel transistor (16) is disabled. Then, a weak pull-up transistor (18) may be provided. Alternatively, a senseamp may be provided to the connected outputs (y).

Abstract: In a semiconductor integrated circuit device having a data latch function, one of two inverters constituting a data latch circuit is formed of a PMOS transistor and an NMOS transistor, with the source terminal of the NMOS transistor being connected to a terminal for applying a reset signal. The reset signal is applied to an inverter through the NMOS transistor, and the inverter inverts the reset signal and resets the data latch circuit. Since one inverter of the data latch circuit is formed of the PMOS transistor and the NMOS transistor, the setting/resetting function of the semiconductor integrated circuit device can readily be implemented.

Abstract: A non-volatile, in-system programmable integrated-circuit switch has horizontal conductive lines and vertical conductive lines. A programmable interconnect cell including a floating gate transistor is provided at each intersection of a horizontal line and a vertical line. Each line is connected to a pin through a programmable I/O cell which includes a floating gate transistor. Each I/O cell can be programmed to configure the corresponding pin as an input pin or as an inverting or non-inverting output pin. The I/O cell can also be programmed to tri-state the pin or to fix the pin at a high or low voltage level. Each input pin can be connected to more than one output pins. A TTL-to-CMOS translator in each I/O cell is provided in the output section of the cell to reduce the translator output load and make the load, and hence the speed and power consumption of the switch, less dependent on the switch programming.

Abstract: A logic circuit arrangement for performing synchronous dual word decoding utilizing a programmable logic array which is formed with a reduced number of transistor counts. This is achieved by organizing the AND plane (64) so as to decode only the seven (7) most significant bits of an 8-bit opcode word. A LSB decoder circuit (153) is used for decoding the least significant bit of the opcode word separately and outside of the AND plane. As a result, the amount I.C. chip space required has been substantially reduced.

Abstract: A programmable logic device is presented comprising a global interconnect array whose lines are fed via programmable multiplexers to two stacks of logic array blocks on its sides. The logic array blocks include CMOS look up table based logic modules that consume zero DC power. The global interconnect array lines are fed to the multiplexers in a specific pattern which maximizes routing flexibility and speed. The combination of low power logic array blocks and high performance global interconnect array allows for increased logic density at lower power consumption compared to prior art programmable logic array devices.

Abstract: A circuit style, which may be employed in fast, area-efficient, flexible programmable interconnect architectures, is disclosed. In one embodiment, a plurality of clocked dynamic logic circuits, each having a single network node, is connected to the intermediate nodes of a programmable interconnect architecture. During the precharge clock phase, the circuits precharge the intermediate nodes to a high logic level. During the evaluation clock phase, each circuit is initially in the stand-by state, in which it monitors the logic level on its network node. If a substantial deviation from the high level towards the low level is detected, the circuit switches to the discharge state, in which it enforces that level change by connecting its network node to the low level. This causes the potential on neighboring nodes, connected through conducting programmable switches, to change towards a low level, and their circuits in turn switch to the discharge state.

Abstract: A gate array base cell (100) performs logic and memory cell functions and comprises a first P-channel transistor (M1) for performing logic functions and having a first predetermined transconductance area and a second P-channel transistor (M5) for performing memory cell functions and having a second predetermined transconductance area. The second transconductance area is smaller than said first predetermined transconductance area. The gate array base cell (100) has programmable connections to first P-channel transistor (M1) and second P-channel transistor (M5) for selectively performing memory cell functions and logic functions. The gate array base cell (100) may be connected to operate as a memory cell with logic functions or separately as a memory cell or a logic gate array, such as a two-input NAND gate (128).

Abstract: A user-programmable inter-chip interconnect architecture, which may be used for providing programmable interconnections among a plurality of integrated circuits, is disclosed. A plurality of main circuitry in the core region of an integrated circuit is connected through connection nodes to a programmable peripheral switch network in the frame region of the integrated circuit. The peripheral switch network may be programmed by the user to obtain the desired signal-propagating paths between said connection nodes and bonding pads of the peripheral switch network, or among bonding pads of the peripheral switch network. The peripheral switch network has intersecting wiring channels attached to the bonding pads and the connection nodes. Programmable junctions may be present at the intersections of the wiring channels. A substantial number of desired interconnections may be achieved that have only one such programmable junction in the signal-propagating path.

Abstract: A digital logic circuit for use in or as a macrocell which can be programmed to operate as a flip-flop or as a latch, or to be transparent to a signal, and which also has programmable output polarity. This programmable macrocell circuit has two master latch elements and one slave latch element. The master latch elements are respectively inverting and noninverting latches which are located on two parallel alternate paths. A set of pass transistors on the input end of the two paths causes an input signal to drive only a selected one of the two paths and its associated master latch element. A two-by-one multiplexer connects the output of the selected master latch element in one of the two signal paths to the input of the slave latch.

Abstract: A base cell for a CMOS gate array is provided with a first plurality of N-channel transistors 12, 14, 16 with two such N-channel transistors coupled in series. A first plurality of P-channel transistors 50, 52, 54 with two such P-channel transistors coupled in series. These transistors are interconnected at the transistor level to form a partially prewired circuit. Additional pairs of series connected N-channel transistors (18, 20), (22, 24) and pairs of series connected P-channel transistors (56, 58), (60, 62) are also provided and are interconnected at the transistor level to form additional partially prewired circuits. By adding additional levels of wiring 100, 102, the base cell can be finally wired to form a plurality of different logic circuits.

Abstract: An input buffer for utilization in a programmable logic device (PLD). The input buffer includes an inverter consisting of a PMOS pull up transistor one half the size of a corresponding NMOS pull down transistor to enable TTL compatibility. To drive a high capacitance load, instead of utilizing further buffering which introduces gate delays, a cascode transistor is used to control an additional pull up output driver connected to the output of the inverter. The cascode functions to turn on the additional pull up output driver to supplement the PMOS pull up transistor during a low to high transition of the output. The input buffer further includes a switching transistor coupled between a V.sub.DD power supply and the PMOS pull up transistor to cut power to the PMOS pull up transistor when the inverter has a low output. With no utilization of power during a low output, the input buffer provides a zero power TTL input enabling the input buffer to be utilized on circuitry in battery powered devices.

Abstract: A low power optional inverter uses P-channel and N-channel transistors in series as in a conventional CMOS inverter, but in one embodiment connects complementary signals to the sources of the P-channel and N-channel transistors such that when the complementary signals are switched the circuit switches between an inverting and a non-inverting buffer. In some embodiments P-channel and/or N-channel pass transistors are used in the non-inverting mode to avoid the threshold voltage drop associated with a CMOS non-inverting buffer. In another embodiment, in the noninverting mode, at least one bypass transistor is turned on and power is not supplied to the inverter. In yet another embodiment, in the inverting mode a CMOS inverter is powered with conventional voltages and in the noninverting mode the CMOS inverter is disabled and a bypass transistor connects input to output.

Abstract: In a semiconductor integrated circuit device having a data latch function, one of two inverters constituting a data latch circuit is formed of a PMOS transistor and an NMOS transistor, with the source terminal of the NMOS transistor being connected to a terminal for applying a reset signal. The reset signal is applied to an inverter through the NMOS transistor, and the inverter inverts the reset signal and resets the data latch circuit. Since one inverter of the data latch circuit is formed of the PMOS transistor and the NMOS transistor, the setting/resetting function of the semiconductor integrated circuit device can readily be implemented.

Abstract: A FPGA matching the organization and performance of mask programmable gate arrays is presented. The core array is organized into rows of continuous series transistors (CSTs) and rows of small latch/logic blocks. The source/drains and gate of each of the transistors are connected to line segments. The input and output terminals of the blocks are also connected to line segments. Programmable antifuses are located at the intersections of the line segments, which also include others for power and routing purposes. The FPGA can be efficiently configured into a user's application with the flexibility of the CSTs and the efficiency of the latch/logic blocks, which may also be configured into RAM arrays.

Abstract: A semiconductor integrated circuit device such as a memory device with logic function comprises a plurality of RAM macrocells and gate arrays. The RAM macrocells are constituted by bipolar CMOS RAMs having a total memory capacity of at least 100 kilobits, and the gate arrays contain at least 4000 gates. The logic circuits in the memory device with logic function or the like are constructed by selectively combining CMOS, bipolar CMOS or ECL gate circuits depending on the output load capacity, transmission characteristic requirement, power dissipation and required layout area. The level of signals at various circuits is set to the ECL level or MOS level depending on the local circuit configuration and other factors. The memory device further incorporates sequence control circuits required to be installed downstream of buffer storages of computers.

Abstract: A field programmable gate array (FPGA) including both routing and logic blocks (RLBs) and routing and arbiter blocks (RABs) is disclosed. The RABs are periodically placed throughout the FPGA and operate either to arbitrate the arrival of simultaneous signals or to synchronize simultaneous signals. In addition, each of the RLBs are capable of operating in accordance with two clock signals and an asynchronous initialization. The combination of the RLBs and RABs allow the FPGA to operate synchronously and asynchronously.

Abstract: A test configuration register (80) associated with a programmable memory device (88), wherein the signals at the outputs of the test configuration register force elements of the memory device into certain logic states to enable the device to be tested without programming the device's logic array (22).