Abstract: The disclosed technology includes, among other innovations, a framework for resource efficient compilation of higher-level programs into lower-level reversible circuits. In particular embodiments, the disclosed technology reduces the memory footprint of a reversible network implemented in a quantum computer and generated from a higher-level program. Such a reduced-memory footprint is desirable in that it addresses the limited availability of qubits available in many target quantum computer architectures.

Abstract: A chip package comprises an interposer; an FPGA IC chip over the interposer, wherein the FPGA IC chip comprises a programmable logic block configured to perform a logic operation on its inputs, wherein the programmable logic block comprises a look-up table configured to be provided with multiple resulting values of the logic operation on multiple combinations of the inputs of the programmable logic block respectively, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values into its output, and multiple non-volatile memory cells configured to save the resulting values respectively; multiple first metal bumps between the interposer and the FPGA IC chip; and an underfill between the interposer and the FPGA IC chip, wherein the underfill encloses the first metal bumps.

Abstract: Some embodiments include apparatus and methods using an input stage and an output stage of a circuit. The input stage operates to receive an input signal and a clock signal and to provide an internal signal at an internal node based at least in part on the input signal. The input signal has levels in a first voltage range. The internal signal has levels in a second voltage range greater than the first voltage range. The output stage operates to receive the internal signal, the clock signal, and an additional signal generated based on the input signal. The output stage provides an output signal based at least in part on the input signal and the additional signal. The output signal has a third voltage range greater than the first voltage range.

Abstract: An integrated circuit comprising a plurality of one-hot-bit multiplexers interconnected to form a switch interconnect network (e.g., hierarchical and/or mesh type networks), wherein each of the plurality of one-hot-bit multiplexers includes an output, inputs, and input selects, wherein each one-hot-bit multiplexer of the plurality of one-hot-bit multiplexers are capable of receiving: (i) an input select signal to select one of the plurality of inputs, (ii) an operational input signal at a selected input during a normal operation of the switch interconnect network, and (iii) an initialization input signal at the selected input during an initialization operation.

Abstract: Methods for serializing data output including receiving a plurality of data values, sequentially providing data values representative of data values of a first subset of data values of the plurality of data values to a first signal line while sequentially providing data values representative of data values of a second subset of data values of the plurality of data values to a second signal line, and providing data values representative of the sequentially-provided data values from the first signal line and providing data values representative of the sequentially-provided data values from the second signal line in an alternating manner to a third signal line, as well as apparatus having a configuration to support such methods.

Abstract: An apparatus and method are described to determine line functionality between two electrical circuits to enable the line to run at a maximum frequency without deleterious conditions occurring from cross-talk effects.

Abstract: Work can be migrated between processor cores. For example, a thread causing a heavy load on a first core can be detected. A power control unit can determine to migrate the thread from the first less-efficient core to the second more-efficient core. The power control unit can request that the first core and the second core transition to a low-power state (e.g., a sleep state, a C6 power state, etc.). The first core can transfer its software context to a first core software context storage, halt and quiesce. The second core can halt and quiesce. The software context from the first core software context storage can be transferred to a second core software context storage of the second core. A processing core identifier of the first core can be assigned to the second core. The power control unit can then request the second core to transition to an active state (such as a C0 state).

Abstract: A multi-modality medical system having a computing system communicatively coupled to a medical instrument is provided. An acquisition control activity module is configured to control acquisition of medical data from a patient with the medical instrument and a business logic state machine having a first data acquisition state and a first data review state and being operable to utilize the acquisition control activity module to control acquisition of medical data from the patient with the medical instrument while in the first data acquisition state, and being configured to convert the medical data into images representative of portions of the patient while in the first data acquisition state. The computing system includes also includes a user interface state machine having a second data acquisition state and a second data review state and being configured to present the images within a user interface while in the second data review state.

Abstract: Described is an apparatus which comprises: a state detector which is operable to detect logic states of zero and one in response to a clock edge; and an error detector coupled to the state detector, wherein the error detector is to detect an error in the detected logic states.

Abstract: According to one embodiment, a semiconductor integrated circuit comprises: a tested block including a test control circuit; and a control circuit configured to output a first signal. The test control circuit performs a test of at least a first test pattern of the test patterns for the scan chain in accordance with the first signal during a first non-access state period of the tested block, and performs a test of at least a second test pattern following the first test pattern of the test patterns for the scan chain in accordance with the first signal during a second non-access state period of the tested block, and the test of the first test pattern and the test of the second test pattern are performed discontinuously.

Abstract: Digital systems formed on integrated circuits may include sequential logic circuitry. The sequential logic circuitry may form at least part of a finite state machine that records different logical states. The sequential logic circuitry may include a first latching circuit and a second latching circuit that each latch bits onto their respective outputs when clocked at different levels. The first latching circuit may output a first bit. Combinational logic circuitry may be distributed on both sides of the first latching circuit such that a combinational logic circuit interposed between the first and second latching circuits generates a second bit based on at least the first bit. The first and second bits may record one of two possible finite logical states of the sequential logic circuitry. By distributing combinational logic circuitry on two sides of a given latching circuit, dynamic power consumption by the sequential logic circuitry may be optimized.

Abstract: An object is to provide a semiconductor device which can suppress characteristic deterioration in each transistor without destabilizing operation. In a non-selection period, a transistor is turned on at regular intervals, so that a power supply potential is supplied to an output terminal of a shift register circuit. A power supply potential is supplied to the output terminal of the shift register circuit through the transistor. Since the transistor is not always on in a non-selection period, a shift of the threshold voltage of the transistor is suppressed. In addition, a power supply potential is supplied to the output terminal of the shift register circuit through the transistor at regular intervals. Therefore, the shift register circuit can suppress noise which is generated in the output terminal.

Abstract: An integrated circuit includes a security module with multiple stages arranged in a pipeline, with each stage executing a different operation for accessing stored lifecycle (LC) information. For each portion of LC being accessed, each stage performs N iterations of its corresponding operation, whereby N is an integer greater than two, and crosschecks the results of successive iterations to ensure that the results of the operation are consistent. In addition, the stages of the security module are overlapping, such that different stages can perform different iterations concurrently. These concurrent operations at different stages are organized such that they may also be crosschecked and thereby confirm “offset” results between the stages.

Abstract: A system can include a finite state machine generator implemented in programmable circuitry of an integrated circuit. The finite state machine generator is parameterizable to implement different finite state machines at runtime of the integrated circuit. The system can include a processor configured to execute program code. The processor is configured to provide first parameterization data to the finite state machine generator at runtime of the integrated circuit. The first parameterization data specifies a first finite state machine and the finite state machine generator implements the first finite state machine in response to receiving the first parameterization data from the processor.

Abstract: In order to generate a false failure in a logic circuit without adding a new circuit to the logic circuit, a semiconductor device includes a plurality of test points includes a test point flip-flop to fix a target node within the logic circuit to a predetermined logic level when the flip-flop holds a predetermined value. A scan chain is configured by sequentially coupling a plurality of test point slip-flops. A failure injection circuit injects a failure into the target node during the normal operation of the logic circuit, by generating failure data and by setting the generated failure data to the scan chain through a scan-in node of the scan chain.

Abstract: A triangular wave generator includes a wave generator configured to generate a triangular wave according to a clock signal and a control signal. The triangular wave generator further includes a wave controller configured to adjust a value of the control signal in a correction mode. The control signal includes a first bias control signal, a second bias control signal, and a capacitance control signal.

Abstract: System and method for validating a program under a specified model of computation. The model of computation may be related to the synchronous statechart model of computation. A program may be received that specifies a plurality of operations using a variable within a logical tick such that the variable has multiple values within the logical tick. The program may be statically analyzed according to a specified model of computation that specifies program execution based on logical ticks, which may include determining that the program has deterministic semantics that specify deterministic results for each logical tick during execution of the program, including specifying deterministic results of the plurality of operations performed within the logical tick. The program may be validated in accordance with the specified model of computation in response to the determining.

Abstract: Embodiments of the present disclosure provide a clock signal transmission circuit, a driving method thereof, a gate driving circuit, and a display device. The clock signal transmission circuit includes an input circuit, a pull-up circuit, a reset circuit, a pull-down control circuit, a pull-down circuit, and a pull-up holding circuit. According to an embodiment of the present disclosure, the clock signal source can be disconnected from each shift register unit in the gate driving circuit before a screen is displayed, preventing malfunctions of the gate driving circuit caused by an undesired high voltage on the clock signal line.

Abstract: A model of a state machine may be created in a modeling environment, and the model may be executed over a simulation time. A duration operator may be defined within the model. The duration operator may include as an input argument, a conditional expression that may evaluate to True or False. During execution, the modeling environment may define a plurality of time steps over the course of the model's simulation time. The conditional expression of the duration operator may be evaluated at the time steps. When the conditional expression evaluates to True, the modeling environment may begin tracking elapsed simulation time, and may continue to track elapsed simulation time while the conditional expression remains True. The value of elapsed simulation time may be made available to other portions of the model.

Abstract: Various implementations described herein are directed to a sequential logic device having multiple stages. The sequential logic device may include a first stage having first transistors that are arranged to receive a data input signal and a clock signal and provide a first signal and a second signal based on the data input signal and the clock signal. The sequential logic device may include a second stage having second transistors that are arranged to receive the first signal from the first stage and provide an inverted first signal to a gate of a first pass transistor. The first pass transistor may allow the second signal to pass from the first stage to a second pass transistor based on the inverted first signal, and the second pass transistor may allow the second signal to pass from the first pass transistor to ground based on the clock signal.

Abstract: To provide a memory device with short overhead time and a semiconductor device including the memory device. A memory device includes a first circuit that can retain data and a second circuit by the supply of power supply voltage. The second circuit includes a third circuit that selects a first potential corresponding to the data or a second potential supplied to a first wiring; a first transistor having a channel formation region in an oxide semiconductor film; a capacitor that hold the first potential or the second potential that is selected by the third circuit and supplied through the first transistor; and a second transistor controlling a conduction state between the first circuit and a second wiring that can supply a third potential in accordance with the potential retained in the capacitor.

Abstract: Examples disclosed herein relate to set-reset (SR) latch circuits and methods for manufacturing the same. In some of the disclosed examples, a SR latch circuit includes an inverter storage loop for storing state information and a set of p-channel field-effect transistors (PFETs) for control circuitry. The PFETs may include first and second PFETs connected to a first node of the inverter storage loop, and third and fourth PFETs connected to a second node of the inverter storage loop. Gate terminals of the first and fourth PFETs may be connected to a first control input, and gate terminals of the second and third PFETs may be connected to a second control input.

Abstract: A shift register unit and a control method thereof, a gate drive device including the shift register unit, and a display device. The shift register unit includes: an input module, a pull-up module, a first pull-down control signal generation module, controlling, in the period that a first signal is high level, potential of a first pull-down control node according to a drive input signal and potential of a pull-up control node; a second pull-down control signal generation module, controlling, in the period that a second signal is high level, potential of a second pull-down control node according to the drive input signal and the potential of the pull-up control node, the first signal and the second signal alternatively becoming high level; and a pull-down module, pulling down a drive output signal according to the potential of the first pull-down control node and the potential of the second pull-down control node.

Abstract: A shift register includes a pulling-up unit, a pulling-down unit and an output unit, the pulling-up unit being connected to a first input terminal, a first clock signal terminal, a first level terminal, a pulling-down node and a pulling-up node, respectively, the pulling-down unit being connected to a second input terminal, a second level terminal, the first level terminal, the pulling-up node and the pulling-down node, respectively, and the output unit being connected to the first level terminal, a second clock signal terminal, an output terminal, the pulling-down node and the pulling-up node, respectively. The shift register provides an output signal through the output terminal according to the signals inputted from the first input terminal, the second input terminal, the first level terminal, the second level terminal, the first clock signal terminal and the second clock signal terminal.

Abstract: Various implementations described herein are directed to a circuit. The circuit may include a memory circuit having a first latch. The circuit may include a power-on-reset circuit having a second latch coupled to the first latch. The second latch may be configured to reset the first latch to a predetermined state at power-up.

Abstract: To provide a semiconductor device which operates stably with few malfunctions due to noise, with low power consumption, and little variation in characteristics; a display device including the semiconductor device; and an electronic device including the display device. An output terminal is connected to a power supply line, thereby reducing variation in electric potential of the output terminal. In addition, a gate electrode potential which turns ON a transistor is maintained due to the capacitance of the transistor. Further, change in characteristics of the transistor is reduced by a signal line for reverse bias.

Abstract: Embodiments of the invention relate to a neuromorphic network for producing spike-timing dependent plasticity. The neuromorphic network includes a plurality of electronic neurons and an interconnect circuit coupled for interconnecting the plurality of electronic neurons. The interconnect circuit includes plural synaptic devices for interconnecting the electronic neurons via axon paths, dendrite paths and membrane paths. Each synaptic device includes a variable state resistor and a transistor device with a gate terminal, a source terminal and a drain terminal, wherein the drain terminal is connected in series with a first terminal of the variable state resistor.

Abstract: Embodiments of the invention relate to a neuromorphic network for producing spike-timing dependent plasticity. The neuromorphic network includes a plurality of electronic neurons and an interconnect circuit coupled for interconnecting the plurality of electronic neurons. The interconnect circuit includes plural synaptic devices for interconnecting the electronic neurons via axon paths, dendrite paths and membrane paths. Each synaptic device includes a variable state resistor and a transistor device with a gate terminal, a source terminal and a drain terminal, wherein the drain terminal is connected in series with a first terminal of the variable state resistor.

Abstract: A memory device does not need a complex manufacturing process and whose power consumption can be suppressed, and a semiconductor device including the memory device. A solution is to provide a capacitor which holds data and a switching element which controls storing and releasing charge in the capacitor in a memory element. In the memory element, a phase-inversion element such as an inverter or a clocked inverter includes the phase of an input signal is inverted and the signal is output. For the switching element, a transistor including an oxide semiconductor in a channel formation region is used. In the case where application of a power supply voltage to the phase-inversion element is stopped, the data is stored in the capacitor, so that the data is held in the capacitor even when the application of the power supply voltage to the phase-inversion element is stopped.

Abstract: A device including a data analysis element including a plurality of memory cells. The memory cells analyze at least a portion of a data stream and output a result of the analysis. The device also includes a detection cell. The detection cell includes an AND gate. The AND gate receives result of the analysis as a first input. The detection cell also includes a D flip-flop including an output coupled to a second input of the AND gate.

Abstract: A method is provided for transmitting, by a base station, signals in a communication system. Carrier aggregation configuration information is transmitted to a mobile station via a primary carrier band of the mobile station. The carrier aggregation configuration information informs the mobile station of a subsidiary carrier band for the mobile station. Uplink control information for the subsidiary carrier band is received from the mobile station via the primary carrier band. The carrier aggregation configuration information includes a physical identification of a frequency allocation band used as the subsidiary carrier band and a logical identification assigned to the subsidiary carrier band for the mobile station. The physical identification includes one of plural absolute frequency band indexes assigned to frequency allocation bands available in the communication system. The logical identification includes a logical index assigned to the subsidiary carrier band identifying the subsidiary carrier band.

Abstract: A method and a circuit dynamically adjust a frequency of a clock signal that drives the operations of a power converter. The method includes (a) detecting a change from a predetermined value in an output voltage of the power converter; and (b) upon detecting the change, changing the frequency of the clock signal so as to restore the output voltage. The change, such as a load step-up, may be detected by comparing a feedback signal generated from the output voltage and a predetermined threshold voltage. In one implementation, changing the switching frequency is achieved in increasing (e.g., doubling) the frequency of the clock signal, as needed. The frequency of the clock signal need only be changed for a predetermined time period.

Abstract: A multi-memory cell operator includes a non-destructive memory array, an activation unit and a multiple column decoder. The non-destructive memory array has first and second bit lines per column. The activation unit activates at least two cells in a column of the memory array at the same time thereby to generate multiple Boolean function outputs of the data and of complementary data of the at least two cells on the first bit line and different multiple Boolean function outputs of the data and of the complementary data on the second bit line. The multiple column decoder at least activates the first and second bit lines of multiple selected columns for reading or writing. The multiple column decoder also includes a write unit to write the output of the first bit line, the second bit line or both bit lines of the selected columns into the memory array.

Abstract: A 3D multi-bit flip-flop may include a two tier structure. The two tier structure may include a first tier containing a common clock circuit for the multi-bit flip-flop as well as the clock driven portions of the individual flip-flops and a second tier containing a common scan circuit for the multi-bit flip-flop as well as the non-clock driven portions of the individual flip-flops. Alternatively, the first tier may include the common clock circuit as well as a portion of the individual flip-flops and the second tier may include the common scan circuit as well as the other portion of the individual flip-flops.

Abstract: An interconnect multiplexer comprises a plurality of CMOS pass gates of a first multiplexer stage coupled to receive data to be output by the interconnect multiplexer; an output inverter coupled to the outputs of the plurality of CMOS pass gates, wherein an output of the output inverter is an output of the interconnect multiplexer; and a plurality of memory elements coupled to the plurality of CMOS pass gates; wherein inputs to the plurality of CMOS pass gates are pulled to a common potential during a startup mode. A method of reducing contention currents in an integrated circuit is also disclosed.

Abstract: The semiconductor device includes a transistor, first to N-th switches (N is a natural number of three or more), and first to (N?1)-th capacitors. A first terminal of the first capacitor (or a J-th capacitor) is electrically connected to a gate of the transistor (or a second terminal of a (J?1)-th capacitor (J is a natural number of two or more and (N?1) or less)). A first (or K-th) potential is supplied to the gate of the transistor through the first switch (or a second terminal of a (K?1)-th capacitor through a K-th switch (K is a natural number of two or more and N or less)). A capacitance value of the first capacitor is preferably equal to a gate capacitance value of the transistor, and a capacitance value of the J-th capacitor is preferably equal to a capacitance value of the (J?1)-th capacitor.

Abstract: A method detects active power dissipation in an integrated circuit. The method includes receiving a hardware design for the integrated circuit having one or more clock domains, wherein the hardware design comprises a local clock buffer for a clock domain, wherein the local clock buffer is configured to receive a clock signal and an actuation signal. The method includes adding instrumentation logic to the design for the clock domain, wherein the instrumentation logic is configured to compare a first value of the actuation signal determined at a beginning point of a test period to a second value of the actuation signal determined at a time when the clock domain is in an idle condition. The method includes detecting the clock domain includes unintended active power dissipation, in response to the first value of the actuation signal not being equal to the second value of the actuation signal.

Abstract: A system and method for implementing a real-time state machine with a microcontroller is disclosed. The method includes using a two-stage process, including a configuration stage and a run-time stage, for processing objects for a printing device. The configuration stage is executed prior to the run-time stage, which operates in real-time. During the configuration stage, the system predetermines a state transition list, devices that need to be monitored, devices that need to be controlled, and other variables used during the run-time stage. Once the configuration stage is complete, the system executes the run-time stage in real-time to complete processing of an object for a printing device. By pre-calculating items during the configuration stage, the system reduces the execution time of the run-time stage in real-time. As a result, the performance of the microcontroller in real-time is enhanced.

Abstract: Predictive time-to-digital converters (TDCs) and methods for providing a digital representation of a time interval are disclosed herein. In an example, a TDC can include a delay line, a selection circuit, and a latch circuit. The delay line can include a plurality of delay elements configured to propagate a first edge of a first signal sequentially through the plurality of delay elements. The selection circuit can be configured to receive the first signal, to receive prediction information, and to route the first signal to an input of one of the plurality of delay elements based on the prediction information. The latch circuit can receive a second signal and can latch a plurality of outputs of the delay line upon reception of a second edge of the second signal. An output of the latch circuit can provide an indication of a delay between the first edge and the second edge.

Abstract: Two gate drivers each comprising a shift register and a demultiplexer including single conductivity type transistors are provided on left and right sides of a pixel portion. Gate lines are alternately connected to the left-side and right-side gate drivers in every M rows. The shift register includes k first unit circuits connected in cascade. The demultiplexer includes k second unit circuits to each of which a signal is input from the first unit circuit and to each of which M gate lines are connected. The second unit circuit selects one or more wirings which output an input signal from the first unit circuit among M gate lines, and outputs the signal from the first unit circuit to the selected wiring(s). Since gate signals can be output from an output of a one-stage shift register to the M gate lines, the width of the shift register can be narrowed.

Abstract: Provided is a semiconductor circuit which includes a first circuit configured to determine a voltage level of a feedback node based on a voltage level of input data, a voltage level of a latch input node, and a voltage level of a clock signal, a second circuit configured to pre-charge the latch input node based on the voltage level of the clock signal, a third circuit configured to pull down the latch input node based on the voltage level of the feedback node and the voltage level of the clock signal, a latch configured to output output data based on the voltage level of the clock signal and the voltage level of the latch input node, and a control circuit included in at least one of the first to third circuits and the latch and configured to receive the control signal.

Abstract: A method for transmitting, by a base station, signals in a communication system. The base station transmits, to a mobile station via a primary carrier band of the mobile station, carrier aggregation configuration information informing the mobile station of a subsidiary carrier band for the mobile station. The base station receives, from the mobile station, control information for the subsidiary carrier band via the primary carrier band. The carrier aggregation configuration information includes a physical identification of a frequency allocation band used as the subsidiary carrier band and a logical identification assigned to the subsidiary carrier band for the mobile station. The physical identification includes one of plural absolute frequency band indexes assigned to frequency allocation bands available in the communication system.

Abstract: A clock gating circuit includes a first transistor, a first inverter and a second transistor. A first terminal of the first transistor receives a clock input signal. A second terminal of the first transistor is coupled to a first node. The first transistor adjusts a voltage of the first node to a first voltage based on the clock input signal. The first inverter is coupled to the first node and receives the voltage of the first node, and outputs a clock output signal. A first terminal of the second transistor receives the clock input signal. A second terminal of the second transistor is coupled to the first node and a second node. The second transistor adjusts the voltage of the first node or the second node to the second voltage, based on the clock input signal.

Abstract: A method, computer program product, and computing system for defining a transactional log file for a data storage system including a data array. A first plurality of IO requests for the data storage system is processed. The transactional log file is updated to include information concerning the first plurality of IO requests. An IO pointer is defined to locate a specific IO request of the first plurality of IO requests within the transactional log file. File system metadata is defined on the data array for the data storage system.

Abstract: A duty cycle adjustment apparatus includes a duty cycle adjustment determination module configured to determine an adjustment to a duty cycle of a clock signal, and includes a clock delay module configured to receive the clock signal, to delay the clock signal through first and second delay stage modules (with a first and a second plurality of delay paths, respectively) based on the duty cycle adjustment determined by the duty cycle adjustment determination module, and to output the delayed clock signal. The second plurality of delay paths have a greater delay difference between each of the corresponding delay paths than the first plurality of delay paths. The apparatus further includes a duty cycle adjustment module configured to receive the clock signal and the delayed clock signal, to adjust the duty cycle of the clock signal based on the delayed clock signal, and to output a duty cycle adjusted clock signal.

Abstract: A network mapper for performing tasks on targets is provided. The mapper generates a map of a network that specifies the overall configuration of the network. The mapper inputs a procedure that defines how the network is to be mapped. The procedure specifies what, when, and in what order the tasks are to be performed. Each task specifies processing that is to be performed for a target to produce results. The procedure may also specify input parameters for a task. The mapper inputs initial targets that specify a range of network addresses to be mapped. The mapper maps the network by, for each target, executing the procedure to perform the tasks on the target. The results of the tasks represent the mapping of the network defined by the initial targets.

Abstract: A shift register unit, a gate driving circuit, an array substrate and a display apparatus are disclosed to reduce noises generated at an output of a next stage shift register unit caused by an output of a pervious stage shift register unit. The shift register unit at each stage comprises at least a signal inputting terminal INPUT, a signal outputting terminal OUTPUT and a capacitor CAP connected with the outputting terminal OUTPUT so as to provide an output signal to the outputting terminal OUTPUT, wherein the shift register unit further comprises a switch located between the capacitor CAP and the outputting terminal OUTPUT, and the switch is in a turned-off state when the capacitor CAP is charged.

Abstract: Embodiments of the invention relate to providing transposable access to a synapse array using a recursive array layout. One embodiment comprises maintaining synaptic weights for multiple synapses connecting multiple axons and multiple neurons, wherein the synaptic weights are maintained based on a recursive array layout. The recursive array layout facilitates transposable access to the synaptic weights. A neuronal spike event between an axon and a neuron is communicated via a corresponding connecting synapse by accessing the synaptic weight of the corresponding connecting synapse in the recursive array layout.

Abstract: To provide a semiconductor device which operates stably with few malfunctions due to noise, with low power consumption, and little variation in characteristics; a display device including the semiconductor device; and an electronic device including the display device. An output terminal is connected to a power supply line, thereby reducing variation in electric potential of the output terminal. In addition, a gate electrode potential which turns ON a transistor is maintained due to the capacitance of the transistor. Further, change in characteristics of the transistor is reduced by a signal line for reverse bias.

Abstract: A highly reliable semiconductor device in which a shift in the threshold voltage of a transistor due to deterioration is prevented is provided. The semiconductor device is formed using a sequential circuit including: a first transistor controlling the electrical connection between a first wiring and a second wiring; a second transistor and a third transistor in each of which a source and a drain are electrically connected to each other and which control the electrical connection between the second wiring and a third wiring; and a switch group controlling the electrical connection between a gate of the first transistor and the third wiring or a fourth wiring, the electrical connection between a gate of the second transistor and the third wiring or the fourth wiring, and the electrical connection between a gate of the third transistor and the third wiring or the fourth wiring in response to a control signal.