Abstract: The exemplary embodiments provide a reconfigurable integrated circuit architecture comprising: a configurable circuit element configurable for a plurality of data operations, each data operation corresponding to a context of a plurality of contexts; a plurality of input queues; a plurality of output queues; one or more configuration and control registers to store, for each context of the plurality of contexts, a plurality of configuration bits, a run status bit, and a plurality of bits designating at least one data input queue and at least one data output queue; and an element controller coupled to the configurable circuit element and to the one or more configuration and control registers, the element controller to allow loading of a context configuration and execution of a data operation upon the arrival of input data in the context-designated data input queue when the context run status is enabled and the context-designated data output queue has a status to accept output data.

Abstract: A signal processing unit with reduced power consumption is provided. A transistor in which a channel is formed in an oxide semiconductor is used for a storage circuit included in the signal processing unit, so that data can be held (stored) even while supply of power is stopped. Non-destructive reading can be performed on the data stored in the storage circuit even when supply of power to the signal processing unit is stopped.

Abstract: A scan flip-flop circuit includes an input unit and an output unit. The input unit selects one of a data input signal and a scan input signal depending on an operation mode and generates an intermediate signal based on the selected signal. The output unit generates an output signal based on the intermediate signal and selects one of a data output terminal and a scan output terminal depending on the operation mode to provide the output signal through the selected output terminal. A voltage level at the selected output terminal bidirectionally transitions between a first voltage level and a second voltage level. A voltage level at a non-selected output terminal unidirectionally transitions between the first voltage level and the second voltage level.

Abstract: A sequential voltage output circuit is connected between a power supply and a number of loads. The voltage sequence output circuit includes a complex programmable logic device (CPLD) and a number of switching circuits. When the CPLD receives a power on signal, the CPLD outputs a number of control signals sequentially through a number of outputs. When a switching circuit receives a control signal from the CPLD, the switching circuit allows the power supply to supply power to a corresponding load.

Abstract: A multiple level integrated circuit uses an array of oppositely oriented individually enabled buffers between through-silicon vias (TSVs) and a clocked flip-flop, for each of multiple signal lines that include TSVs. Applying and/or reading logic levels to and from the TSVs and associated flip-flops produces values that a logic element compares to expected values characterizing nominal operation or detects open and short circuit defects. A process associated with testing the TSVs during assembly comprises testing for short circuits and then exposing and connecting the TSVs via a conductive layer to check for open circuits.

Abstract: A device comprises a analysis section for detecting hold errors according to data including the values of the input and output nodes of the FF circuit, and identifying the node in which a hold error has occurred, a determining section for determining insertion of the trailing edge FF or the buffer into hold error sections on the basis of the results of the analysis by the analysis section, a FF insertion section for inserting the FF into a hold error section subjected to position determination so as to insert the trailing edge FF, and connecting a clock line to the FF based on the results of the determining section, and a buffer insertion section for inserting the buffer into the hold error section subjected to the position determination so as to insert the FF based on the results of data of the determining section.

Abstract: Data latch circuit and method of low power decision feedback equalization (DFE) system is disclosed. In one embodiment, the data latch circuit of the of a decision feedback equalization (DFE) system includes a first parallel n-channel metal-oxide-semiconductor field-effect transistor (NMOS) pair to input a differential input voltage. The data latch circuit also includes a second parallel NMOS pair coupled to the first parallel NMOS pair to input a decision feedback equalization (DFE) voltage. The data latch circuit further includes a cross-coupled PMOS pair to generate a positive feedback to the first parallel NMOS pair and/or the second parallel NMOS pair. In addition, the data latch circuit includes a cross-coupled NMOS pair to escalate the positive feedback. Furthermore the data latch circuit includes a latching circuit to generate a signal data based on the sinking of a current at an input of the latching circuit and/or the positive feedback.

Abstract: A nonvolatile latch circuit of the invention includes a variable resistance element which is formed by interposing an oxide layer between electrodes, and changes to a low resistance state by applying a voltage to cause current flow in the direction from the first to the second electrode, and changes to a high resistance state by applying a voltage to cause current flow in the reverse direction, wherein a first terminal of a transistor, a first terminal of other transistor, an output terminal of an inverter circuit, and an output terminal of other inverter circuit are respectively connected to one electrode, the other electrode, a second terminal of the transistor, and a second terminal of the other transistor, and a current flowing through the variable resistance element when changed to a low resistance state is smaller in absolute value than a current therethrough when changed to a high resistance state.

Abstract: Sequential electronic circuit (10) reacting on a rising edge and a falling edge of a clock signal (CK), comprising a first (1) and a second (2) D-type flip-flop, a main multiplexer (3) coupled at input to the flip-flops (1 and 2), the circuit (10) comprising a first input receiving the clock signal (CK) and a second input receiving a control signal (TE) so as to control the circuit (10) according to a normal operating mode and a test operating mode making it possible to check the proper operation of the sequential electronic circuit (10). The clock signal (CK) used in the normal operating mode is used to gate the circuit (10) during the test operating mode.

Abstract: A command control circuit of a semiconductor integrated device includes a plurality of latches sequentially connected and receiving a command signal, and a plurality of selection switches configured to pass or to interrupt the command signal inputted to each one of the plurality of latches.

Abstract: To provide a novel nonvolatile latch circuit and a semiconductor device using the nonvolatile latch circuit, a nonvolatile latch circuit includes a latch portion having a loop structure where an output of a first element is electrically connected to an input of a second element, and an output of the second element is electrically connected to an input of the first element; and a data holding portion configured to hold data of the latch portion. In the data holding portion, a transistor using an oxide semiconductor as a semiconductor material for forming a channel formation region is used as a switching element. In addition, a capacitor electrically connected to a source electrode or a drain electrode of the transistor is included.

Abstract: A dynamic latch has a pair of parallel pass gates (a first parallel pass gate that receives a seed signal, and a second parallel pass gate that receives a data signal). A first latch logic circuit performs logic operations using signals output by the parallel pass gates to produce an updated data signal. An additional pass gate is operatively connected to the first latch logic circuit. An additional pass gate controls passage of the updated data signal. An inverter receives the updated data signal from the pass gate, and inverts and outputs the updated data signal as an output data signal. Thus, the dynamic latch comprises two inputs into the pair of parallel pass gates and performs only one of four logical operations on a received data signal. The four logical operations are performed using the signals applied to the two inputs.

Abstract: A state machine for generating signals configured for generating different signals according to the current state of the machine. The state machine is configured to change state both as a function of an internal timer and as a function of signals representative of events external to the state machine.

Abstract: In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.

Abstract: The exemplary embodiments provide a reconfigurable integrated circuit architecture having a predetermined, unit timing increment (or delay) for both data operations and data word transfers within every zone and between zones, which are independent of application placement and routing. An exemplary IC comprises a plurality of circuit zones, with each zone comprising: a plurality of composite circuit elements, a plurality of cluster queues, and a full interconnect bus. Each composite circuit element comprises: a configurable circuit element circuit and an element interface and control circuit, with the element interface and control circuit comprising an input queue and an output queue. Each cluster queue comprises an element interface and control having an input queue and an output queue. The full interconnect bus couples every output queue within the zone to every input queue within the zone.

Abstract: A method and apparatus for processing data by a pipeline of a virtual multiple instance extended finite state machine (VMI EFSM). An input token is selected to enter the pipeline. The input token includes a reference to an EFSM instance, an extended command, and an operation code. The EFSM instance requires the resource to be available to generate an output token from the input token. In response to receiving an indication that the resource is unavailable, the input token is sent to a wait room or an initiative token containing the reference and the operation code is sent to a wait queue, and the output token is not generated. Without stalling and restarting the pipeline, another input token is processed in the pipeline while the resource is unavailable and while the input token is in the wait room or the initiative token is in the wait queue.

Abstract: The exemplary embodiments provide a reconfigurable integrated circuit capable of on-chip configuration and reconfiguration, comprising: a plurality of configurable composite circuit elements; a configuration and control bus; a memory; and a sequential processor. Each composite circuit element comprises: a configurable circuit; and an element interface and control circuit, the element interface and control circuit comprising an element controller and at least one configuration and control register to store one or more configuration and control words. The configuration and control bus is coupled to the plurality of configurable composite circuit elements, and comprises a plurality of address and control lines and a plurality of data lines. The sequential processor can write configurations to the configuration and control registers of an addressed configurable composite circuit element to configure or reconfigure the configurable circuit.

Abstract: This invention comprises a layout method to effectively protect logic circuits against soft errors (non-destructive errors) and circuit cells, with layout, which are protected against soft errors. In particular, the method protects against cases where multiple nodes in circuit are affected by a single event. These events lead to multiple errors in the circuit, and while several methods exist to deal with single node errors, multiple node errors are very hard to deal with using any currently existing protection methods. The method is particularly useful for CMOS based logic circuits in modem technologies (.ltoreq.90 nm), where the occurrence of multiple node pulses becomes high (due to the high integration level). It uses a unique layout configuration, which makes the circuits protected against single event generated soft-errors.

Abstract: Invocation language is described that is suitable for controlling a machine to perform a process having concurrent parts. Each concurrent part has an association relationship, a completeness relation, and an invocation expression.

Abstract: A method and system for direct construction of a minimal deterministic finite state machine corresponding to a regular expression are provided. The method includes providing a regular expression represented as a regular expression tree with nodes of operators and leaves of elementary character transitions and traversing the regular expression tree recursively to build minimal finite state automata (FSAs) corresponding to the branches of the tree, wherein the FSAs end in a specified tail automaton. The operators are concatenation, alternation, and Kleene closure. A concatenation operation is performed by recursive construction in reverse order wherein each automaton built becomes the tail for the preceding argument of the operation. An alternation operation is performed by recursively building automata corresponding to the arguments of the operation with the same tail and merging them.

Abstract: Exemplary techniques for turning off the clock signal to flip flops are described, which may reduce power consumption by electronic devices. In an implementation, a clock-gating logic turns off the clock signal to a flip flop when a data input of the flip flop remains untoggled. The reduction in power consumption is envisioned to also reduce heat generation.

Abstract: Some embodiments show a storage circuit with fault detection. The storage circuit comprises, first and second fault detection circuits each comprising a first stable state and a second stable state, wherein each of the first and the second fault detection circuits is configured such that a fault signal strength necessary to cause switching from the first stable state to the second stable state is different from a fault signal strength necessary to cause switching from the second stable state to the first stable state.

Abstract: An apparatus comprising a first circuit, a state machine, a compare circuit and a calibration circuit. The first circuit may be configured to generate a slew rate control signal and a calibration signal in response to (i) a plurality of control bits and (ii) an operation signal. The state machine may be configured to generate the operation signal and a plurality of intermediate control signals in response to (i) a compare signal and (ii) clock signal. The compare circuit may be configured to generate the compare signal in response to (i) a reference voltage and (ii) a capacitance signal. The calibration circuit may be configured to generate the capacitance signal in response to (i) the calibration signal and (ii) the plurality of intermediate control signals.

Abstract: Some embodiments of the invention provide an integrated circuit (IC) with configurable input/output (I/O) circuits for optimally operating with two or more interfaces. Some embodiments optimally operate over the two or more interfaces by supporting a particular voltage for each interface. Also, some embodiments optimally operate over two or more interfaces by supporting a particular frequency for each supported voltage whereby supporting a particular frequency involves producing sufficient current drive at each voltage to support the particular frequency.

Abstract: The disclosure relates generally to triple-redundant sequential state (TRSS) machines formed as integrated circuits on a semiconductor substrate, such as CMOS, and computerized methods and systems of designing the triple-redundant sequential state machines. Of particular focus in this disclosure are sequential state elements (SSEs) used to sample and hold bit states. The sampling and holding of bits states are synchronized by a clock signal thereby allowing for pipelining in the TRSS machines. In particular, the clock signal may oscillate between a first clock state and a second clock state to synchronize the operation of the SSE according to the timing provided by the clock states. The SSEs has a self-correcting mechanism to protect against radiation induced soft errors. The SSE may be provided in a pipeline circuit of a TRSS machine to receive and store a bit state of bit signal generated by combinational circuits within the pipeline circuit.

Abstract: A nonvolatile latch circuit of the invention includes a variable resistance element which is formed by interposing an oxide layer between electrodes, and changes to a low resistance state by applying a voltage to cause current flow in the direction from the first to the second electrode, and changes to a high resistance state by applying a voltage to cause current flow in the reverse direction, wherein a first terminal of a transistor, a first terminal of other transistor, an output terminal of an inverter circuit, and an output terminal of other inverter circuit are respectively connected to one electrode, the other electrode, a second terminal of the transistor, and a second terminal of the other transistor, and a current flowing through the variable resistance element when changed to a low resistance state is smaller in absolute value than a current therethrough when changed to a high resistance state.

Abstract: A signal processing unit with reduced power consumption is provided. A transistor in which a channel is formed in an oxide semiconductor is used for a storage circuit included in the signal processing unit, so that data can be held (stored) even while supply of power is stopped. Non-destructive reading can be performed on the data stored in the storage circuit even when supply of power to the signal processing unit is stopped.

Abstract: Vertical dithering is performed for vertical droop compensation in image processing using Linear Feedback Shift Registers (LFSRs). Line memories are not used. A compensation circuit includes a signature reload input signal coupled to the input of five LFSRs. Each LFSR includes a signature store. The output of each LFSR provides a sequence output signal that is gated with a corresponding enable signal in a first logic circuit. The output of all of the first logic circuits are combined in a second logic circuit to provide a control signal output.

Abstract: A data processing apparatus includes a reconfigurable circuit capable of reconfigurating partially a circuit configuration: and a reconfiguration controlling unit that controls a reconfiguration of the circuit configuration of the reconfigurable circuit. The reconfiguration controlling unit reconfigurates a plurality of partial circuits, which constitute one pipeline and are reconfigurated simultaneously on the reconfigurable circuit, on the reconfigurable circuit in sequence from a head partial circuit of the pipeline, and starts sequentially the reconfigurated partial circuits from a head.

Abstract: A high speed flip-flop circuit and a configuration method thereof are provided. A small number of transistors may be used to configure a flip-flop circuit, so that the flip-flop circuit may be operated at a high-speed. Additionally, an area occupied by the flip-flop circuit may be reduced, and power consumption may be reduced. Accordingly, the flip-flop circuit may be integrated together with a microwave frequency integrated circuit using a Gallium Arsenide (GaAs) compound semiconductor process.

Abstract: In some embodiments, new clock gating approaches, referred hereafter as State Transition Gating (STG) methods and circuits are provided. In areas of circuit designs including sequential elements, the use of STG may be used to reduce dynamic power consumption.

Abstract: In the electronic circuit device with stacked plural components of the same function, this invention enables to select an arbitrary component among plural components by a control element, without setting pre-determined identification information in each component. By installing a sequential logic circuit in each component, and changing a state of the sequential logic circuit by control data transmitted from the component stacked in a preceding stage or the control element, the state of the controlled component is set to a state that accepts a selection made by the control element.

Abstract: FPGAs and MPLDs, which are conventional programmable semiconductor devices, have had poor cost performance and did not suitably take long signal lines into account. To solve this, a flip-flop is built into each MLUT block comprised of a plurality of MLUTs, each MLUT comprising a memory and an address-data pair. With respect to the adjacent line between adjacent MLUTs, alternated adjacent line are introduced, while in the case of interconnects between non-adjacent MLUTs, dedicated distant line and, furthermore, a torus interconnect network are provided.

Abstract: A multiple level integrated circuit uses an array of oppositely oriented individually enabled buffers between through-silicon vias (TSVs) and a clocked flip-flop, for each of multiple signal lines that include TSVs. Applying and/or reading logic levels to and from the TSVs and associated flip-flops produces values that a logic element compares to expected values characterizing nominal operation or detects open and short circuit defects. A process associated with testing the TSVs during assembly comprises testing for short circuits and then exposing and connecting the TSVs via a conductive layer to check for open circuits.

Abstract: States included in a deterministic finite automaton are classified into states having the same input symbols associated with outgoing transitions and the same finality, and a calculates an intersection set between each of the state sets and a set of transition destination states which is obtained by translating each of states included in the state sets, until the number of states included in the intersection set becomes equal to one, while regarding the set of the transition destination states for each of the input symbol included in the intersection set as new state sets, and plural indistinguishable states are merged into one state by tracing a route in a reverse direction to a transition direction, when the number of states has become equal to one.

Abstract: A flip-flop is provided. The flip-flop includes a first latch circuit configured to latch a data signal in response to a plurality of first control signals or latch a scan input signal in response to a plurality of second control signals, and a second latch circuit configured to latch a signal output from the first latch circuit in response to complementary clock signals.

Abstract: A tree-like signal distribution network comprises a plurality of branches extending from a plurality of branching points. The distribution network comprises a plurality of control blocks, each control block being situated at a branching point of the tree-like distribution network, wherein each of the plurality of control blocks is arranged such that it can distribute a signal received from the tree-like distribution network, a locally generated signal, and a combination of a signal received from the tree-like distribution network and a locally generated signal.

Abstract: A distributable and serializable finite state machine and methods for using the distributable and serializable finite state machine are provided wherein finite state machine instance can be location-shifted, time-shifted or location-shift and time-shifted, for example by serializing and deserializing each instance. Each instance can be located-shifted between agents, and a persistent memory storage location is provided to facilitate both location-shifting and time-shifting. Finite state machine instances and the actions that make up each instance can be run in a distributed fashion among a plurality of agents.

Abstract: Clock switch-over circuits and methods provide clock signals to clock routing networks. According to one embodiment, a multiplexer selects between a first clock signal and a second clock signal in response to a switch select signal received from a control circuit. A storage circuit stores an enable signal in response to an output clock signal of the multiplexer. A logic circuit transmits the output clock signal of the multiplexer to a clock routing network in response to the enable signal from the storage circuit. At least one signal is transmitted from the clock switch-over circuit to the control circuit.

Abstract: Systems and methods for managing a write operation are described. The systems include a logic element (LE) including an N-input look-up table (LUT) having a configurable random access memory (CRAM) including 2N memory cells. The systems further include a write address decoder coupled to the LE and a write address hard logic register that stores an address of one of the memory cells. N is an integer. The hard logic register removes a dependency of a timing relationship between a write address launch and a write to the CRAM on a design of an integrated circuit.

Abstract: The disclosed embodiments provide a first-in, first-out (FIFO) circuit that operates asynchronously. The FIFO circuit includes a data path that contains data latches sequentially connected through data-wire segments. The FIFO circuit also includes a control circuit that generates control signals for the data latches so that the data path behaves like a FIFO. The control circuit includes control components sequentially connected to each other through control-wire segments and repeaters located within the control-wire segments. The control components are configured to asynchronously generate the control signals for the data latches, and the repeaters are configured to repeat asynchronous signals communicated between the asynchronous control components.

Abstract: In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.

Abstract: A method and apparatus that controls the clock of a digital circuit, and therefore power consumption, without substantially comprising performance is provided. The apparatus may include monitoring the utilization of a First in First Out (FIFO) buffer. For example in a systems and methods according to the invention, clock speed may be reduced when the FIFO is relatively empty and increased when the FIFO is relatively full. The clock speed may be controlled by a phase locked loop, a clock divider, a clock masking device or a combination of more than one of these methods. Power reduction may also be obtained by controlling the clocking of different stages of a pipelined device. One or more aspects of the inventions may be implemented in combination with other aspects of the invention to further reduce power use.

Abstract: To provide a semiconductor device which operates stably with few malfunctions due to noise, with low power consumption, and little variation in characteristics; a display device including the semiconductor device; and an electronic device including the display device. An output terminal is connected to a power supply line, thereby reducing variation in electric potential of the output terminal. In addition, a gate electrode potential which turns ON a transistor is maintained due to the capacitance of the transistor. Further, change in characteristics of the transistor is reduced by a signal line for reverse bias.

Abstract: The fast round robin circuit includes AND gates, OR gates, multiplexers and four D flip-flop gates configured to handle requests using linear propagation of a single grant token. In this manner the device avoids wasting clock cycles when some of the arbitrated entities do not have a pending request. The circuit has an R stage and an S stage. The R stage contains the request signal and an R memorization element to memorize the request. The S stage is the arbitration stage where the next active request is selected based on the position of the current request. The selection is then memorized in an S selection bit memorization element. There is one request signal and one pair of R and S Flip-Flops associated to every requesting entity. The selection circuit skips inactive requests to enable the next active request in a polling direction defined by the circuit.

Abstract: Some embodiments provide a configurable integrated circuit (IC) comprising multiple deskew circuits for delaying data passage. Each of the deskew circuits comprises a stepwise delay circuit with multiple outputs and an input selection circuit with multiple inputs. Multiple outputs connect to multiple inputs.

Abstract: A combinatorial circuit with pre-calculation and having shorter delay is described. The combinatorial circuit uses information available from earlier input signals to pre-calculate intermediate signals, which are used to generate output signals when the last input signal arrives. The combinatorial circuit includes an input calculation block, at least one pre-calculation block, and an output calculation block coupled in series. The input calculation block receives some input signals and generates intermediate signals for the first pre-calculation block. The pre-calculation block(s) receive at least one earlier input signal and generate additional intermediate signals. The output calculation block receives the latest input signal and the intermediate signals from the last pre-calculation block and generates the output signals. The pre-calculation block(s) and the output calculation block may be implemented with simple circuits.

Abstract: Specific logic gates for q-gating are selected by determining the minimum leakage state for a circuit design and then selecting logic gates that hold the circuit design in its lowest leakage state. Depending on the input desired to implement the minimum leakage state, the gate may be selected as a NOR or OR gate. Q-gating that is implemented with gates chosen to implement the minimum leakage state may be enabled during selected operating modes. The minimum leakage state of a circuit can be determined with an automatic test pattern generation (ATPG) tool.

Abstract: Two latches store the state of a data signal at a transition of a clock signal. Comparison logic compares the outputs of the two latches and produces a signal to indicate whether the outputs are equal or unequal. Systems using the latches and comparison logic are described and claimed.

Abstract: FPGAs and MPLDs, which are conventional programmable semiconductor devices, have had poor cost performance and did not suitably take long signal lines into account. To solve this, a flip-flop is built into each MLUT block comprised of a plurality of MLUTs, each MLUT comprising a memory and an address-data pair. With respect to the adjacent line between adjacent MLUTs, alternated adjacent line are introduced, while in the case of interconnects between non-adjacent MLUTs, dedicated distant line and, furthermore, a torus interconnect network are provided.