Abstract: A method of preventing current leakage in logic circuits within level sensitive scan design (LSSD) latch circuits in an application specific integrated circuit (ASIC). When the ASIC is in a manufacturing test mode, a gating signal at an input terminal of a power gating circuit is set to exceed a threshold voltage of transistors within the power gating circuit. The gating signal thus causes the power gating circuit to enable electrical current to reach the LSSD latch circuits. When the ASIC is in a normal functional mode, the gating signal is set below the threshold voltage. The gating signal thus causes the power gating circuit to prevent electrical current from reaching particular logic circuits (e.g., scan logic) within the LSSD latch circuits, thereby conserving power within the ASIC by preventing current leakage and heat generation in the LSSD latch circuit.

Abstract: The present invention is directed to margin characterization of memory devices, such as interface ASICs connected to SDRAM. The circuits and method perform margin characterization on a chip during wafer test; however the characterization could also be performed at module test or in a system.

Abstract: Exemplary techniques for turning off the clock signal to flip flops are described, which may reduce power consumption by electronic devices. In an implementation, a clock-gating logic turns off the clock signal to a flip flop when a data input of the flip flop remains untoggled. The reduction in power consumption is envisioned to also reduce heat generation.

Abstract: A modified high-speed flip-flop including an input circuit, a smart window circuit, a smart keeper circuit, a pre-charge circuit, a discharge circuit, a slave storage circuit, and an output circuit. Additionally, a circuit including the modified high-speed flip-flop, the circuit also including a non-zero operating voltage provided to the flip-flop, a common voltage provided to the flip-flop, a clock signal input to the flip-flop, a data signal input to the flip-flop wherein the data signal has a high state and a low state, and an output signal from the flip-flop wherein the output signal has a high state and a low state.

Abstract: Circuits, methods, and apparatus are directed to sharing input and output functionality. A timing circuit usable for input and output functionality may be combined with another timing circuit to provide additional input/output functionality or to reduce the number of circuit elements for input/output functionality. For example, two timing circuits may be used to provide double data-rate input while still providing output functionality, or vice versa. Two timing circuits may also provide output that is timed and gated with an output enable signal.

Abstract: An apparatus, system, and method are described for synchronously resetting logic circuits. A synchronous reset signal is coupled to at least one asynchronous reset input for synchronously resetting sequential logic. In one embodiment, reset logic generates a signal coupled to the at least one asynchronous reset input of the sequential logic to synchronously reset the sequential logic.

Abstract: A dual function serial and parallel data register with integrated program verify functionality. The master and slave latching circuits of the dual function data register can concurrently store two different words of data. In a program verify operation, the master latch stores program data and the slave latch will receive and store read data. Comparison logic in each register stage will compare the data of both latches, and integrate the comparison result to that of the previous register stage. The final single bit result will indicate the presence of at least one bit that has not been programmed. Automatic program inhibit logic in each stage will prevent successfully programmed bits from being re-programmed in each subsequent reprogram cycle. Either data word can be serially clocked out by selectively starting the shift operations on either the low or high active logic level of a clock signal.

Abstract: The invention relates to a method of, and system for, linear speed control for an electric motor, in which a digital to analog converter means is used for converting an 8-bit digital signal to an analog voltage for setting voltage across a motor, a digital state machine means is used for converting the duty cycle of an input signal for output to the digital to analog converter means, and a closed loop feedback loop means is used for monitoring and setting the voltage across the motor. An over-current sense circuit can be used for monitoring the current across the electric motor. An over/under voltage sense circuit can be used for monitoring voltage of the electric motor. The resulting 8-bit digital control signal is converted to an analog voltage for the electric motor. Such methods and systems find particular use in automotive applications.

Abstract: Two latches store the state of a data signal at a transition of a clock signal. Comparison logic compares the outputs of the two latches and produces a signal to indicate whether the outputs are equal or unequal. Systems using the latches and comparison logic are described and claimed.

Abstract: An apparatus for providing active mode power reduction for circuits having data retention includes a master slave flip flop (MSFF) for latching a data input. An output level shifter (OLS), coupled to the MSFF, retains the data input in response to the MSFF being operable in an active power saving mode (APSM) to reduce power. The OLS operating in the APSM provides a level shifter output having a configurable voltage, thereby providing output isolation. A change in an operating mode of the MSFF between an active mode and the APSM is independent of a retention (RET) mode input.

Abstract: A circuit having a local power block for leakage reduction is disclosed. The circuit has a first portion and a second portion. The first portion is configured to operate at a substantially greater operating frequency than the operating frequency of the second portion. The second portion has a local power block configured to decouple the second portion if the second portion is inactive to reduce leakage current associated with the second portion without sacrificing performance of the first portion.

Abstract: A method for detecting a malfunction in a state machine is described. The state machine has an operation modeled by a set of states linked to each other by transitions, the state machine generating, upon each transition, output signals according to input signals comprising signals generated during a previous transition. During a transition, the method comprises steps of generating at least one control signal according to a control signal generated during a previous transition, determining an expected value of the control signal, and comparing the control signal with the expected value.

Abstract: Configurable time-borrowing flip-flops are provided for circuits such as programmable logic devices. The flip-flops may be based on a configurable delay circuit and two latches or may be based on a configurable pulse generation circuit and a single latch. In designs based on two latches, a first and a second latch are arranged in series. A clock signal is delayed using a configurable delay circuit. Programmable memory elements that have been loaded with configuration data may be used to adjust how much delay is produced by the configurable delay circuit. The delayed version of the clock signal is provided to a clock input associated with the first latch. The second latch has a clock input that receives the clock signal without delay. In designs based on a single latch, a configurable pulse generation circuit receives a clock signal for the flip-flop and generates a corresponding clock pulse for the latch.

Abstract: A nano-electron fluidic logic (NFL) device for controlling launching and propagation of at least one surface plasma wave (SPW) is disclosed. The NFL device comprises a metallic gate patterned with a plurality of terminals at which SPWs may be launched and a plurality of drain terminals at which the SPWs may be detected. A wave guiding structure such as a 2 DEG EF facilitates propagation of the SPW within the structure so as to scatter/steer the SPW in a direction different from a pre-scattering direction. A bias SPW is excited by an application of a control SPW with a momentum vector at an angle to the bias SPW and a control current with a wavevector which scatters the bias SPW in the direction of at least one output SPW, towards a drain terminal. The NFL device being rendered with device speed as a function of SPW propagation velocity.

Abstract: A system and method for implementing a state machine including a plurality of states, the state machine configured to transition from a present state to a next state in response to input. One embodiment of the system includes a plurality of state elements, each of the plurality of state elements representing one of the plurality of states of the state machine, each of the plurality of state elements receiving an on signal, an off signal, and a synchronizing signal, each of the state elements outputting a state value, each of the plurality of state elements further including a logic element to store a temporary state value, wherein the state value is updated by the temporary state value in response to the synchronizing signal, and wherein the state value of each of the plurality of state elements is synchronously updated in response to the synchronizing signal.

Abstract: A cell element field for data processing, having function cell means for execution of algebraic and/or logic functions and memory cell means for receiving, storing and/or outputting information is described. Function cell-memory cell combinations are formed in which a control connection leads from the function cell means to the memory cell means.

Abstract: The invention provides a shift register which can operate normally while suppressing a delay of signal and a rounding of waveform. The shift register of the invention includes a plurality of stages of flip-flop circuits each of which includes a clocked inverter. The clocked inverter includes a first transistor and a second transistor which are connected in series, a first compensation circuit including a third transistor and a fourth transistor which are connected in series, and a second compensation circuit including a fifth transistor and a transmission gate. According to the first compensation circuit, a timing at which a signal outputted from the flip-flop circuit rises or falls can be controlled in synchronization with an output of two stages before. The second compensation circuit can control a clock signal input can be controlled.

Abstract: A programmable logic device including a plurality of logic elements organized in an array. Each of the logic elements includes an N-stage Look Up Table structure having 2N configuration bit inputs and a Look Up Table output. The first stage of the Look Up Table includes 2N tri-state buffers coupled to receive the 2N configuration bit inputs respectively. A decoder, configured from logic gates, is coupled to receive to one or more Look Up Table select signals and to generate a set of control signals to control the 2N tri-state buffers so that one or more of the 2N configuration bit inputs is selected by the first stage. The configuration bits are then provided to subsequent muxing stages in the Look Up Table.

Abstract: Various types of memory circuits are described. A memory circuit may include a state-storage feedback loop coupled to a first data input and to a second data input. The first data input is introduced into the feedback loop at a first set of points, and the second data input is introduced into the feedback loop at a second set of points.

Abstract: Circuits, methods, and apparatus for the dynamic control of calibration data that adjusts the timing of input and output signals on an integrated circuit. This dynamic control allows input and output circuits to self-calibrate by compensating for temperature and voltage changes in an efficient manner, without the need for device reconfiguration. Calibration settings can be maintained while new calibration settings are loaded. Skew between clock and data signals, as well as among multiple data signals, can be reduced. Dynamic control is achieved while consuming only a minimal resources including route paths.

Abstract: Method and apparatus for testing input/output circuits of an integrated circuit are described. An integrated circuit includes input/output circuits having input/output pads. The input/output pads are capable of being coupled together to a tester channel. The input/output circuits each are configurable via configuration circuitry to be in either a first mode or a second mode responsive to a select circuit of the configuration circuitry coupled to receive a first input for the first mode and a second input for the second mode. The select circuit is controlled responsive to a control select signal common to all or a portion of the select circuits of each of the input/output circuits.

Abstract: An integrated circuit design method includes: classifying flipflops arranged around a macro based on a netlist of a integrated circuit incorporating the flipflops and the macro; and generating a flipflop-replaced netlist from the netlist. In classifying the flipflops, a flipflop which is connected to an input terminal of the macro directly or through an input-side logic cone and operated on the same clock signal as the macro is classified as a control type, and a flipflop which has a data output connected to an input terminal of the macro directly or through the input-side logic cone and operated on a different clock signal is classified as a hold type.

Abstract: A diagnosable structured logic array and associated process is provided. A base cell structure is provided comprising a logic unit comprising a plurality of input nodes, a plurality of selection nodes, and an output node, a plurality of switches coupled to the selection nodes, where the switches comprises a plurality of input lines, a selection line and an output line, a memory cell coupled to the output node, and a test address bus and a program control bus coupled to the plurality of input lines and the selection line of the plurality of switches. A state on each of the plurality of input nodes is verifiably loaded and read from the memory cell. A trusted memory block is provided. The associated process is provided for testing and verifying a plurality of truth table inputs of the logic unit.

Abstract: An integrated circuit device has a state-saving feature and includes a programmable logic block, I/O pads, a dedicated register, at least one volatile memory block, a non-volatile memory block, a condition-sensing circuit for detecting at least one condition, A control circuit such as a state machine controls the saving of states of various volatile memories and registers to the non-volatile memory and also controls the initialization of the volatile registers and memories using the saved state data.

Abstract: State machines using resistivity-sensitive memory elements are disclosed. The state machine includes a next state logic comprising a non-volatile memory including a resistivity-sensitive memory element and receiving an input, a state storage device connected to the next state logic including a connection to provide a state of the state machine to the next state logic, and an output connect to the state register to output the state of the state machine. The resistivity-sensitive memory elements may be two-terminal resistivity-sensitive memory elements. The two-terminal resistivity-sensitive memory elements may store data as a plurality of conductivity profiles that can be non-destructively read by applying a read voltage across the terminals of the memory elements, and new data can be written by applying a write voltage across the terminals. The two-terminal resistivity-sensitive memory elements retain stored data in the absence of power and may be configured into a two-terminal cross-point memory array.

Abstract: A circuit is attached in parallel to a universal serial bus interface of a data processing system. A capacitor in the circuit is charged by receiving power from a power pin of the universal serial bus interface while the data processing system is not in a reduced power state. A vibration sensor is unpowered while the data processing system is not in a reduced power state. The vibration sensor is disconnected from a data pin of the universal serial bus interface while the data processing system is not in a reduced power state. When the data processing system enters a reduced power state, the capacitor provides power to the vibration sensor. When a vibration is detected by the vibration sensor, a switch connects the vibration sensor to the data pin of the universal serial bus interface, providing a wake up signal to the data processing system.

Abstract: Circuits and methods of concatenating first-in-first-out memory circuits (FIFOs). A concatenated FIFO includes first and second FIFOs. The data output terminals of the first FIFO are coupled to the data input terminals of the second FIFO. The read clock of the second FIFO is the system read clock, and the write clock of the first FIFO is the system write clock. Communication between the first and second FIFOs is controlled by the faster of the two system clocks. A control circuit coupled to both the first and second FIFOs has a local clock input terminal coupled to the read clock input terminal of the first FIFO and the write clock input terminal of the second FIFO. The control circuit is driven by status signals from the first and second FIFOs, and generates a read enable signal for the first FIFO and a write enable signal for the second FIFO.

Abstract: The present invention relates to a system and method for increasing the manufacturing yield of a plurality of memory cells used in cell arrays. A programmable fuse, having both hardware and software elements, is used with the plurality of memory cells to indicate that at least one memory cell is unusable and should be shifted out of operation. The software programmable element includes a programmable register adapted to shift in an appropriate value indicating that at least one of the memory cells is flawed. The hardware element includes a fuse gated with the programmable register. Shifting is indicated either by software programmable fuse or hard fuse. Soft fuse registers may be chained together forming a shift register.

Abstract: Reducing power consumption in latches and similar electronic devices. In one aspect, an apparatus for configuring power consumption of sequential logic includes a sequential logic device including a first latch, a second latch, and first and second enable inputs. The first enable input enables and disables the first and second latches, and the second enable input enables and disables the second latch and does not affect the first latch. The first enable input has an earlier required signal arrival time than the second enable input to be effective for a particular clock cycle. A circuit configures the sequential logic device at operating time to consume less power during a lower frequency of operation of the sequential logic device, and to consume more power during a higher frequency of operation.

Abstract: Some embodiments provide a configurable IC that includes a configurable routing fabric with storage elements. In some embodiments, the routing fabric provides a communication pathway that routes signals to and from source and destination components. The routing fabric of some embodiments provides the ability to selectively store the signals passing through the routing fabric within the storage elements of the routing fabric. In this manner, a source or destination component continually performs operations (e.g., computational or routing) irrespective of whether a previous signal from or to such a component is stored within the routing fabric. The source and destination components include configurable logic circuits, configurable interconnect circuits, and various other circuits that receive or distribute signals throughout the configurable IC.

Abstract: A method for specifying reactive systems using Dynamic State Machines (DSMs) is disclosed. The method extends statecharts in three areas. One is the integration of a group of related finite state machines (FSMs) into a single and powerful entity supporting multiple repeatable concurrent communication sessions. The second is the support for composite transitions to model various parallel event patterns or nested event patterns, which occur in the real world, and to significantly improve the readability of state diagrams. The third is the addition of a parallel-OR composite state to support the OR-termination semantics of a parallel composite state.

Abstract: A flip-flop circuit of the present invention includes a first switch and a second switch which are connected in series to each other. The first switch includes: two input ports upon which light source light and signal light are incident; two output ports for outputting an optical output; and a thermal lens forming element for forming a thermal lens in a predetermined optical inputting condition. Although the second switch is composed in the same manner as that of the first switch, a relation between the wave-lengths to be utilized is inverted. When a state is changed from OFF to ON, a pulse signal is inputted for setting and one of the rays of output light of the second switch is fed-back to the first switch so as to maintain the state of ON. When the state is changed from ON to OFF, a pulse of additional signal light is inputted. Due to the foregoing, the two states of ON and OFF can be stably maintained.

Abstract: A method for protecting a state machine having an operation modeled by a set of states linked to each other by transitions, the state machine evaluating output signals upon each transition during an evaluation phase according to input signals comprising signals evaluated during a previous transition, the method comprising steps of determining a minimum duration of each evaluation phase according to a minimum duration to evaluate the output signals according to the input signals, and of adjusting the duration of each evaluation phase.

Abstract: A nonvolatile programmable logic circuit using a ferroelectric memory performs a nonvolatile memory function and an operation function without additional memory devices, thereby reducing power consumption. Also, a nonvolatile ferroelectric memory is applied to a FPGA (Field Programmable Gate Array), thereby preventing leakage of internal data and reducing the area of a chip.

Abstract: An integrated circuit includes a data node, an output node, and set logic coupling to the data node to the output node. The set logic changes a state of the output node in response to a change in state of the data node. The integrated circuit also includes a reset transistor, coupled to the data node, that resets the data node to a first state in response to a transition in a timing signal, an input transistor, coupled to the data node, that asserts the data node to a second state in response to receipt of a data signal, and reset logic coupled between the output node and the data node. The first reset logic resets the output node to an original state in response to resetting of the data node if the output node achieves a set state. The integrated circuit further includes feedback logic coupled between the output node and a reset input node of the reset logic that limits a duration of operation of the reset logic.

Abstract: A method is disclosed that includes propagating data via a first data path of a sequential circuit element in response to a clock signal received at a single clocked transistor of the sequential circuit element. The method also includes retaining information related to the data propagated via the first path at a retention circuit element of a second data path, where the first data path includes a first transistor that is responsive to an output of the single clocked transistor. The first transistor has a higher current flow capacity than a second transistor associated with the second data path.

Abstract: A PLD (200) includes a power management unit (PMU 210) that selectively implements one or more different power-reduction techniques in response to power configuration signals (PC). By manipulating the PC signals, the PMU can independently enable/disable various supply voltage circuits (110, 120, 130) that power CLBs (101), IOBs (102), and configuration memory cells (106), can generate a capture signal that causes data stored in storage elements of the CLBs to be captured in configuration memory cells, and/or can switch power terminals of configuration memory cells between voltage supply circuits. Also, the PMU can sequentially apply and remove power from a number of configurable PLD portions in response to the PC signals, wherein each configurable portion may include any number of the PLD's resources.

Abstract: The present invention relates to a system and method for increasing the manufacturing yield of a plurality of memory cells used in cell arrays. A programmable fuse, having both hardware and software elements, is used with the plurality of memory cells to indicate that at least one memory cell is unusable and should be shifted out of operation. The software programmable element includes a programmable register adapted to shift in an appropriate value indicating that at least one of the memory cells is flawed. The hardware element includes a fuse gated with the programmable register. Shifting is indicated either by software programmable fuse or hard fuse. Soft fuse registers may be chained together forming a shift register.

Abstract: Sequential circuitry comprising a data input, a data output, a clock signal input and a clamp signal input is disclosed. The sequential circuitry is arranged to clock a data signal received at said data input into said sequential circuitry in response to a clock signal received at said clock signal input, and to output a data signal from said sequential circuitry at said data output in response to said clock signal. The sequential circuitry is responsive to a predetermined value at said clamp signal input to switch to a low power mode and to set said data output to a forced value, while retaining said sequential state within said circuitry, said forced value being selected to reduce leakage power from combinatorial circuitry arranged to receive said output data signal.

Abstract: A non-volatile-memory-transistor based lookup table for an FPGA includes a n:1 multiplexer. A non-volatile memory transistor is coupled to each of the n inputs of the multiplexer. The multiplexer has x address inputs wherein 2x=n as is known in the art. The output of the multiplexer is coupled to Vcc through a pullup transistor. The gate of the pullup transistor is coupled to the output of an address transition detector circuit that has inputs coupled to the address inputs of the multiplexer. A sense amplifier is coupled to the output of the multiplexer.

Abstract: A dynamic and differential CMOS logic style is disclosed in which a gate uses a fixed amount of energy per evaluation event. The gate switches its output at every event and loads a constant capacitance. The logic style is a Dynamic and Differential Logic (DDL) style. The DDL style logic typically has one charging event per clock cycle and the charging event does not depend on the input signals. The differential feature masks the input value because a precharged output nodes is discharged during the evaluation phase. The dynamic feature breaks the input sequence: the discharged node is charged during the subsequent precharge phase.

Abstract: A semiconductor storage device, comprising: a first port to write data to a storage element; and a second port to read a signal generated by the storage element, wherein reading the generated signal protects data stored at the storage element from a read condition disturbance.

Abstract: An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.

Abstract: An implementation of multiplexer functionality using a multiplexer having half the number of input ports as it has possible output values is provided. A multiplexer having two data input ports performs the function of a multiplexer having four predetermined data input signals (A1, A2, A3, A4). In general, a multiplexer having only m data input ports performs the function of a multiplexer having twice as many predetermined data input signals A1, A2, . . . , Aj, where j=m*2. The multiplexer functionality may be implemented using a programmable device having one or more macrocells, an inverter and switches such as antifuses.

Abstract: Techniques are provided to hardware debug a programmable logic integrated circuit that includes a hardware intellectual property block (HIP). The HIP includes a logic circuit and state machine(s). The state machine outputs state machine information depending on selected signals within the logic circuit. The HIP block can also output data from a number of internal registers/flip-flops. Optional data registering logic can capture the state machine information and output it to a data bus.

Abstract: A field programmable gate array logic cell includes a logic circuit having three inputs and at least one output and a plurality of multiplexers having inputs and outputs. The logic circuit also includes a plurality of programmable elements coupled between the three inputs and at least one output of the logic circuit and the inputs and outputs of the plurality of multiplexers such that a plurality of sequential logic units and combinatorial units can be realized by programming selected ones of the programmable elements, the sequential logic units may include a flip-flop.

Abstract: Reducing power consumption in latches and similar electronic devices. In one aspect, an apparatus for configuring power consumption of sequential logic includes a sequential logic device including a first latch, a second latch, and first and second enable inputs. The first enable input enables and disables the first and second latches, and the second enable input enables and disables the second latch and does not affect the first latch. The first enable input has an earlier required signal arrival time than the second enable input to be effective for a particular clock cycle. A circuit configures the sequential logic device at operating time to consume less power during a lower frequency of operation of the sequential logic device, and to consume more power during a higher frequency of operation.

Abstract: A logic circuit apparatus that allocates process capability to unit circuits operated in a time divisional manner, including a circuit arrangement information memory which stores circuit arrangement information corresponding to each of plurality of unit circuits, and a programmable logic circuit with a circuit arrangement which can be reconfigured by employing the circuit arrangement information while the programmable logic circuit is being operated, a process data memory which stores both input data and output data related to a process operation of each of the circuits, and a controller which monitors a storage amount of the input data and/or a storage amount of the output data corresponding to each unit circuit, and which controls reconfiguration of the circuit arrangement of the programmable logic circuit when the storage amount satisfies a certain condition.

Abstract: Embodiments of the invention relate to a method and system to implement a DDR interface, such as a high-speed encode/decode interface. In one embodiment, a method of encoding data comprises the acts of (1) receiving a first signal, a second signal, and a first clock signal common to the first and second signals; (2) detecting rising edges and falling edges of the first clock signal; and (3) generating a composite signal based at least in part on the first and second signals and the detected rising and falling edges. The composite signal is associated with a second clock signal that is generated based at least in part on the detected rising and falling edges and on a time delay relative to the first clock signal.

Abstract: A programmable logic device may comprise a plurality of programmable resources and non-volatile configuration memory to store configuration data by which to configure the programmable resources. Test override circuitry may determine a test mode and selectively override the configuration data stored in the non-volatile configuration memory during the test mode for configuring the programmable resources based at least in part on test configuration data other than the configuration data stored in the non-volatile memory. A buffer may be operable to drive a configuration select node for at least one of the programmable resources for designating a configuration therefore based on the configuration data of the non-volatile memory. The test override circuitry may comprise a pull-down circuit operable, when enabled dependent on the test configuration data, to drive the buffer with a high/low level capable of overriding a state of the non-volatile configuration memory.