Abstract: The protection circuit of the present invention addresses the problem of indeterminate logic levels caused by loss of one of the power supplies in a two-power-supply CMOS integrated circuit. The circuit of the present invention replaces the typical scheme of power supply sequencing to fix the problem. The circuit disclosed herein detects the state of the core voltage and disables the output drivers when the core voltage is detected as being off. The disabled drivers are put into a high impedance state, thereby eliminating the potential for damage and eliminating the need for power supply sequencing. The invention also protects against the sudden loss of the integrated circuit core voltage, VDD, power supply during normal operation.

Abstract: In a specialized functional region of a programmable logic device, in which certain components may not be used, those components can be placed in a low-power mode so that they do not switch. For example, in an adder which is not being used but is receiving inputs, the current path for the adding circuitry is interrupted, while the output is forced low. If the adder is a carry/look-ahead adder, the GENERATE and PROPAGATE signals normally used in subsequent stages to predict the value of the carry signal are forced to constant values even if the inputs to the adder are changing.

Abstract: A small sized tri-state buffer circuit that realizes a higher integration of semiconductor integrated circuits is provided. The tri-state buffer circuit includes an AND device that obtains a logical product of an input signal IN and a control signal, inverts the logical product and outputs the same, a P-channel transistor having a gate that is supplied with a signal outputted from the AND device and a source that is supplied with a first power supply voltage, a first N-channel transistor that is complementarily connected with the P-channel transistor, and a second N-channel transistor that allows a current to flow from a source of the first N-channel transistor to a second power supply voltage according to the control signal.

Abstract: Systems and methods are provided for improving signal propagation. A repeater segments a transmission line into a first and a second line. The repeater includes an inverting amplifier and an equilibration circuit. The inverting amplifier has an input connected to the first line and an output connected to the second line. The amplifier receives and an input signal at a first logic potential and transmits an output signal at an inverted second logic potential during and an active portion of a cycle. The equilibration circuit electrically isolates the first line and the second line and shorts the first line to the second line during and an inactive portion of the cycle. Upon completion of the inactive portion of the cycle, the first line and the second line have substantially equal starting potentials between the first logic potential and the second logic potential.

Abstract: A method and apparatus for providing programmable active termination of transmission lines with substantially reduced DC power consumption.

Abstract: The input-output buffer circuit is provided with a PMOS transistor and an NMOS transistor which form an output driver which are ordinary MOS transistors instead of high breakdown voltage transistors. A resistor is inserted between drains of those MOS transistors and an external terminal. The resistance of this resistor is such that it generates a voltage drop as to cause a potential of drains of the PMOS transistor and the NMOS transistor not to exceed a voltage which can be safely applied to those MOS transistors and to become a potential which is at least a threshold level of an input buffer, when a current path extending from the external terminal to a power supply terminal through a parasitic diode of the PMOS transistor is formed.

Abstract: A buffer circuit has a high-impedance function mode. The buffer circuit is for outputting a buffer output level. The buffer circuit comprises a buffer output control section for controlling the buffer output level to an opposite level in a moment before the buffer circuit becomes the high-impedance function mode. The opposite level is a level opposite to a present buffer output level.

Abstract: A tristate buffers includes a logic circuit which outputs a high-level signal. The output signal is fed to gates of 1st and 2nd P-channel MOS transistors (TRs). A 3rd PMOS TR has a gate connected to a drain of the 2nd PMOS TR, and a drain connected to a drain of the 1st PMOS TR. A 4th PMOS TR has a gate connected to the drain of the 1st PMOS TR, and a drain connected to the drain of the 2nd PMOS TR. A 1st NMOS TR and a 2nd NMOS TR have their drains connected respectively to the drains of the 1st and the 3rd PMOS TRs and the drains of the 2nd and the 4th PMOS TRs. A 3rd NMOS TR and a 4th NMOS TR are connected respectively between the source of the 1st NMOS TR and ground and the source of the 2nd NMOS TR and the ground. The drains of the 1st and the 3rd PMOS TRs and the 1st NMOS TR are connected to an inverter. A 5th PMOS TR is connected to the drains of the 2nd and the 4th PMOS TRs and the 2nd NMOS TR.

Abstract: A small sized tri-state buffer circuit that realizes a higher integration of semiconductor integrated circuits is provided. The tri-state buffer circuit comprises an AND device 12 that obtains a logical product of an input signal IN and a control signal OE, inverts the logical product and outputs the same, a P-channel transistor QP1 having a gate that is supplied with a signal outputted from the AND device and a source that is supplied with a first power supply voltage, a first N-channel transistor QN1 that is complementarily connected with the P-channel transistor, and a second N-channel transistor QN2 that allows a current to flow from a source of the first N-channel transistor to a second power supply voltage according to the control signal.

Abstract: A circuit and a method for setting a digital potential at an integrated circuit output pin in which pull up/pull down circuitry holds a defined value at the output pin during the power down of the integrated circuit. A primary driver responsive to a state of the integrated circuit sets the output pin while the integrated circuit is in an active mode of operation, and secondary driver sets the output pin while the integrated circuit is in an inactive mode of operation. Control logic is provided as being responsive to a change in the mode of operation of the integrated circuit from its active mode to its inactive mode for generating a control signal relative to the state of the integrated circuit.

Abstract: A method and apparatus for implementing a dual voltage driver circuit having two predrive circuits for driving the supported voltages. The driver circuit automatically senses the operating voltage and selects the appropriate predrive circuitry while isolating the non-selected predrive circuitry from the sensed voltage.

Abstract: An output driver on an integrated circuit (IC) includes at least one transistor that has a thicker gate oxide than other standard transistors in the IC. In one embodiment, the output driver includes two pull-up transistors. A first pull-up transistor has a thicker gate oxide than standard transistors on the IC to provide a wide range of output voltages on the pad. A second pull-up transistor has a standard, i.e. thin, gate oxide thickness to ensure a fast low-to-high voltage transition on the pad. The other transistors in the output driver have standard gate oxide thicknesses. Illustrative thicknesses include 150 Angstroms for the first pull-up transistor and 50 Angstroms for the second pull-up transistor.

Abstract: A pull-up circuit has substantially linear current-voltage (I-V) characteristics for use in a bus system, such as in an open drain bus architecture type system. Operation in the linear region of the I-V characteristics is useful in high frequency input/output circuits. The pull-up circuit includes a transistor and a single termination resistor coupled to the transistor, and is simpler than other types of pull-up circuits. This simplicity in design saves area on a chip. The termination resistor in the pull-up circuit can be an n-well resistor formed on the same chip as the transistor, thereby further contributing to the savings in chip area.

Abstract: A P-channel transistor is disclosed having P+ source and drain regions formed in a N− well, which is formed in a P− substrate. A third P+ region is provided that functions as a well tie. When the P-channel transistor is used as the pull-up transistor in a CMOS “push-pull” output buffer circuit, the P+ well tie prevents undesired current flow from the bus back to the positive voltage supply. This prevents potential damage to the power supply plane and any additional components connected thereto. In another aspect, the N− well has formed therein both a P+ and N+ well tie. Additional switch circuitry is provided which allows for upper level programmability or selection of either one or both of the two well ties, depending upon the ultimate circuit configuration.

Abstract: The input-output buffer circuit is provided with a PMOS transistor and an NMOS transistor which form an output driver are determined to be ordinary MOS transistors instead of high breakdown voltage transistors. A resistor is inserted between drains of those MOS transistors and an external terminal. The resistance of this resistor is such that it generates a voltage drop as to cause a potential of drains of the PMOS transistor and the NMOS transistor not to exceed a voltage which can be applied to those MOS transistors and to become a potential which is at least a threshold level of an input buffer, when a current path extending from the external terminal to a power supply terminal through a parasitic diode of the PMOS transistor is formed.

Abstract: A buffer circuit comprises a data input terminal; an enabling terminal inputting an enabling signal; an output terminal; a first power source terminal supplying high potential voltage; a second power source terminal supplying low potential voltage; a first N-channel transistor connected between said output terminal and said second power source terminal; a common bulk P-channel transistors group of a first to fifth transistors formed on a common bulk region; a second N-channel transistor formed between said one node and said second power source terminal and comprising a gate electrode supplied an inverted signal of an enabling signal; and a logic circuit either inputting an inverted signal of said input signal to said gate electrodes of said first P-channel transistor and said first N-channel transistor, or inputting a signal keeping said first P-channel transistor turned off to the gate electrode of said first P-channel according to state of said enabling signal.

Abstract: A method and apparatus are provided for tri-state dynamic body charge modulation for sensing devices in silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) applications. A sense amplifier includes a silicon-on-insulator (SOI) field effect transistor. A tri-state body charge modulation circuit is coupled to a body of the silicon-on-insulator (SOI) field effect transistor. The body charge modulation circuit provides a high body bias preparatory state; a floating body state and a low body bias stand-by state enabling high performance operation, good matching characteristics, and low stand-by leakage suitable for low-power applications. The tri-state body charge modulation circuit includes a P-channel field effect transistor (PFET) and an N-channel field effect transistor (NFET) connected between a high voltage potential and ground.

Abstract: A control circuit of a control part sets the gate potential of a p-channel MOSFET of a driver part to a level lowering from a supply potential by at least the threshold voltage of the p-channel MOSFET while setting the gate potential of an n-channel MOSFET to a level rising from a low level of an input signal by at least the threshold voltage of the n-channel MOSFET in response to the input signal, thereby strongly turning on one of the p-channel MOSFET and the n-channel MOSFET and weakly turning on the other MOSFET.

Abstract: A technique is provided for improving the output drive capacity of output drivers on an integrated circuit that is configured to support I/O standards having operating voltages greater than the intrinsic core supply voltage. When MOS field-effect transistors are used in the I/O circuitry of such integrated circuits, the gate oxide layers of the transistors in the interface circuitry may need to be thicker than those comprising the core circuitry in order to tolerate I/O voltages that exceed the core supply voltage. In counteracting the degradation in output drive that may result from thickening the gate oxide layer, the pull-down signal applied to the gate of the pull-down transistor is preferably level-shifted from the core supply voltage to the higher external operating voltage associated with the I/O standard being supported. This external voltage is made available to the level-shifting circuit preferably through a spare pin or a gated I/O pin.

Abstract: CMOS voltage interface circuits have low power consumption, and minimal delays and power dissipation for the driving strength of the output. The circuits use a interface block which is operative upon the applied input signal, depending upon its state and timing, to generate the output at a specified voltage level which may be different from the level of the applied input.

Abstract: An input buffer receiver is described that will latch on a particular transition to insure a single transition does not have multiple transitions due to disturbances. This is accomplished with a Schmitt Trigger and a feedback latch controlled by an enabling signal. In one application, this is a chip select. A chip addressing input to a Schmitt Trigger type tri-state buffer is applied in parallel to two gates of the plurality of stacked CMOS transistors. A chip selection (CSB) signal is applied to a first gate of the Schmitt Trigger type tri-state buffer and in parallel to a second gate through an inverter. The output of the tri-state buffer is then fed to a latch circuit comprised of a plurality of stacked CMOS transistors. The latch output is the signal that goes to the circuitry that selects the desired chip address. The latch output is fed back into the appropriate gates of the latch to effect the desired latch-up when the Schmitt Trigger is put into the high output impedance state.

Abstract: A buffer circuit and method provide substantially constant output signal edges to facilitate service as a bus driver with enhanced timing flexibility. The buffer circuit includes a NOR gate and a NAND gate for driving output pulldown and pullup transistors. The initiation of current flows through the NOR and NAND gates is controlled by an environmentally adaptive reference circuit. First and second transistors are provided respectively between the NAND gate and the pullup transistor, and between the NOR gate and the pulldown transistor, to produce enhanced sourcing and sinking currents. The enhanced sinking and sourcing currents are timely terminated by switching of the pulldown and pullup transistors to save energy.

Abstract: A pulsed clock tri-state controller uses pulsed clock logic to control a tri-state bus driver. A clock shaper generates a pulsed clock bar signal. The pulsed clock tri-state controller utilizes the pulsed clock bar signal to sample a data input signal and an enable input signal into latches to generate a data signal and an enable signal for a tri-state bus driver. Receivers on the tri-state bus, such as latches or registers, are clocked using a locally generated pulsed clock bar signal from a local clock shaper. The pulsed clock tri-state controller, tri-state bus drivers, and the pulsed receivers provide an efficient method for transferring data over a tri-state bus.

Abstract: An integrated circuit device capable of effectively shutting off the power supply in a powerdown mode. The integrated circuit device is connected to a first (ground) power supply, a second power supply that continuously provides power, and a third power supply that halts power supply during the powerdown mode. It includes a controller and a CMOS tri-state driver consisting of a series connection of a P-channel MOS transistor and an N-channel MOS transistor. The P-channel MOS transistor has its source connected to the third power supply, its backgates connected to the second power supply and its gate connected to the controller. The N-channel MOS transistor has its source and backgate connected to the first power supply, its drain connected to the drain of the P-channel MOS transistor and its gate connected to the controller.

Abstract: A circuit comprising a first and a second circuit. The first circuit may be configured to generate a first control signal and a second control signal in response to (i) a first input signal and (ii) an enable signal. The first control signal generally matches the second control signal. The second circuit may be configured to generate a third control signal and a fourth control signal in response to (i) a second input signal and (ii) the enable signal. The third control signal generally matches the fourth control signal.

Abstract: An address buffer for a memory device comprises a tri-state input stage, an address output latch, and an inverter that are successively coupled. In one embodiment, the address buffer uses address enable signals for controlling both the tri-state input stage and the address output latch. In another embodiment, the tri-state input stage includes series coupled pairs of N and P channel transistors. The address signal is provided to gates of one P channel and one N channel transistor which form an inverter. The other two transistors have their gates coupled to the address enable signal and its complement for enabling the tri-state input stage. In another embodiment, the address output latch includes a multiplexed feedback loop that is controlled by the address enable signal and its complement. A method of operating the buffer comprises sampling a signal. The sampled signal is inverted. The inverted sampled signal is latched. Finally, the latched signal is inverted.

Abstract: A bidirectional full swing voltage repeater implemented on a signal line of an integrated circuit, which includes a first enable node for providing a first enable signal and a second enable node for providing a second enable signal. There is included a first full-swing unidirectional repeater circuit coupled between a first portion of the signal line and a second portion of the signal line. The first full-swing unidirectional repeater is configured to pass a first full swing signal from the first portion of the signal line to the second portion of the signal line when the first enable signal is enabled. The second full-swing unidirectional repeater circuit is coupled between the first portion of the signal line and the second portion of the signal line.

Abstract: In a semiconductor integrated circuit, an input-output circuit includes a flip-flop circuit (a front stage of an output circuit) between an input circuit unit and a tri-state output circuit unit (a final stage of an output circuit). This input-output circuit converts the level of the signal supplied from an internal circuit, which is operated by a first power source system, which provides a first supply potential and a grounding potential, of an LSI. After elapse of a certain time delay, the input-output circuit outputs a level converted signal to a device, which is operated by a second power source system, providing a second supply potential and a grounding potential, outside of the LSI.

Abstract: Various exemplary aspects of the present invention provide methods and apparatus for powering down the line driver to a state that reduces power dissipation without affecting the overall impedance of the line driver. More particularly, a power down state for line drivers and the like is suitably provided that saves power when no transmission is required. The power down mode suitably provides line termination for received data. According to various aspects of an exemplary embodiment, output devices are configured at power down such that a low impedance is maintained.

Abstract: A low-consumption TTL-CMOS input buffer stage includes a chain of inverters cascade connected between an input receiving electric signals at a TTL logic level and an output reproducing electric signals at a CMOS logic level, and powered between a first or supply voltage reference and a second or ground reference. Advantageously, the first inverter in the chain includes a means of selecting the delivery path to the stage according to an activate signal for a low-consumption operation mode. In essence, the first inverter of the buffer has two signal paths: one for normal operation and the other for low consumption operation.

Abstract: A method in an integrated circuit for implementing a reduced voltage repeater circuit on a signal line having thereon reduced voltage signals. The reduced voltage signals has a voltage level that is below VDD. The reduced voltage repeater circuit is configured to be coupled to the signal line and having an input node coupled to a first portion of the signal line for receiving a first reduced voltage signal and an output node coupled to a second portion of the signal line for outputting a second reduced voltage signal. The method includes coupling the input node to the first portion of the signal line. The input node is coupled to an input stage of the reduced voltage repeater circuit. The input stage is configured to receive the first reduced voltage signal on the signal line. The input stage is also coupled to a level shifter stage that is arranged to output a set of level shifter stage control signals responsive to the first reduced voltage signal.

Abstract: An integrated circuit device capable of effectively shutting off the power supply in a powerdown mode. The integrated circuit device is connected to a first (ground) power supply, a second power supply that continuously provides power, and a third power supply that halts power supply during the powerdown mode. It includes a controller and a CMOS tri-state driver consisting of a series connection of a P-channel MOS transistor and an N-channel MOS transistor. The P-channel MOS transistor has its source connected to the third power supply, its backgates connected to the second power supply and its gate connected to the controller. The N-channel MOS transistor has its source and backgate connected to the first power supply, its drain connected to the drain of the P-channel MOS transistor and its gate connected to the controller.

Abstract: A Muller C-element comprises two stages. The first stage consists of a NAND and a NOR gate, each driven by all of the inputs to the Muller C-element. In the second stage, the outputs of the two gates are used separately to switch on and off two output transistors, which drive the output of the Muller C-element A keeper flip flop serves to retain the output value between changes. Because current from each gate is applied only to one output transistor, delay is reduced. Furthermore, an unneeded output transistor is switched off as soon as logically possible, often during the otherwise unused interval while the input values differ, which reduces both delay and crossover current. In a preferred embodiment, the NAND and NOR gates each comprise a set of series transistors and a set of parallel transistors.

Abstract: A system and method that compensates for a pull-up resistor coupled to a buffer, when the pull-up resistor has an unknown resistance value. The system includes a buffer and a parameter detector. The buffer receives an input signal at a buffer input, and the buffer generates a buffered signal at a buffer output. The parameter detector measures a parameter at the buffer output when the buffer is in a high impedance output state, and the parameter detector generates a buffer control signal based upon the measured parameter. The buffer responds to the buffer control signal generated by the parameter detector.

Abstract: Integrated circuit output buffers include pull-down an pull-up circuits and a control circuit that utilizes a preferred feedback circuit to facilitate a reduction in simultaneous-switching noise during pull-down and pull-up operations and also improve the impedance matching characteristics of the output buffers during DC conditions. The preferred feedback circuit also limits the degree to which external noise can influence operation of the control circuit. Each of the pull-down and pull-up circuits may comprise a respective pair of primary and secondary transistors. The pull-down circuit is preferably configured so that the primary and secondary pull-down transistors (e.g., NMOS transistors) are electrically coupled to an output signal line (through an ESD protection resistor) and a first reference signal line (e.g., Vss).

Abstract: A programmable logic device architecture including tristate structures. The programmable logic device architecture provides tristate structures which may be logically or programmably controlled, or both. Through these tristate structures, the logic elements may be coupled to the programmable interconnect, where they may be coupled with other logic elements of the programmable logic device. Using these tristate structures, the signal pathways of the architecture may be dynamically reconfigured.

Abstract: An apparatus and method of communicating signals between a 2.5 volt internal circuit and both 3.3 and 5 volt external circuits using a P-well. The apparatus includes a circuit having a P-well control circuit and a number of NMOS transistors. The P-well control circuit is configured to receive a P-well control signal and an external signal, and in accordance therewith selectively generate a P-well voltage. The NMOS transistors are coupled to the P-well control circuit. At least one of the NMOS transistors has a bulk region configured to receive the P-well voltage. The NMOS transistors are further configured to receive a 5 volt signal and in accordance therewith selectively generate a 2.5 volt signal. The NMOS transistors are still further configured to receive a 3.3 volt signal and in accordance therewith selectively generate a 2.5 volt signal.

Abstract: An output buffer (500) is disclosed that includes an output driver circuit (508) having a first drive transistor (P504) for driving an output node (520) to a first logic level according the potential at a first pre-drive node (516), and a second drive transistor (N504) for driving the output node (520) to a second logic level according the potential at a second pre-drive node (518). The potential at the first pre-drive node (516) is established by a first standard pre-drive circuit (504) and a first phased pre-drive circuit (512). The potential at the second pre-drive node (518) is established by a second standard pre-drive circuit (506) and a second phased pre-drive circuit (514). In a low voltage mode of operation, where the rate of current drawn (di/dt) by the output driver circuit (508) is reduced, the standard and phased pre-drive circuits (504, 506, 512, 514) function together to drive their respective pre-drive nodes.

Abstract: A logical circuit device has a MOS transistor having a source region, a drain region, a channel region defined between the source region and the drain region, and a gate electrode formed above the channel region, respectively formed on a semiconductor substrate. The amplitude of a voltage applied to the gate electrode necessary for making the channel region conductive is not level throughout the channel region in the width direction. Using such a logical circuit device, flip-flop circuits and storage circuits of a multivalued logic type can be realized.

Abstract: A buffer circuit including a pair of complementary P-channel transistor and N-channel transistor connected in series, the connecting point of which is connected to an output terminal. The gate terminal of the P-channel transistor is connected to a power supply when the input signal is a low level, and to the output terminal when the input signal is a high level. The gate terminal of the N-channel transistor is connected to the output terminal when the input signal is the low level, and to a ground when the input signal is the high level. This makes it possible to solve a problem of a conventional buffer circuit in that an increasing capacity of a load connected to an output terminal increases a delay time between a time the input signal changes to the high level and a time the output signal changes to the high level.

Abstract: The invention typically relates to a semiconductor device comprising a driving portion composed of an output transistor NMOS 130 or PMOS 129 for driving an output terminal, and a control portion for controlling the operation state of the driving portion. The control portion outputs an enable signal for turning on or off the output transistor NMOS 130 or PMOS 129. The enable signal is produced by a pulse-shaped read instruction signal IN1 for increasing the time involved in the change from on to off of the output transistor NMOS 130 or PMOS 129.

Abstract: A CMOS driver circuit for high-speed data transmission has a complementary differential switch formed by four transistors, a bias cell containing current mirrors controlled by a reference current, two drive-current limiting devices for limiting the drive current to a required value via the bias cell, a current-shunting switch, and buffers which drive each of the gate nodes of the switches. CMOS transistors used in these buffers are limited in size to limit the rate at which they operate the switches and to limit the rate at which current is steered from one side of the differential switch to the other. One supply side of each of these buffers is connected to one of the current-limited supply nodes of the main output switches, thus greatly reducing variations in switching rate. The CMOS devices have sizes optimized to achieve both the required switching speed and minimized sensitivity to variations affecting switching speed.

Abstract: There is disclosed a tri-state buffer circuit for receiving an input signal at a buffer input node and transmitting, responsive to a buffer enable signal, an output signal at a buffer output node. The buffer circuit includes an input stage coupled to the buffer input node. The input stage is configured to receive, when the buffer enable signal is enabled, the input signal. The buffer circuit further includes a level shifter stage coupled to the input stage. The level shifter stage is arranged to output, when the buffer enable signal is enabled, a set of level shifter stage control signals responsive to the input signal. A voltage range of the set of level shifter stage control signals is higher than a voltage range associated with the input signal. The buffer circuit also includes an output stage coupled to the level shifter stage.

Abstract: A driver to drive a bus with a pullup and a pulldown transistor according to a data signal during a drive phase and to charge or discharge the bus to intermediate voltage levels during a precondition phase using the pullup and pulldown transistors, the driver comprising a buffer and latch to latch the bus voltage at the end of a drive phase; a precondition circuit responsive to the latch to switch ON a pullup transistor at the beginning of a precondition phase when the bus voltage was LOW in the previous drive phase so as to charge the bus voltage to a first voltage less than a supply voltage, and to switch ON a pulldown transistor at the beginning of the precondition phase when the bus voltage was HIGH in the previous drive phase so as to discharge the bus voltage to a second voltage above ground.

Abstract: A digital CMOS predriver circuit pulls an output node up and down with accurately controlled rise and fall times in the threshold region. Resistors independently set rise and fall slew rates while additional CMOS devices initially charge and discharge the output node. The additional devices turn off before the output reaches the threshold region.

Abstract: Reduction of standby leakage current in an internal circuit block using a transistor stack effect. For one embodiment, an apparatus includes a standby leakage reduction circuit to be coupled to the circuit block including a plurality of logic gates. The standby leakage reduction circuit causes a stack effect at each of the plurality of logic gates during a standby mode of the circuit block by turning off two or more series-coupled transistors of a same type (either n-type or p-type) at each of the plurality of logic gates.

Abstract: OCD circuitry is provided for an integrated circuit having a split rail power supply providing a first and a second voltage. The OCD circuitry comprises a tristate logic circuit adapted to control the OCD and a detection circuit coupled to the tristate logic circuit and adapted to generate an inactivation signal that inactivates the OCD if the first voltage is low. The detection circuit preferably comprises a comparator that compares the first voltage to the second voltage, and that generates the inactivation signal if the first voltage is less than the second voltage. To prevent the inadvertent inactivation of the OCD circuitry, the detection circuit preferably is provided with a filter that sets a minimum time period that the first voltage must be low before the detection circuit generates the inactivation signal and thus inactivates the OCD circuitry.

Abstract: A digital circuit pulls up an output node using an NFET device. The digital circuit is part of a CMOS predriver having balanced delays for coming out of tristate mode and for data mode operation. The predriver has size and speed capability advantages and is particularly advantageous when followed by a CMOS driver powered by a lower positive voltage supply.

Abstract: An address buffer for a memory device comprises a tri-state input stage, an address output latch, and an inverter that are successively coupled. In one embodiment, the address buffer uses address enable signals for controlling both the tri-state input stage and the address output latch. In another embodiment, the tri-state input stage includes series coupled pairs of N and P channel transistors. The address signal is provided to gates of one P channel and one N channel transistor which form an inverter. The other two transistors have their gates coupled to the address enable signal and its complement for enabling the tri-state input stage. In another embodiment, the address output latch includes a multiplexed feedback loop that is controlled by the address enable signal and its complement. A method of operating the buffer comprises sampling a signal. The sampled signal is inverted. The inverted sampled signal is latched. Finally, the latched signal is inverted.

Abstract: A crow-bar current reduction circuit for use with a NMOS output circuit a gate voltage control circuit (GVC). The GVC receives a data signal and an output enable signal and generates control signals to drive the gates of the output transistors of the output circuit. When enabled, the GVC delays the rising edges of the gate control signals so as to help ensure that during a transition of the output signal generated by the output circuit, the NFET that was conductive before the transition is "turned off" to become non-conductive before the NFET that was non-conductive before the transition is "turned on" to become conductive. When adapted for a CMOS output circuit, the GVC delays the rising edge of the gate control signal provided to the NMOS pull-down transistor and delays the falling edge of gate control signal provided to the PMOS pull-up transistor.