Abstract: An embodiment level converter circuit is configured to receive, as a current supply, a current proportional to temperature.

Abstract: In various embodiments, a circuit is provided including a supply terminal, a logic circuit, an inverter and a control transistor which may include a body region, first and second source/drain regions, a gate insulating region having a layer thickness and a gate region. The first source/drain region may be coupled to the supply terminal. The logic circuit may have an internal supply terminal connected to the second source/drain region of the control transistor and a plurality of transistors each having a gate insulating region having a second layer thickness. The inverter input may be coupled to the internal supply terminal of the logic circuit and the output to the gate region of the control transistor. The inverter may include a transistor with a gate insulating region having a third layer thickness substantially equal to the first and second layer thicknesses.

Abstract: A semiconductor apparatus may include a mode control circuit configured to output differential output signals which swing in a current mode logic (CML) area and a first control signal, in response to a power-down mode signal; a first circuit unit configured to be provided with the differential output signals, and operate in a power-down mode; and a second circuit unit configured to be provided with the differential output signals, and be interrupted in its operation in the power-down mode.

Abstract: A battery assisted level shifter comprises a pull up transistor pulling up an output when a received input signal is high, a pull down transistor pulling down the output when the received input signal is low, and a battery element to provide voltage offsets. The battery element can be implemented using one or more pull-up transistors for assisting with pulling up the output. The level shifter can be used in class-D amplifiers, DC-DC power converters and interfaces between circuits having different reference voltages.

Abstract: A bus switch chip is limited to operating with a power-supply voltage of 1.8 volts relative to a 0-volt ground. Differential bus signals switched through the bus switch chip swing from 2.7 to 3.3 volts, well above the chip's specified power-supply voltage. The bus switch chip is level-shifted by applying a 1.5-volt signal as the chip's ground, and a 3.3-volt signal as its power supply, so the chip's net power supply is within the specification at 1.8 volts. High-Definition Multimedia Interface (HDMI) and Digital Visual Interface (DVI) require that the differential signals are never driven to ground. However, some non-compliant video transmitters drive differential signals to ground when disabled. External pullup resistors or internal pullup transistors in the bus switch chip are added to the bus signals from non-compliant transmitters to pull disabled signals above the 1.5-volt chip ground to prevent damage from signals below the chip's 1.5-volt ground.

Abstract: The CML (current mode logic) to CMOS converter with a leakage balancing transistor for jitter reduction includes: a differential input stage; an output stage having a first branch coupled to a first output of the differential input stage and a second branch coupled to a second output of the differential input stage; and a leakage balancing transistor coupled to the first branch of the output stage.

Abstract: The present invention provides an apparatus for connecting semiconductor modules, in particular memory banks, having: at least two devices (A, B) for receiving a respective semiconductor module (1, 2); a contact device (13a, 13b, 13c, 13d, 13e, 13f) having a first group of contacts (13a, 13b, 13c, 13d) and a second group of contacts (13e, 13f), the two groups being able to be connected to one another by means of a variable connection module (3, 4); a group of lines (10, 11, 20, 21) for connecting the receiving devices (A, B) to the first group of contacts (13a, 13b, 13c, 13d), a subgroup (13b, 13c) of the first group of contacts being assigned to the lines (10, 11) of the first receiving device (A); the connection module (3, 4) connecting either a subgroup of the contacts (13b, 13c) to the second group of contacts (13e, 13f), or the first group of contacts (13a, 13b, 13c, 13d) to the second group of contacts (13e, 13f).

Abstract: To provide an input circuit of an IC wherein the current flowing towards the input terminal when receiving a LOW level signal can be restricted to minimum, and the input threshold level can be controlled appropriately without degrading transition performance of the input circuit, an input circuit includes: a current control means for controlling a first current to be supplied to a first node according to a second current to be supplied to a second node an input level transfer means for transferring logic of the external logical signal into an intermediate signal whereof potential of a HIGH level is restricted within a power supply voltage; a level shift means for shifting a LOW level of the intermediate signal to substantially the same level of a LOW level of the external logical signal; an inverter for outputting a signal of low output impedance by inverting the shifted intermediate signal; and a transition current generating means for controlling the level shift means to supply a sufficient transition curre

Abstract: Integrated buffer circuits which are less susceptible to noise and provide TTL-to-CMOS signal conversion capability include a first TTL-compatible inversion buffer, a second CMOS-compatible inversion buffer having an input electrically coupled to an output of the first inversion buffer and a preferred pull-up (or pull-down) circuit to improve noise immunity. The preferred circuit pulls the output of the first inversion buffer to a potential of the first reference signal line (e.g., Vdd) in response to a signal at an output of the second inversion buffer and a signal at an input of the first inversion buffer. This circuit comprises a first field effect transistor having a gate electrode electrically coupled to the output of the second inversion buffer and a second field effect transistor having a gate electrode electrically coupled to the input of the first inversion buffer.

Abstract: A semiconductor device is arranged by a push-pull circuit 1 for shifting a first center potential of an amplitude of an input signal to a second center potential, and for outputting first and seconc complimentary signals P1, P2 having said second center potential, and further a bipolar type differential amplifier 2 for receiving the first and second complementary signals as input signals thereof.

Abstract: A logic output stage that may be part of a circuit that provides the circuit user with the ability to select the type of digital electronic format for the digital signals output from the circuit. The logic output stage may include separate sections for processing signals so that they will have one of a plurality of digital electronic formats. Moreover, in cases where two or more digital electronic formats are very close, a single section may be used to process digital signals to have these formats.

Abstract: The present invention includes an input buffer circuit (10) having sleep mode and bus hold capability. An input section (11) of the buffer circuit is operated from an operating voltage which is lower than a supply voltage of the buffer circuit thereby minimizing the static power dissipation. Sleep mode circuitry (15, 36, 38) is included for effectively disconnecting an input signal from the rest of the buffer circuit thereby minimizing dynamic power dissipation. Bus hold circuitry (40) is included for holding the logic state appearing at an output of the input buffer circuit when the input signal is removed thereby further reducing the static power dissipation.

Abstract: A buffer utilizing the pseudo-ground hysteresis of the present invention contains first and second stage switching elements and a resistive element. The pseudo-ground hysteresis is implemented via a ground path from the switching elements. The first stage switching element is configured to have a first DC voltage trip point, and the second stage switching element is configured to have a second DC voltage trip point. As an input voltage, transitioning from a first state to a second state, is applied to the first stage switching element, a first current (I.sub.1), from the first stage switching element, and a second current (I.sub.2), from the second stage switching element, is generated. When the input voltage equals the first stage DC voltage trip point, the first and second stage switching elements transition. During the transition of the input voltage from the second state to the first state, the total current flowing through resistive element is reduced, and the voltage at the resistive element decreases.

Abstract: A programmable logic device (PLD) with an output macrocell circuit is disclosed. Specifically, there is a macrocell having an exclusive logic signal feedback line and an exclusive external input signal line both feeding into the input of the PLD. Exactly, this PLD can disable the I/O pad and still have an internal feedback to its logic circuitry.