Abstract: A CMOS differential to single-ended converter is implemented. A differential input stage comprised of a pair of N-channel transistors draws current through two fixed current P-channel load transistors. A first N-channel differential transistor provides negative feedback bias control of a current source transistor coupled to the differential input stage. The negative feedback control provides increased current gain in the second N-channel transistor, which drives a CMOS inverter to a full rail-to-rail voltage swing on its output.

Abstract: A rectifying transfer gate circuit includes first and second field effect transistors and one diode. The source of the first field effect transistor is coupled to a first input node and the gate thereof is coupled to a second input node. Meanwhile, the source of the second field effect transistor is coupled to the second input node and the gate thereof is coupled to the first input node. The diode is coupled between the common drain of the first and second field effect transistors and an output node, so as to increase the speed of the operation in the application circuit utilizing the above rectifying transfer gate circuit.

Abstract: The differential output signals from the sense amplifiers of a dynamic random access memory unit are applied to apparatus which converts these output signals to a non-differential current mode signal. The non-differential current mode signal is applied to a data line. The output signal from the data line is converted to a small swing voltage signal. The small swing voltage signal is compared with a reference voltage level thereby generating a full swing voltage output signal. The reference voltage level is generated by a sample and hold circuit which samples the small swing voltage level when the differential signals from the sensors are equal. The sampled level is stored for comparison with the small swing voltage level resulting from the sensing of the stored voltage level. The full swing voltage output signal is suitable for use with CMOS circuits associated with the dynamic random access memory unit.

Abstract: An input stage of a level converter for converting an ECL compatible signal to an MOS compatible signal is formed as a differential amplifier. The differential amplifier produces a current that is coupled directly to a first transistor of a pair of complementary transistors, during a transition interval, to turn on the first transistor. An output signal of the first transistor is fed back to a control terminal of the first transistor via a first inverter. Consequently, the first transistor is actively turned off immediately following the transition interval. A second inverter and the first inverter form a latch for maintaining the output signal unchanged, after the first transistor is turned off.

Abstract: The present invention provides BICMOS level shifter having pull-up and/or pull-down transistors at pull-up and/or pull-down portions, which perform a switching operation in response to a reference signal of a stable voltage level, and a BICMOS data output buffer employing the BICMOS level shifters as respective pull-up and pull-down control circuits. Thereby, it is possible to attain low power consumption, high drive capability and high speed operation by bipolar transistors and is also possible to cope with unstable signals.

Abstract: The logic of an intermediate signal (Y.sub.1) goes high when an input signal (CI) makes an "L" to "H" transition, and then a transistor (Q.sub.1) turns on and a transistor (Q.sub.2) turns off. The input signal (CI) at a potential corresponding to the logic "H" at a CMOS level has been applied to the gate of an NMOS transisitor (N.sub.1), and the NMOS transistor (N.sub.1) turns on rapidly. At this time, only current flowing through the base of an output transistor (Q.sub.0) flows through parallel connection of a resistor (R.sub.2) and an on-resistance of the NMOS transistor (N.sub.1). Since the NMOS transistor (N.sub.1) is on, the base potential of the output transistor (Q.sub.0) is raised if the resistor (R.sub.2) has a high resistance, and current fed from the output transistor (Q.sub.0) increases, thereby raising the emitter potential of the output transistor (Q.sub.0). Then the logic of an output signal (EO) goes high. Power consumption of an output buffer circuit is reduced.

Abstract: In a semiconductor device where a CMOS circuit and a bipolar circuit are mixed, the bipolar circuit is operated between a first power supply voltage and a second power supply voltage, and the CMOS circuit and a level conversion circuit between a CMOS level and a bipolar level are operated between the first power supply voltage and a third power supply voltage. The third power supply voltage is between the first and second power supply voltages.

Abstract: A logic output stage that may be part of a circuit that provides the circuit user with the ability to select the type of digital electronic format for the digital signals output from the circuit. The logic output stage may include separate sections for processing signals so that they will have one of a plurality of digital electronic formats. Moreover, in cases where two or more digital electronic formats are very close, a single section may be used to process digital signals to have these formats.

Abstract: A signal level converter is disclosed, for converting a signal having a first logic voltage swing characteristic to a signal having a second voltage swing characteristic. The converter comprises a level converting section and a differential circuit coupled thereto. The level converting section converts the supplied signal at the first logic voltage swing to an intermediate signal at a logic voltage swing different from the first voltage swing. The differential circuit 3, being supplied with the intermediate signal, produces an output signal at the second voltage swing level that corresponds to the potential difference between a high and low potential power supplies.

Abstract: A translator for translating signals from a CML or ECL circuit to signals that are compatible with CMOS or TTL voltage levels is disclosed. The translator has minimum power consumption and provides switching and drive characteristics that are independent of the threshold voltage, power supply voltage, temperature and process variations. The translator includes the following components: a bias reference generator for receiving a first bias voltage and generating a second bias voltage; an input circuit for receiving the input signals; a cascode circuit for receiving the second bias voltage, having a controlled current and outputting the output signals; and a current-mirror circuit. The first bias voltage is at the mid-point of the logic swing of the input signals, and the bias reference generator provides the second bias voltage to generate the controlled current in the switching stage of the translator.

Abstract: An efficient high-speed ECL to CMOS logic converter for BiCMOS integrated circuits. In one embodiment, a differential amplifier compares an ECL input signal to an ECL reference voltage and generates a pair of complementary intermediate signals on a corresponding pair of differential output nodes. The differential amplifier has two load resistors coupled in series with a common load resistor which limits the upper voltage swing at the differential output nodes. A regenerative stage coupled to the differential output nodes switches between a partially on state and a fully on state in response to the complementary intermediate signals. A pair of inverter stages convert the complementary intermediate signals into a pair of CMOS level signals. A pair of complementary output drivers coupled to the respective complementary inverter stages provide current driving capability.

Abstract: A level shifter and a data output buffer adapted for use in a semiconductor memory device including a memory cell for storing data, a sense amplifier for amplifying data read from the memory cell and generating an ECL-level output signal, and a level shifter for converting the ECL-level output signals into a CMOS-level signal, wherein the level shifter has a level shifting means receiving the ECL-level data signals, converting the input data to CMOS-levels, and outputting a result, and a delay for delaying the result so as to control its current consumption of the level shifter.

Abstract: A level conversion circuit for converting a first signal having a first amplitude into a second signal having a second amplitude that is larger than the first amplitude, includes a bipolar transistor supplied at a base thereof with the first signal, a first MOS transistor of a first channel type having a gate supplied with a bias voltage and a source-drain path connected between the emitter of the bipolar transistor and an output node from which the second signal is derived, and a second MOS transistor of a second channel type having a gate supplied with an inverted signal of the first signal and a source-drain path connected between the output node and a reference potential line. A PN junction diode is preferably inserted between the third transistor and the reference potential line.

Abstract: A translator circuit for converting from a first logic-level range to a second logic-level range, as is generally involved in the translation from an ECL stage to a CMOS stage. The translator includes a reference stage that provides a reference voltage that is coupled to the CMOS logic stage as well as the ECL logic stage. The ECL logic stage is indirectly coupled between a high potential power rail and a low potential power rail through a plurality of transistors. The CMOS stage is coupled to the ECL stage through two emitter-follower transistors. The CMOS stage uses current-mirroring techniques in combination with the isolated reference stage to effect a translation from the ECL logic level to the CMOS logic level. The CMOS stage also provides relatively fast propagation time which may be set, within certain limits, to a desired time.

Abstract: A semiconductor integrated circuit device is provided for permitting operation of a CMOS or BiCMOS memory with ECL level input signals, in which operating speed is increased and power consumption is reduced.Input signals of ECL levels are received by an input buffer for amplifying the input signals to an output signal level within a range where differential transistors of the input buffer operate in an unsaturation region. The output signal of the input buffer is supplied to a CMOS circuit or Bi-CMOS circuit which is operated by both an operating voltage having a first-stage smaller absolute value than that of the operating voltage of the input buffer and the ground potential of the circuit. This first stage CMOS or BiCMOS circuit also includes an arrangement to further amplify the received signals to provide further level conversion.

Abstract: An ECL to CMOS signal converter circuit including built-in toggle-fault detection circuitry and method of conversion are provided in which an RF transformer is used to translate ECL level digital signals to CMOS level signals. A diode biasing circuit shifts the average DC level of the CMOS level signals in a positive direction to avoid signal undershoot. An AC peak detection circuit is connected to the inactive leg of the RF transformer to monitor toggling of the ECL level input signal lines. A DC comparator circuit compares the detected peak voltage with a predetermined threshold voltage, and generates an alarm signal representing a toggle-fault whenever the detected peak voltage is lower than the predetermined threshold.

Abstract: An ECL-to-BiCMOS/CMOS translator for translating a pair of differential ECL level signals into a BiCMOS/CMOS level signal is disclosed. The translator includes an output stage having an output node and a first output switching means for coupling the output node to a first voltage supply and a second output switching means for coupling the output node to a second voltage supply. A first input stage activates the first output switching means of the output stage in response to one of the differential ECL signals, and a second input stage activates the second output switching means of the output stage in response to the other differential ECL signal. The first input stage includes a first input switching means for coupling a first resistive element between the first voltage supply and the output node of the output stage, and the second input stage includes a second input switching means for coupling a second resistive element between the first voltage supply and the second voltage supply.

Abstract: A latching ECL to CMOS input buffer (20) has an input buffer (21) for receiving an ECL input signal, a CMOS latch (35), and driver circuits (55, 65). Transmission gates (31, 32) are used to couple the input buffer (21) to the latch (35) in response to a CMOS clock signal being a logic low. The driver circuits (55, 65) are coupled to transmission gates (31, 32). While the clock signal is a logic low, input nodes of the first and second driver circuits (55, 65) are precharged to a relatively high voltage in order to isolate the input signal from the first and second driver circuits (55, 65). The latch (35) both latches the logic state of the ECL input signal and converts the ECL input signal to CMOS logic levels. This allows an input signal to be latched and level converted within a relatively short period of time.

Abstract: A level shifting circuit which can be implemented as part of a bipolar ECL integrated circuit, provides reliable switching and level shifted output suitable for driving a low voltage CMOS integrated circuit. The circuit includes a level shifting circuit which is connected to trigger a high gain positive feedback bootstrap circuit to reliably ensure switching even under poor signal conditions. An output taken from one of the switched pair is allowed to go to V.sub.CC, 0 volts, or is clamped by a clamping circuit to -3.3 volts, representing the two output states suitable for driving inverted rail CMOS circuitry.

Abstract: A current steering switch circuit responsive to a CMOS signal. In an specific embodiment the switch is incorporated in a hybrid BiCMOS multiplexer circuit using combined CMOS and CML/ECL signal types. The high speed CML/ECL logic signals are multiplexed under the control of a lower speed CMOS signal. A particular aspect of the circuit is that a CMOS to CML/ECL converter is not used. Additionally, a differential, logic commutation signal is not required.

Abstract: In a synchronous semiconductor device, a plurality of input signals having a small amplitude such as an ECL level are converted into a plurality of input signals having a large amplitude such as a CMOS logic level. The large amplitude input signals are held by a plurality of latch circuits and are then supplied to an internal circuit such as a CMOS memory circuit. An ECL level clock signal is converted into CMOS logic level clock signals at a plurality of clock signal conversion circuits. Each of the latch circuits is clocked by the CMOS logic level clock signal generated from one of the clock signal conversion circuits closest thereto.

Abstract: A semiconductor integrated circuit device such as a memory device with logic function comprises a plurality of RAM macrocells and gate arrays. The RAM macrocells are constituted by bipolar CMOS RAMs having a total memory capacity of at least 100 kilobits, and the gate arrays contain at least 4000 gates. The logic circuits in the memory device with logic function or the like are constructed by selectively combining CMOS, bipolar CMOS or ECL gate circuits depending on the output load capacity, transmission characteristic requirement, power dissipation and required layout area. The level of signals at various circuits is set to the ECL level or MOS level depending on the local circuit configuration and other factors. The memory device further incorporates sequence control circuits required to be installed downstream of buffer storages of computers.

Abstract: It is an object of the present invention to provide an amplifier circuit for amplifying the voltage amplitude of a small amplitude signal to the CMOS level which operates at a high speed with low power dissipation while assuring high gain. PMOS FETs M.sub.11, M.sub.16 for pulling up the output are of the source-driving type and receive signals V.sub.IN1, V.sub.IN1i, respectively, and NMOS FETs M.sub.12, M.sub.17 for pulling down the output are of the gate-driving type and receive level shifted signals V.sub.IN2, V.sub.IN2i, respectively. In the circuit of the present invention, constant voltages for reference are set by diodes D.sub.13, D.sub.14, and bipolar transistors are connected as transistors for driving an output portion of the amplifier circuit.

Abstract: In one aspect of the present invention, a converter is provided comprising a capacitive coupling arranged to receive said input signal to be converter, and a conversion circuitry coupled to the capacitive coupling to produce the converted output signal. A biasing circuit is further arranged to facilitate a fast transition in the converted output signal in response to an active transition in the input signal.

Abstract: The output terminal of an ECL circuit is directly connected to the input terminal of a CMOS output circuit. The CMOS output circuit has a transistor which sets the threshold voltage of the CMOS output circuit nearly midway between ECL logic levels. A first reference voltage generating circuit has substantially the same arrangement as the CMOS output circuit and outputs a potential midway between CMOS logic levels as a first reference voltage Vref1. The first reference voltage Vref1 is made variable. A second reference voltage generating circuit has substantially the same arrangement as the ECL circuit and outputs a potential which is midway between the ECL logic levels as a second reference voltage Vref2. A comparator makes a comparison between the first and second reference voltages Vref1 and Vref2 and controls the first reference voltage generating circuit and the CMOS output circuit so that the first and second reference voltages Vref1 and Vref2 may become equal to each other.