Abstract: In one embodiment, the present disclosure includes a level shift circuit. The level shift circuit includes a clocked latch to receive a digital data signal and a complement of the digital data signal. Outputs of the clocked latch are coupled to inputs of a second latch through capacitors. The clocked latch is powered by first and second power supply voltages that are different than third and fourth power supply voltages used for powering the second latch. Latch output signals from the second latch have high and low voltage values at the third and fourth power supply voltages. In one embodiment, transistors in circuitry driven by the level shift circuit may receive output signals from the level shift circuit that have high and low voltage values within a safe operating range of the transistor receiving the output signal.

Abstract: A signal output circuit is disclosed that supplies a signal from a first circuit that is driven based on a first reference voltage to a second circuit that is driven based on a second reference voltage. The signal output circuit includes a first control circuit that draws a current to the first reference voltage according to an output signal from the first circuit and supplies a signal to the second circuit according to the drawn current, and a second control circuit that draws a current from the second circuit to the second reference voltage.

Abstract: The CML (current mode logic) to CMOS converter with a leakage balancing transistor for jitter reduction includes: a differential input stage; an output stage having a first branch coupled to a first output of the differential input stage and a second branch coupled to a second output of the differential input stage; and a leakage balancing transistor coupled to the first branch of the output stage.

Abstract: An improved ECL circuit, based upon an ECL circuit of conventional design, functions as the required transceiver for the bi-directional data transmission between a computer and an electronic device with a specific interface of USB 2.0. The value of an emitter resistor within an emitter resistance network in the conventional ECL circuit is adjusted till its output voltage amplitude meets the USB 2.0 specification. A number of voltage level shifting and capacitive coupling circuits are added to both the input and output sections of the conventional ECL circuit making it directly interfaceable with the popular CMOS logic family. A collector electrode switch network is also added to the conventional ECL circuit to make its output terminals tri-statable thus compatible with the communication scheme of half duplexing under the USB 2.0 specification.

Abstract: An interface circuit from Common Mode Logic to a low voltage, fixed common mode output, with high current drive. The CML signal is received, and then re-referenced to a low-voltage band-gap supply. The circuit is arranged to provide an output data signal referenced to a second positive reference voltage supply responsive to receipt of a common mode input data signal referenced to a first positive reference voltage supply. The circuit avoids use of vertical PNP transistors in the signal path.

Abstract: A circuit (10) for providing TTL logic signals at an output (24) employs dual pull up devices (20, 30) at the output. The first device (20) is a bipolar transistor that acts as an emitter-follower to quickly pull up the output in response to applied logic signals to drive the output to a logic one state. Thereafter, the second device (30) which is a MOS transistor is turned on to drive the magnitude of the high logic output signal to substantially VCC, the positive power supply voltage supplied to the circuit (10).

Abstract: The present invention provides a level converting circuit comprising: a differential output transistor circuit for amplifying a difference between two mutually complementary input logic signals; a first output transistor circuit for outputting an inverted output logic signal based on a signal output by the differential output transistor circuit; and a second output transistor circuit for outputting an uninverted output logic signal based on a signal output by the differential output transistor circuit, wherein the first output transistor circuit further comprises first and second field-effect transistors and the second output transistor circuit further comprises third and fourth field-effect transistors. The differential output transistor circuit comprises a combination of first, second, third, fourth and fifth bais components which are each resistive element or a field-effect transistors.

Abstract: A semiconductor integrated circuit device has a first ground to which a first circuit is connected and whose level is fluctuate due to noise and a second ground to which a second circuit, which provides an output to the first circuit, is connected and whose level is stable. The semiconductor integrated circuit device includes a fluctuation detecting unit for detecting a fluctuation in the level of the first ground according to the level of the second ground serving as a reference; and a level controlling unit for controlling the level of the output of the second circuit, to cancel the fluctuation detected by the fluctuation detecting unit. The semiconductor integrated circuit device detects a fluctuation in the level of the first ground, which is easily affected by noise, according to the level of the second ground, which is stable, and controls the level of the output of the second circuit, to cancel the detected fluctuation.