Abstract: An output circuit for a TTL-CMOS integrated circuit that comprises an output stage with two P MOS and N MOS transistors in parallel, which are connected in cascade with an N MOS enabling transistor between the power supply and the reference voltages. The output stage connected by means of a validation signal TRISB and of P and N MOS transistors delivers an output signal representing the input logic variable to the common point between the P MOS transistor and enabling transistor. A first circuit allows switching of the P MOS transistor by an intermediate switching control signal TRISP and a third circuit allows switching of the N MOS transistor, the circuit operating in mode of feedback of the switching control of the P MOS transistor, the controls being applied successively in order to generate an intermediate switching level belonging to the high logic level.

Abstract: An input buffer circuit for converting a TTL(TTL:Transistor transistor logic) level signal supplied from an outside into an internal CMOS level signal. The input buffer circuit comprises a power voltage terminal supplied with a power voltage, a power voltage sensing signal generator for detecting a level of the power voltage by inputting as source power the power voltage supplied to the power voltage terminal and for outputting a power voltage sensing signal respondent to the detected level, and switching means for convening an external signal into an internal signal and for performing an switching operation in response to a level of the power voltage sensing signal positioned on an output path to output the convened signal.

Abstract: A clock distribution system for a data processing system is implemented in CMOS technology wherein a full-swing differential clock signal is converted to a low-voltage swing differential clock signal by a driver's circuit and then returned to a full-swing differential clock signal at each receiver circuit.

Abstract: An input buffer insensitive to changes in supply voltage, temperature and other operational parameters comprises a decoupling capacitor and receives a reference voltage. In one embodiment, the input buffer comprises a CMOS invertor in which a PMOS transistor is provided to decouple the output signal from a fluctuation of the ground voltage ("ground bounce"). In one embodiment, a band gap type voltage regulator provides the reference voltage of the input buffer.

Abstract: A translator for translating signals from a CML or ECL circuit to signals that are compatible with CMOS or TTL voltage levels is disclosed. The translator has minimum power consumption and provides switching and drive characteristics that are independent of the threshold voltage, power supply voltage, temperature and process variations. The translator includes the following components: a bias reference generator for receiving a first bias voltage and generating a second bias voltage; an input circuit for receiving the input signals; a cascode circuit for receiving the second bias voltage, having a controlled current and outputting the output signals; and a current-mirror circuit. The first bias voltage is at the mid-point of the logic swing of the input signals, and the bias reference generator provides the second bias voltage to generate the controlled current in the switching stage of the translator.

Abstract: An inverter receives an energizing voltage with a particular magnitude (e.g. 1.5 V) at a first terminal and produces the voltage at a second terminal. The received and produced voltages are differentially introduced to a stage which produces a single-ended bias voltage (e.g. 3 V) related to the second terminal voltage. The bias voltage is servoed to regulate the second terminal voltage (e.g. 1.5 V) and the bias voltage (e.g. 3 V) regardless of energizing voltage variations. In response to the bias voltage and a variable input voltage, a pass transistor in a buffer produces a first control voltage different from the bias voltage by the pass transistor threshold voltage for input voltages greater than a value equal to the bias voltage less the pass transistor threshold, and corresponding to the input voltage for input voltages less than the bias voltage less the pass transistor threshold.

Abstract: A voltage level shifting circuit which enables realization of high sensitivity input, high speed, and large output amplitude with a low power consumption, wherein a flipflop is constituted by two CMOS inverters, INV.sub.1 and INV.sub.2, the power voltage sides of the CMOS inverters are used as the inputs of the signals, transfer gates are connected between the input terminals of the input signals and the input terminals of the CMOS inverters, and the transfer gates are turned on and off by the same clock signal CLK.

Abstract: A low-power, logic signal level converter includes a CMOSFET current mirror differential amplifier with a current control element for providing a level-converted output logic signal in response to an input logic signal while ensuring that virtually no DC current is drawn during steady-state circuit operations. The CMOSFET current mirror differential amplifier includes a PMOSFET current mirror driven by NMOSFET pull-down transistors with a DC current-blocking PMOSFET between them. The interposed PMOSFET blocks DC current flow during steady-state circuit operation without adversely affecting the line driving capacity of the current mirror differential amplifier during logic signal transitions.

Abstract: A CMOS input circuit that has a first inverter stage for comparing non rail-to-rail digital input voltages to a threshold voltage, and producing inverted CMOS output voltages is disclosed. The inverted output voltages are approximately equal to a low CMOS supply voltage plus an offset voltage and a high CMOS supply voltage. The inverter includes PMOS and NMOS transistors that are connected to receive a common input voltage at their gates and to have a common drain current. The PMOS' source is connected to the high supply voltage, and the NMOS' source is connected through a voltage drop circuit element to the low supply voltage. The inverted output voltage is produced at the connection of the PMOS and NMOS transistors' drains. The NMOS and PMOS transistors have gate width and length parameters W.sub.N, L.sub.N and W.sub.P, L.sub.P, respectively. The ratio ##EQU1## is selected so that the threshold voltage is set between the maximum low and minimum high input signals for a desired range of high supply voltages.

Abstract: An input circuit designed for a semiconductor device. A first input buffer (14) receives a control signal EN, an input signal IN, and a reference signal VREF, for producing a first output signal OUT.sub.1 in response the control signal and a difference between the input signal and the reference signal. A second input buffer (16) receives the control signal and the input signal, for producing a second output signal OUT.sub.2 in response to the control signal and the input signal. A control circuit (22) produces the control signal, in response to a predetermined output state.

Abstract: A signal input circuit having a CMOS inverter for receiving an input signal of a TTL level is disclosed. This circuit includes a first transistor of one channel type connected between a first power terminal and an output terminal and having a gate connected to an input terminal, a second transistor of an opposite channel type connected between a second power terminal and the output terminal and having a gate connected to the input terminal, and a current gain control circuit coupled to the first transistor for controlling the current gain of the first transistor to a first value when a power voltage is at a first level and to a second value when the power voltage is at a second level.

Abstract: A pull-down circuit for a TTL compatible data output buffer uses NMOS devices. The pull-down circuit comprising two NMOS stages. Namely, a diode configuration stage where the gate and drain electrodes are shorted together during pull-down and a common-source stage. Both PMOS and NMOS devices are used for shorting the gate and drain electrodes.

Abstract: An input buffer for utilization in a programmable logic device (PLD). The input buffer includes an inverter consisting of a PMOS pull up transistor one half the size of a corresponding NMOS pull down transistor to enable TTL compatibility. To drive a high capacitance load, instead of utilizing further buffering which introduces gate delays, a cascode transistor is used to control an additional pull up output driver connected to the output of the inverter. The cascode functions to turn on the additional pull up output driver to supplement the PMOS pull up transistor during a low to high transition of the output. The input buffer further includes a switching transistor coupled between a V.sub.DD power supply and the PMOS pull up transistor to cut power to the PMOS pull up transistor when the inverter has a low output. With no utilization of power during a low output, the input buffer provides a zero power TTL input enabling the input buffer to be utilized on circuitry in battery powered devices.

Abstract: A TTL/CMOS compatible input buffer circuit comprises a Schmitt trigger input buffer stage and a reference voltage generator. In the TTL mode, the reference voltage generator supplies a reference voltage having a level that forces the trigger point of the Schmitt trigger to a predetermined value. In the CMOS mode, the reference voltage generator is disabled and a voltage equal to the power supply voltage is provided to the Schmitt trigger. The input buffer circuit affords an enhanced input noise margin and minimizes DC power loss.