Abstract: A magneto-inductive flow measuring device including a coil arrangement and a circuit for controlling a supply voltage of the coil arrangement. The circuit is designed to provide the supply voltage of the coil arrangement with a voltage curve sequenced as follows: A) the voltage rises from a starting voltage I up to an overvoltage II; B) in given cases, the voltage is held at the overvoltage II; C) the voltage falls from the overvoltage II down to a holding voltage V. The circuit controls the fall of the voltage from the overvoltage down to the holding voltage by tuning the voltage to at least two or more predetermined, intermediate, desired values III, IV.

Abstract: A level-shifting circuit includes an input node, a first output transistor, a second output transistor, a pull-up transistor, and an output node. The input node receives an input signal. The first output transistor turns on when the input signal is at a first voltage level and couples an output node to a positive supply voltage when turned on. The second output transistor, a bipolar junction transistor (BJT), couples the output node to a negative supply voltage when turned on. The pull-up transistor turns on when the input signal is at a second voltage level and generates a voltage at a base terminal of the second output transistor that turns the second output transistor on. Additionally, the level-shifting circuit generates, at the output node, an output signal with a voltage swing that includes a positive voltage range and a negative voltage range.

Abstract: There is disclosed a MOS transistor output circuit capable of suppressing ringing and other noises and of operating at high speed under low power supply voltages. A signal corresponding to an input signal is applied to the gates of a first p-channel MOS transistor and a first n-channel MOS transistor. A control circuit detects the falling edge of the input signal to create a first signal. A second p-channel MOS transistor is held in conduction by the first signal during a period beginning with the rising edge of the output signal and ending with the instant at which the output signal can be regarded as having logic high (H) level. The rising edge of the input signal is detected to create a second signal. A second n-channel MOS transistor is held in conduction by the second signal during a period beginning with the falling edge of the output signal and ending with the instant at which the output signal can be regarded as having logic low (L) level.

Abstract: Integrated buffer circuits which are less susceptible to noise and provide TTL-to-CMOS signal conversion capability include a first TTL-compatible inversion buffer, a second CMOS-compatible inversion buffer having an input electrically coupled to an output of the first inversion buffer and a preferred pull-up (or pull-down) circuit to improve noise immunity. The preferred circuit pulls the output of the first inversion buffer to a potential of the first reference signal line (e.g., Vdd) in response to a signal at an output of the second inversion buffer and a signal at an input of the first inversion buffer. This circuit comprises a first field effect transistor having a gate electrode electrically coupled to the output of the second inversion buffer and a second field effect transistor having a gate electrode electrically coupled to the input of the first inversion buffer.