Abstract: The RC sensor circuit includes a driver circuit that includes an output configured to drive the RC sensor circuit to a drive voltage using a representative copy of a current that drives an electronic circuit line. The RC sensor circuit includes an integration capacitor. The integration capacitor is configured to integrate the representative copy of the current over a first time period to generate a first representative voltage and over a second time period to generate a second representative voltage. The RC sensor circuit includes a sampling circuit coupled to the integration capacitor. The sampling circuit is configured to determine a first sample voltage by sampling the first representative voltage and a second sample voltage by sampling the second representative voltage. A ratio of the first sample voltage and the second sample voltage is indicative of an RC time constant of the electronic circuit line.

Abstract: In hard disc drive (HDD) applications, there is often a need for input buffers that can operate at a variety of voltages (i.e., 1.8V, 2.5V, and 3.3V) as well as tolerate high voltages (i.e., 5V). Traditional buffers, however, usually lack the ability to operate at these varying voltages and lack the ability to tolerate high voltages. Here, a buffer is provided that fits this criteria through the use of a switching circuit and an anti-saturation circuit (as well as other circuitry).

Abstract: An integrated circuit structure includes a well region of a first conductivity type, an emitter of a second conductivity type opposite the first conductivity type over the well region, a collector of the second conductivity type over the well region and substantially encircling the emitter, and a base contact of the first conductivity type over the well region. The base contact is horizontally spaced apart from the emitter by the collector. At least one conductive strip horizontally spaces the emitter, the collector, and the base contact apart from each other. A dielectric layer is directly under, and contacting, the at least one conductive strip.

Abstract: A semiconductor device includes: a GaAs chip; and a resin sealing the GaAs chip. The GaAs chip includes: a p-type GaAs layer; an n-type GaAs layer on the p-type GaAs layer; a metal electrode located on the n-type GaAs layer along an edge of the GaAs chip and to which a positive voltage is applied; a device region located in a central portion of the GaAs chip; a semi-insulating region located between the metal electrode and the device region and extending in the p-type GaAs layer and the n-type GaAs layer; and a connecting portion disposed outside the semi-insulating region and electrically connecting the p-type GaAs layer to the metal electrode.

Abstract: A lateral bipolar junction transistor having improved current gain and a method for forming the same are provided. The transistor includes a well region of a first conductivity type formed over a substrate, at least one emitter of a second conductivity type opposite the first conductivity type in the well region wherein each of the at least one emitters are interconnected, a plurality of collectors of the second conductivity type in the well region wherein the collectors are interconnected to each other, and a plurality of base contacts of the first conductivity type in the well region wherein the base contacts are interconnected to each other. Preferably, all sides of the at least one emitters are adjacent the collectors, and none of the base contacts are adjacent the sides of the emitters. The neighboring emitter, collectors and base contacts are separated by spacings in the well region.

Abstract: A level-shifting circuit includes an input node, a first output transistor, a second output transistor, a pull-up transistor, and an output node. The input node receives an input signal. The first output transistor turns on when the input signal is at a first voltage level and couples an output node to a positive supply voltage when turned on. The second output transistor, a bipolar junction transistor (BJT), couples the output node to a negative supply voltage when turned on. The pull-up transistor turns on when the input signal is at a second voltage level and generates a voltage at a base terminal of the second output transistor that turns the second output transistor on. Additionally, the level-shifting circuit generates, at the output node, an output signal with a voltage swing that includes a positive voltage range and a negative voltage range.

Abstract: A plurality of transistors are connected between an I2C bus operating at a first voltage level and an I2C bus operating at a second voltage level and a main control electrode of at least one transistor is connected to a first power supply terminal and a main control electrode of the other at least one transistor is connected to an intermediate level between the first voltage level and the second voltage level, whereby a withstand voltage required to a transistor of the bidirectional level shift circuit of the I2C bus can be lowered.

Abstract: The present invention provides for a device to reduce the voltage swing for control signals. An input signal with a maximum potential of DVDD and minimum potential of AVSS is level shifted to a maximum potential of AVDD and a minimum potential of AVDD-DVDD. A series of control signals are generated from the level shifted input signal by standard logic cells. The shifting of the input signal reduces the voltage swing for the control signals. These control signals are then used to drive a device operating at a potential of AVDD.

Abstract: An apparatus for shifting a received signal at a first reference level to an output signal at a second reference level; the received signal including information-indicating signal values; includes: (a) an input locus for receiving the received signal; (b) an output locus for presenting the output signal; (c) a first signal-handling circuit coupled with the input locus and with the output locus and setting the second reference level at the output locus; and (d) a second signal-handling circuit coupled with the input locus and with the first signal-handling circuit; the first signal-handling circuit and the second signal-handling circuit cooperating to convey the information-indicating signal values from the input locus to the output locus.

Abstract: An apparatus and method for driving an output signal in a high speed integrated circuit. The apparatus and methods enable the output voltage swing from the driver to exceed the breakdown voltage of any individual element in the output driver. A high speed driver can utilize one or more transistors in a stacked configuration, such that the breakdown voltage of the entire stacked configuration is based on the number of transistors in the stack. The driver is configured to distribute the output voltage substantially equally among each of the stacked transistors, such that the driver is able to source an output voltage swing that is greater than the breakdown voltage of any individual transistor in the driver.

Abstract: In accordance with the present invention, the circuit apparatus has a first and a second connection point each for respectively connecting to the first bay and second bay for communicating with them to determine which device in the bays is the master device. The circuit apparatus also has a third and a fourth connection point both of them for connecting to the first bay or second bay for receiving the Boolean algebra to determine which device is the master device. The circuit apparatus further has a fifth connection point for determining whether the circuit apparatus works.

Abstract: A voltage level conversion circuit for converting a voltage level of a low voltage system input signal into a voltage level of a high voltage system signal comprises a latch circuit comprising plural high-breakdown-voltage MOS transistors having a high power supply voltage as a breakdown voltage, a first high-breakdown-voltage N channel MOS transistor which discharges one of the latch nodes of the latch circuit, and a second high-breakdown-voltage N channel MOS transistor which discharges the other latch node, and a pulse signal obtained by boosting a low voltage system pulse signal is applied to a gate of the first or second high-breakdown voltage N channel MOS transistor when the input signal transits.

Abstract: An improved low voltage to high voltage translator for digital electronic circuits providing reduced rise times, fall times and transition times that remain independent of operating conditions. This is accomplished by modifying a conventional low-to-high voltage translator to include a switched active pull-up at the output of the first high-voltage switch, controlled by the input low-voltage signal and gated by the output from the low-to-high-voltage translator and a switched active pull-down at the output of the first high-voltage switch, controlled by the input low-voltage signal and gated by the complement of the output from the low-to-high-voltage translator, so as at to provide regenerative pull-up and pull-down that also counteracts the bootstrap capacitance at the output of the first high-voltage switch.

Abstract: A semiconductor integrated circuit device includes a level-shifting circuit, a current mirror circuit and a switch circuit. The level-shifting circuit level-shifts an input signal having a first amplitude to an output signal having a second amplitude. The current mirror circuit charges or discharges an output node of the level-shifting circuit. The switch circuit operates the current mirror circuit during a period from the inversion of the input signal to the inversion of the output signal.

Abstract: The invention relates to a current mode device (CMD). The CMD comprises a first, a second and a third pairs of voltage controlled current sources (CCS). The first pair has an active load that is controlled by the third pair. The first pair provides a first and a second output signal that drive the second pair. The second pair generates a first digital output signal and a second output digital signal depending on a first input signal and on a second input signal, respectively. The CMD further comprises a first, a second and a third current sources that supply a first current (C1) in the first pair, a second current (C2) in the second pair and a third current (C3) in the third pair. The overall delay depends on a ratio between C1 and C2 and the sharpness of the edges of the signals depend on a ratio between C1 and C3, respectively. Furthermore, the second pair controls the amplification of the first pair by controlling the impedance of the active load.

Abstract: An ultra high speed Emitter Coupled Logic (ECL) flip-flop is provided and a method of operating the same. The ECL flip-flop provides for clock levels that operate at logic levels above the data levels. Since the clock operates at logic levels above the data, the clock experiences level shifts that are less than the level shifts of the data. Therefore, the clock will provide a higher fidelity signal relative to the conventional clock signal. The ECL flip-flop can operate at significantly higher data rates than conventional flip-flop circuitry.

Abstract: A current mode logic (CML) circuit includes an emitter follower circuit, a CML gate, and a Schottky diode that is coupled between the emitter follower circuit and the CML gate. Methods and other systems are also provided.

Abstract: An improved ECL circuit, based upon an ECL circuit of conventional design, functions as the required transceiver for the bi-directional data transmission between a computer and an electronic device with a specific interface of USB 2.0. The value of an emitter resistor within an emitter resistance network in the conventional ECL circuit is adjusted till its output voltage amplitude meets the USB 2.0 specification. A number of voltage level shifting and capacitive coupling circuits are added to both the input and output sections of the conventional ECL circuit making it directly interfaceable with the popular CMOS logic family. A collector electrode switch network is also added to the conventional ECL circuit to make its output terminals tri-statable thus compatible with the communication scheme of half duplexing under the USB 2.0 specification.

Abstract: The circuit configuration for converting logic levels has a bipolar input stage and a CMOS output stage. The bipolar input stage is equipped to process ECL and CML logic levels. The CMOS-logic output stage is equipped to supply trailing CMOS gates having CMOS logic levels. A difference amplifier includes bipolar transistors, which are connected to a common emitter current source and to separate collector current sources. An input-output feedback CMOS inverter is connected to one of the collectors, and the output of the inverter is coupled to an output node.

Abstract: This invention relates to a circuit structure of the feedforward type with programmable zeroes, particularly for synthesizing time-continual filters. This structure comprises a pair of amplification cells interconnected at least one interconnection node and connected between a first signal input of a first cell and an output terminal of the second cell, each cell comprising a pair of transistors which have a conduction terminal in common and have the other conduction terminals coupled respectively to a first voltage reference through respective bias members. The structure further comprises a circuit leg connecting a node of the first cell to the output terminal and comprising a transistor which has a control terminal connected to the node of the first cell, a first conduction terminal connected to the output terminal, and a second conduction terminal coupled to a second voltage reference through a capacitor.

Abstract: In a method and in a circuit arrangement for transmitting signals from an output of a first circuit to an input of a second circuit, where the circuits have a first and a second operating voltage and a first and a second ground potential applied to them, and where variable potential differences can arise between the ground potentials. A current controlled by the signal which is to be transmitted flows from the output of the first circuit to a circuit point having a further potential applied to it and controls a further current, which emanates from the circuit point and is supplied to the input of the second circuit, and the further potential is chosen such that a respective voltage enabling the current and the further current is present between the output of the first circuit and the further potential, on the one hand, and between the further potential and the input of the second circuit, on the other hand, for the potential differences which arise.

Abstract: A circuit (10) for providing TTL logic signals at an output (24) employs dual pull up devices (20, 30) at the output. The first device (20) is a bipolar transistor that acts as an emitter-follower to quickly pull up the output in response to applied logic signals to drive the output to a logic one state. Thereafter, the second device (30) which is a MOS transistor is turned on to drive the magnitude of the high logic output signal to substantially VCC, the positive power supply voltage supplied to the circuit (10).

Abstract: A signal level shifting circuit comprises an emitter-follower transistor with a base supplied with an input signal, a collector coupled to a supply voltage, and an emitter coupled via a level shifter to a bias circuit, whereby a level shifted signal is produced at a junction point between the level shifter and the bias circuit. The level shifter comprises one or more diodes to provide a forward voltage drop providing a signal level shift, a PMOS transistor switch in parallel with the diode(s), and a control circuit responsive to the supply voltage for controlling the switch to bypass the diode(s), thereby providing a smaller level shift, when the supply voltage has a lower one of two possible values. The circuit can have a differential input and a differential output stage, and cascode-connected transistors for reducing voltages so that the circuit can be implemented using BCMOS technology.

Abstract: The invention relates to an electronic circuit, and in particular embodiments to a level shifting circuit having an output common mode voltage independent of the input common mode voltage, and unity differential signal gain. The circuit receives first and second input voltages, referenced to a first voltage supply rail, and has first and second resistors, each connected to the first input terminal, and third and fourth resistors, each connected to the second input terminal, the second and third resistors having equal resistance values. The first resistor is also connected to a first output terminal, the fourth resistor is also connected to a second output terminal, and the second and third resistors are also connected together at a reference node.

Abstract: High-speed signal translators are provided to convert differential input signals (e.g., ECL signals) to single-ended output signals (e.g., CMOS signals). An exemplary translator is formed with first and second current mirrors, first and second complimentary differential pairs of transistors, a complimentary transistor output stage and first and second current-diverting transistors. The complimentary output stage initially generates the single-ended output signal in response to currents received from the complimentary differential pairs. When the output signal has been established, the current-diverting transistors respond by carrying at least portions of the currents supplied by the complimentary differential pairs. The current-diverting transistors also drive the current mirrors to divert other portions of these currents away from the complimentary output stage. Stored charges in the output stage are accordingly reduced and its response time enhanced.

Abstract: A system and method for translating a non-logic-family signal level into a logic-family signal level, the system comprising: a source of a non-logic-family signal that can assume a first and a second non-logic-family state; and a translator for determining whether the signal is in the first non-logic-family state, and if so, providing a translated signal having a first-logic family level. The translator can take the form of a comparator controlling an output transistor tied to a pull-up resistor, or a programmed processor. Examples of the logic-families include transistor-transistor logic (TTL) and complimentary metal oxide semiconductor (CMOS) logic. Examples of sources of non-logic-family signals includes a light emitting diode, a buzzer and a beeping device.

Abstract: A high-speed bipolar-to-CMOS logic converter circuit, including an input stage, including a differential amplifier meant to be connected to a bipolar-logic circuit portion and to be supplied by the supply voltage of the bipolar-logic portion, and an output stage, which is supplied by the voltage of a CMOS-logic circuit portion, a dynamic level shifting circuit interposed between the input stage and the output stage, the output stage being connected to the CMOS-logic circuit portion.

Abstract: Circuits using differential logic are employed in high-speed optical communications systems. An essential problem in the design of large-scale integrated circuits for this purpose is the control of undesired heat generation, so that the circuits should have low power consumption. According to the invention, a reduction in power consumption is achieved by reducing the number of stages connected in parallel with respect to the power supply. To accomplish this, part of the parallel-connected stages are connected in series with the remaining part of the parallel-connected stages, so that the total number of parallel branches is reduced.

Abstract: An input circuit includes a pair of common-base circuits having respective transistors including respective bases to which differential signals transmitted through a transmission line are input and constant current sources connected to the emitters of the transistors, and a level shift circuit for inputting, to the emitters of the common-base circuits, differential signals with anti-phase relation to the differential signals input to the bases of the common-base circuits. This input circuit has lower power consumption and can be used to match impedance.

Abstract: A logic selection circuit for selectively matching the transistor logic type of a first interfacing circuit with the transistor logic type of a second interfacing circuit. The logic selection circuit comprises a circuit latching means which latches the level of voltage signal present at the second interfacing circuit while receiving a signal from the first interfacing circuit. The logic selection circuit further comprises both an NPN transistor and a PNP transistor to ensure that the transistor logic type of the first interfacing circuit and the transistor logic type of the second interfacing circuit may be properly matched. The logic selection circuit disclosed may be utilized in a conventional magnetic proximity sensor which helps to control the movement of a piston within a cylinder.

Abstract: A low-voltage, high-speed voltage level interface circuit for signal level translation between circuits operating at different supply voltages. The circuit utilizes a folded cascode structure with a separate reference voltage to achieve high-speed and low-voltage performance. Voltage divider circuits are provided at the signal and reference inputs.

Abstract: A semiconductor integrated circuit device has a differential logic circuit formed by multi-stage series-gating logic circuits each composed of bipolar transistors whose emitters are connected in common and level shift circuits each for shifting a level of an input signal that is inputted from the outside in correspondence to one of the stage logic circuits of the differential logic circuit, and for supplying the level-shifted input signal to the base of one of the bipolar transistors of the corresponding logic circuit. In particular, a potential difference between the level-shifted signals inputted to the bases of the bipolar transistors of each of the stage logic circuits is determined, as a level shift rate, to be lower than a built-in potential between the base and emitter of each of the bipolar transistors thereof. The semiconductor integrated circuit device is operative on a lower supply voltage, without significantly degrading the functions and performance thereof.

Abstract: A first current switch circuit 1a outputs a first logic signal and a complementary signal thereof in response to an input logic signal. A pull-up transistor Q10 has a base receiving the first logic signal. A second current switch circuit 1b outputs a second logic signal based on the complementary signal and the potential of an output terminal OUT1. A level shift circuit 1c shifts the level of the second logic signal and provides it to the base of a pull-down transistor Q11. When the potential of an input terminal IN1 changes from a low level to a high level, a capacitive load CL is discharged through transistors Q9 and Q11. When the potential of output terminal OUT1 becomes lower than that of a first reference potential terminal VBB1, the second logic signal attains a low level, thereby turning off pull-down transistor Q11.

Abstract: A level shifter circuit for converting an input signal referenced to the least positive power supply (typically ground) to an output signal referenced to a higher, more usable voltage. The level shifter circuit generally includes a current mirror arrangement for coupling first and second current legs. The first current leg includes an NPN bipolar transistor arranged in series with a resistor R and a PNP bipolar transistor, wherein the NPN and PNP transistors have base inputs V.sub.ref and V.sub.in, respectively. The second current leg comprises a series arrangement of a diode-connected NPN bipolar transistor, a resistor R and a diode-connected NPN bipolar transistor. An output voltage (V.sub.OUT =V.sub.ref -V.sub.in), is taken at the collector of the diode-connected NPN transistor in the second current leg.

Abstract: There is disclosed a signal processing device which includes a pre-processing circuit (31) for performing a serial-to-parallel conversion on an intermediate signal (M.sub.2) at a PECL level, the serial-to-parallel conversion at the PECL level being permitted to deal with a high frequency, and a level converter circuit (12) for performing a conversion from the ECL to PECL levels both having the same logic level width, which conversion consumes less power than a conversion between the ECL and CMOS levels having different logic level widths. The level conversion of a parallel signal requires less power consumed than a level conversion of a serial signal. The signal processing device further includes a level converter circuit (13) for performing a conversion into the CMOS level after obtaining an intermediate signal (M.sub.3) which is a parallel signal. An intermediate signal (M.sub.4) is at the CMOS level and has a low frequency.

Abstract: Switching between two logic circuits that produce outputs at different respective logic levels is accomplished by means of a common input differential switch that has a branch in each logic circuit. A common current source supplies current to the branches within each logic circuit. The current source remains on regardless of which logic level is selected, thereby enhancing switching speed. The logic circuits produce logic outputs at a common output differential switch, which in turn provides a selected output to a single output terminal. The logic circuits are configured so that the output from the circuit corresponding to the selected logic level dominates the output from the other logic circuit at the output differential switch.

Abstract: A cable connection between a PC and a sewing machine for transmitting data in the form of different voltage levels, wherein the cable connection for connection to the PC has an RS 232 C port and the sewing machine has a TTL port. A level converter is integrated in the cable connection, preferably in the connection jack to the RS 232 C port. The level converter has a switching transistor controllable by the sending pole of the TTL port and a switching transistor controllable by the sending pole of the 232 port for connecting the corresponding receiving pole to a voltage potential which it is able to receive.

Abstract: An interface circuit is designed to connect a first logic circuit such as a microcontroller with a second similar microcontroller using three wires and allowing for simultaneous transfer of data from each of the microcontrollers to the other. A transmitter element in each interface circuit has a bias resistor which cooperates with a pull-up resistor in the other interface circuit to provide an indication for one of the logic circuits when the other of the logic circuits and its associated interface circuit loses power or when one of the three connecting wires is disconnected.

Abstract: Polymer or copolymer of vinyl chloride having superior properties can be produced by suspension-polymerizing vinyl chloride or a mixture thereof with another vinyl monomer, at first, in the presence of an oil-soluble radical initiator, and thereafter, when the percentage of polymerization of the resulting polymer has reached about 15% to about 80%, subjecting the polymer to a further polymerization in the presence of a water-soluble radical initiator.The product thus obtained has both the merits resulting from suspension polymerization and emulsion one. It has an extremely high absorptivity of plasticizer, easy processability, and film made therefrom has substantially no fish eye.