Ecl To/from Mos Patents (Class 326/77)
  • Patent number: 7969189
    Abstract: System and method for a clock driver. An input taking circuit is used for receiving small-signal logic inputs. A voltage follower circuit is coupled to the input taking circuit and used to generate a set of voltage follower outputs. An output circuit is coupled to the voltage follower circuit to receive the set of voltage follower outputs as inputs and generate output signals. The voltage follower circuit is coupled to a switching circuit, that is connected to the set of voltage follower outputs and is deployed for reducing the phase noise level of the output signals.
    Type: Grant
    Filed: November 24, 2009
    Date of Patent: June 28, 2011
    Assignee: Linear Technology Corporation
    Inventor: Joseph Gerard Petrofsky
  • Patent number: 7928765
    Abstract: Electronic circuitry and techniques are disclosed for controlling one or more timing parameters associated with a circuit that converts a signal of a first type to a signal of a second type. For example, the converter circuit may convert a differential digital logic signal, such as a current mode logic (CML) signal, to a complementary metal oxide semiconductor (CMOS) signal. For example, apparatus for converting a first type of signal to a second type of signal comprises the following circuitry. First circuitry is configured for generating a first pair of CMOS signals in response to a differential digital logic signal, the first pair of CMOS signals comprising a first CMOS signal having a first polarity and a second CMOS signal having a second polarity.
    Type: Grant
    Filed: March 30, 2009
    Date of Patent: April 19, 2011
    Assignee: LSI Corporation
    Inventors: Anamul Hoque, Cameron C. Rabe
  • Patent number: 7714614
    Abstract: A serial data receiving apparatus includes a transistor, a resistor, and a diode, converts input data of an RS232 standard to data of a TTL/CMOS standard.
    Type: Grant
    Filed: January 14, 2008
    Date of Patent: May 11, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jeong-kee Park
  • Patent number: 7688111
    Abstract: A level-shifting circuit includes an input node, a first output transistor, a second output transistor, a pull-up transistor, and an output node. The input node receives an input signal. The first output transistor turns on when the input signal is at a first voltage level and couples an output node to a positive supply voltage when turned on. The second output transistor, a bipolar junction transistor (BJT), couples the output node to a negative supply voltage when turned on. The pull-up transistor turns on when the input signal is at a second voltage level and generates a voltage at a base terminal of the second output transistor that turns the second output transistor on. Additionally, the level-shifting circuit generates, at the output node, an output signal with a voltage swing that includes a positive voltage range and a negative voltage range.
    Type: Grant
    Filed: August 21, 2008
    Date of Patent: March 30, 2010
    Assignee: SuVolta, Inc.
    Inventor: Abhijit Ray
  • Patent number: 7688110
    Abstract: A system for providing a CMOS I/O circuit design that may replace existing bipolar I/O circuitry, and thus behave in substantially the same manner as bipolar I/O circuitry. Thus, an I/O circuit using a standard CMOS process is made that mimics operation of an ECL I/O circuit created using bipolar transistors. The CMOS input circuitry can receive input signals from an ECL output circuit, so as to mimic traditional ECL input circuitry. The CMOS output circuitry can output signals to an ECL input circuit, so as to mimic traditional ECL output circuitry. The CMOS I/O circuitry is designed to mimic the temperature dependent signals level, as present within traditional ECL I/O circuitry.
    Type: Grant
    Filed: January 7, 2008
    Date of Patent: March 30, 2010
    Assignee: Honeywell International, Inc.
    Inventors: Jeffrey D. Loukusa, Said E. Abdelli
  • Patent number: 7646219
    Abstract: An integrated circuit (200) includes a translator circuit (210) for translating from a lower logic-level voltage range signal (101(a), 101(b)) to a higher logic-level voltage range signal (141(a), 141(b)). The translator (210) includes a differential input stage (110) including a first (Q39) and a second input transistor (Q38) coupled to receive at least a first input signal (101(a), 101(b)) that defines the lower voltage range signal. A voltage follower 120 includes first and second follower transistors (Q41, Q40). An output of the first and second input transistors (Q39, Q38) is coupled to inputs of the first and second follower transistors (Q41, Q40). A dynamic gain boosting switching circuit (130) is coupled to receive outputs from the first and second follower transistors (Q41, Q40) and includes a first and a second control node (131, 132).
    Type: Grant
    Filed: August 14, 2008
    Date of Patent: January 12, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Priscilla E. Escobar-Bowser, Indumini Ranmuthu
  • Patent number: 7327164
    Abstract: An interface circuit includes a first and a second input terminal, a first output transistor, a second output transistor, a first output controller for implementing control according to a voltage supplied to the first and the second input terminal so that a predetermined current appears at a control terminal of the first output transistor if the first output transistor is in saturated state and supplies a predetermined current to the control terminal of the first output transistor if the first output transistor is in shutoff state, and a second output controller for implementing control according to a voltage supplied to the first and the second input terminal so that a predetermined current appears at a control terminal of the second output transistor if the second output transistor is in saturated state and supplies a predetermined current to the control terminal of the second output transistor if the second output transistor is in shutoff state.
    Type: Grant
    Filed: February 7, 2006
    Date of Patent: February 5, 2008
    Assignee: NEC Electronics Corporation
    Inventor: Jianqin Wang
  • Patent number: 7129750
    Abstract: A CMOS to PECL voltage level converter includes a pad driver containing drive compensation circuitry and a feedback circuit for sensing the output drive level and providing control signals to the drive compensation circuitry for compensating for temperature and process variations while minimizing power consumption.
    Type: Grant
    Filed: July 30, 2004
    Date of Patent: October 31, 2006
    Assignee: STMicroelectronics Pvt. Ltd.
    Inventor: Hari B. Dubey
  • Patent number: 6956400
    Abstract: The invention relates to a converter from ECL to CMOS having an input stage (Q1, Q2, N3, N4), a level shifter stage (N1, N2, N5, R1, R2, R3) including an NFET differential stage (N1, N2), and an output stage (P1, P2, P3, P4, N6, N7, N8, N9), and to a network element for transmitting signals which comprises a converter from ECL to CMOS having an input stage (Q1, Q2, N3, N4), a level shifter stage (N1, N2, N5, R1, R2, R3), and an output stage (P1, P2, P3, P4, N6, N7, N8, N9), with the level shifter stage (N1, N2, N5, R1, R2, R3) including an NFET differential stage (N1, N2).
    Type: Grant
    Filed: November 20, 2003
    Date of Patent: October 18, 2005
    Assignee: Alcatel
    Inventor: Frank Ilchmann
  • Patent number: 6888370
    Abstract: The on-chip impedance termination circuits can be dynamically adjusted to match transmission line impedance values. A network of termination resistors on an integrated circuit provides termination impedance to a transmission line coupled to an IO pin. The termination resistors are coupled in series and in parallel with each other. Pass gates are coupled to the resistors. The pass gates are individually turned ON or OFF to couple or decouple resistors from the transmission line. Each pass gate is set to be ON or OFF to provide a selected termination resistance value to the transmission line. The termination resistance of the resistor network can be increased or decreased to match the impedance of different transmission lines. The termination resistance can also be varied to compensate for changes in the resistors caused by temperature variations on the integrated circuit or other factors.
    Type: Grant
    Filed: August 20, 2003
    Date of Patent: May 3, 2005
    Assignee: Altera Corporation
    Inventors: Mei Luo, Wilson Wong, Sergey Shumarayev
  • Patent number: 6828821
    Abstract: An input buffer circuit includes front stage circuits and a succeeding stage circuit. Each of the front stage circuits has a logic threshold voltage different from each other. The succeeding stage circuit has a P type MOS transistor and an N type MOS transistor connected in series. The succeeding circuit includes inputs connected to the front stage circuit. A logic threshold voltage of the succeeding stage circuit is set to be between the respective logic threshold voltages of the front stage circuits.
    Type: Grant
    Filed: May 30, 2002
    Date of Patent: December 7, 2004
    Assignee: Oki Electric Industry Co, Ltd.
    Inventor: Atsushi Nagayama
  • Patent number: 6714043
    Abstract: An input/output buffer is provided with an output buffer portion which can be used to make an integrated circuit selectively compatible with one of a number of interface types, such as PCI, GTL, PECL, ECL and SSTI. The output buffer portion has an input connected to an output signal node (D) where components on the integrated circuit provide an output signal for connecting to external circuits at an output pad (PAD). Control power switches driving the gates of multiple CMOS buffer transistors to provide sufficient current for rapid switching, and limit current after switching to prepare for a subsequent output transition. The CMOS buffer transistors are selectively enabled to control output drive current. Selectable pull-up and pull-down reference circuits provide references (VRFPU, VRFPPU, VRFPD and VRFPPD) to control the current of the buffer output during transition of the output, while maintaining the output voltage level at a desired voltage with minimal current level after transition.
    Type: Grant
    Filed: May 16, 2002
    Date of Patent: March 30, 2004
    Assignee: Lattice Semiconductor Corporation
    Inventor: Bradley A. Sharpe-Geisler
  • Patent number: 6696858
    Abstract: A semiconductor integrated circuit device includes a level-shifting circuit, a current mirror circuit and a switch circuit. The level-shifting circuit level-shifts an input signal having a first amplitude to an output signal having a second amplitude. The current mirror circuit charges or discharges an output node of the level-shifting circuit. The switch circuit operates the current mirror circuit during a period from the inversion of the input signal to the inversion of the output signal.
    Type: Grant
    Filed: September 5, 2001
    Date of Patent: February 24, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoichi Tokai
  • Patent number: 6693457
    Abstract: An ultra high speed Emitter Coupled Logic (ECL) flip-flop is provided and a method of operating the same. The ECL flip-flop provides for clock levels that operate at logic levels above the data levels. Since the clock operates at logic levels above the data, the clock experiences level shifts that are less than the level shifts of the data. Therefore, the clock will provide a higher fidelity signal relative to the conventional clock signal. The ECL flip-flop can operate at significantly higher data rates than conventional flip-flop circuitry.
    Type: Grant
    Filed: July 18, 2002
    Date of Patent: February 17, 2004
    Assignee: Northrop Grumman Corporation
    Inventor: Ronald J. Yepp
  • Patent number: 6593774
    Abstract: An improved ECL circuit, based upon an ECL circuit of conventional design, functions as the required transceiver for the bi-directional data transmission between a computer and an electronic device with a specific interface of USB 2.0. The value of an emitter resistor within an emitter resistance network in the conventional ECL circuit is adjusted till its output voltage amplitude meets the USB 2.0 specification. A number of voltage level shifting and capacitive coupling circuits are added to both the input and output sections of the conventional ECL circuit making it directly interfaceable with the popular CMOS logic family. A collector electrode switch network is also added to the conventional ECL circuit to make its output terminals tri-statable thus compatible with the communication scheme of half duplexing under the USB 2.0 specification.
    Type: Grant
    Filed: December 7, 2001
    Date of Patent: July 15, 2003
    Assignee: Highpoint Technologies, Inc.
    Inventor: Qi Li
  • Publication number: 20030112034
    Abstract: An improved ECL circuit, based upon an ECL circuit of conventional design, functions as the required transceiver for the bi-directional data transmission between a computer and an electronic device with a specific interface of USB 2.0. The value of an emitter resistor within an emitter resistance network in the conventional ECL circuit is adjusted till its output voltage amplitude meets the USB 2.0 specification. A number of voltage level shifting and capacitive coupling circuits are added to both the input and output sections of the conventional ECL circuit making it directly interfaceable with the popular CMOS logic family. A collector electrode switch network is also added to the conventional ECL circuit to make its output terminals tri-statable thus compatible with the communication scheme of half duplexing under the USB 2.0 specification.
    Type: Application
    Filed: December 7, 2001
    Publication date: June 19, 2003
    Applicant: HighPoint Technologies, Inc.
    Inventor: Qi Li
  • Patent number: 6429691
    Abstract: A circuit provides differential logic signals and includes a differential-input circuit having a first differential input and a second differential input. A first unit receives an input voltage signal and a supply voltage for providing a first voltage to the first differential input via a first node. A second unit receives the supply voltage for providing a second voltage to the second differential input via a second node. The differential-input circuit outputs a signal in accordance with the first and second voltages.
    Type: Grant
    Filed: December 29, 2000
    Date of Patent: August 6, 2002
    Assignee: International Business Machines Corporation
    Inventor: Jungwook Yang
  • Patent number: 6351149
    Abstract: There is disclosed a MOS transistor output circuit capable of suppressing ringing and other noises and of operating at high speed under low power supply voltages. A signal corresponding to an input signal is applied to the gates of a first p-channel MOS transistor and a first n-channel MOS transistor. A control circuit detects the falling edge of the input signal to create a first signal. A second p-channel MOS transistor is held in conduction by the first signal during a period beginning with the rising edge of the output signal and ending with the instant at which the output signal can be regarded as having logic high (H) level. The rising edge of the input signal is detected to create a second signal. A second n-channel MOS transistor is held in conduction by the second signal during a period beginning with the falling edge of the output signal and ending with the instant at which the output signal can be regarded as having logic low (L) level.
    Type: Grant
    Filed: December 3, 1999
    Date of Patent: February 26, 2002
    Assignee: Nippon Precision Circuits, Inc.
    Inventor: Satoru Miyabe
  • Patent number: 6323683
    Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a differential intermediate signal in response to a differential input signal. The second circuit may be configured to generate one or more output signals in response to said differential intermediate signal.
    Type: Grant
    Filed: August 27, 1999
    Date of Patent: November 27, 2001
    Assignee: Cypress Semiconductor Corp.
    Inventor: Pradeep Katikaneni
  • Patent number: 6252421
    Abstract: The invention relates to the interfacing of high speed, low voltage data streams with CMOS circuits and, more specifically, to converting low voltage, differential ECL signals levels to higher voltage levels which are compatible with CMOS circuits while maintaining high speed and sufficient drive capability. This is accomplished by making first stage inverters 5 and 6 as geometrically small as possible subject to the design rules in use to minimize the capacitance at the input of these inverters. The inputs of the first stage inverters are clamped by bias circuits 9/10/11 and 12/13/14 at DC levels so as to provide a narrow range of operation. Additional output inverters 7 and 8 act as buffers to provide the needed capacitive load drive capability.
    Type: Grant
    Filed: July 27, 1998
    Date of Patent: June 26, 2001
    Assignee: Texas Instruments Incorporated
    Inventor: Sami Kiriaki
  • Patent number: 6175249
    Abstract: A logic level converter for translating CMOS logic signals to into differential logic signal pairs such as those associated with ECL levels. The converter includes a first converter branch coupled to the switchable CMOS level input and it provides a first switchable translated output. A second converter branch is not coupled to the input nor is it coupled to the first converter branch. The second converter branch provides a fixed reference signal output around which the output of the first converter branch switches. Changes in the input signal to the first converter branch cause its output potential to be more than or less than the potential of the fixed reference signal supplied by the second converter branch. The components of the respective branches may be tailored to position the fixed signal at a selectable level and to define the differential between the two output signals.
    Type: Grant
    Filed: January 29, 1999
    Date of Patent: January 16, 2001
    Assignee: Fairchild Semiconductor Corp.
    Inventor: Trenor F. Goodell
  • Patent number: 6169432
    Abstract: A voltage switch is provided made up of 2.5 volt process transistors which tolerate a maximum gate to source, gate to drain, or drain to source voltage of 2.7 volts. The voltage switch transistors are arranged to switch between a voltage, such as 2.5 volts, and a much higher voltage, such as 4.5 volts. In one embodiment (350), the voltage switch includes an input provided to the source of an NMOS cascode connected transistor (360). An inverter (354) connects the source of the NMOS cascode (360) to the source of another NMOS cascode (361). A cascode transistor is defined as being connected so that it is turned on and off by varying source voltage with the gate voltage fixed, rather than varying gate voltage. Gates of the cascodes (360, 361) are connected to Vcc (2.5 volts). PMOS cascode transistors (362) and (363) connect the drains of respective cascode transistors (360) and (361) to PMOS transistors (364) and (365). The PMOS transistors (364) and (365) have sources connected to 4.5 volts.
    Type: Grant
    Filed: November 9, 1998
    Date of Patent: January 2, 2001
    Assignee: Vantis Corporation
    Inventor: Bradley A. Sharpe-Geisler
  • Patent number: 6140842
    Abstract: This invention relates to interfacing high speed, low voltage, data streams with CMOS circuits and, more specifically, to converting low voltage, differential, ECL signal levels to higher voltage levels which are compatible with CMOS circuits while maintaining high speed and sufficient drive capability for larger system applications. This is accomplished primarily by making the first stage inverters 5 and 6 as geometrically small as possible and providing additional cross-coupled buffers 7 and 8 capable of driving large capacitive loads.
    Type: Grant
    Filed: July 27, 1998
    Date of Patent: October 31, 2000
    Assignee: Texas Instruments Incorporated
    Inventor: Sami Kiriaki
  • Patent number: 6127847
    Abstract: A high-speed bipolar-to-CMOS logic converter circuit, including an input stage, including a differential amplifier meant to be connected to a bipolar-logic circuit portion and to be supplied by the supply voltage of the bipolar-logic portion, and an output stage, which is supplied by the voltage of a CMOS-logic circuit portion, a dynamic level shifting circuit interposed between the input stage and the output stage, the output stage being connected to the CMOS-logic circuit portion.
    Type: Grant
    Filed: June 1, 1998
    Date of Patent: October 3, 2000
    Assignees: SGS--Thomson Microelectronics S.r.l., Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno
    Inventors: Guglielmo Sirna, Giuseppe Palmisano, Mario Paparo
  • Patent number: 6008667
    Abstract: An emitter-coupled logic to CMOS logic converter includes a first current mirror having a first transistor that has a terminal. The first current mirror is operable to mirror a current in the terminal of the first transistor to produce a mirrored first current. The converter also includes a first current sink operable to generate a first current in the terminal of the first transistor. The converter also includes a second current mirror having a second transistor that has a terminal. The second current mirror is operable to mirror a current in the terminal of the second transistor to produce a mirrored second current. The converter further includes a second current sink operable to generate a second current in the terminal of the second transistor and a differential input pair operable to receive a differential voltage input and direct a current, based on the differential voltage input, to the terminal of the first transistor or the terminal of the second transistor.
    Type: Grant
    Filed: November 19, 1997
    Date of Patent: December 28, 1999
    Assignee: Texas Instruments Incorporated
    Inventor: Shawn A. Fahrenbruch
  • Patent number: 5900746
    Abstract: A pair of complementary signals are switched between a high state and a low state such that the complementary signals are switched within a time period less than two gate delays. An inverter biases other inverters so that these two inverters are maintained at their threshold levels. The maintenance at the threshold values enable these two inverters to be switched quickly.
    Type: Grant
    Filed: June 13, 1996
    Date of Patent: May 4, 1999
    Assignee: Texas Instruments Incorporated
    Inventor: Benjamin Joseph Sheahan
  • Patent number: 5869994
    Abstract: A level converter circuit includes a differential amplifier 20 having a load resistor 8 supplied at its one end with a voltage which is stabilized against the variation of a power voltage by an emitter-follower transistor 4 receiving at its base a bias voltage from a bias circuit 9, 12-14. An intermediate signal is derived from the other end of the load resistor and supplied to a level shift circuit 25.
    Type: Grant
    Filed: September 19, 1996
    Date of Patent: February 9, 1999
    Assignee: NEC Corporation
    Inventor: Kouji Kimura
  • Patent number: 5805005
    Abstract: A voltage level converter circuit is presented that is capable of independently adjusting the falling edge and rising edge delays of the output signal. The circuit includes two separate transconductance amplifiers each biased independently. Each one of the transconductance amplifiers separately drives an output transistor. The circuit is particularly suited for converting ECL signals to CMOS logic levels.
    Type: Grant
    Filed: August 22, 1997
    Date of Patent: September 8, 1998
    Assignee: Exar Corporation
    Inventors: Jasleen M. Raisinghani, Craig N. Lambert
  • Patent number: 5754059
    Abstract: A circuit for converting received input signals to highly symmetrical CMOS level outputs having fast slew rates. The circuit can accept a differential input signal with a wide range of common mode voltages. A first stage level shifts the input signals to provide a ground-based common mode output to a second stage level shifter which centers the input signals around the midpoint between V.sub.cc and ground and which increases their voltage swing. The final stage provides a full, highly symmetric, rail-to-rail output capable of driving highly capacitive loads at high rates and which is immune to temperature, V.sub.cc, and process variations.
    Type: Grant
    Filed: January 14, 1997
    Date of Patent: May 19, 1998
    Assignee: International Business Machines Corporation
    Inventors: Steven J. Tanghe, Gregg R. Castellucci
  • Patent number: 5631580
    Abstract: An input stage of a level converter for converting an ECL compatible signal to an MOS compatible signal is formed as a differential amplifier. The differential amplifier produces a current that is coupled directly to a first transistor of a pair of complementary transistors, during a transition interval, to turn on the first transistor. An output signal of the first transistor is fed back to a control terminal of the first transistor via a first inverter. Consequently, the first transistor is actively turned off immediately following the transition interval. A second inverter and the first inverter form a latch for maintaining the output signal unchanged, after the first transistor is turned off.
    Type: Grant
    Filed: March 17, 1995
    Date of Patent: May 20, 1997
    Assignee: Deutsche Thomson-Brandt GmbH
    Inventor: Martin Rau
  • Patent number: 5479115
    Abstract: There is disclosed a signal processing device which includes a pre-processing circuit (31) for performing a serial-to-parallel conversion on an intermediate signal (M.sub.2) at a PECL level, the serial-to-parallel conversion at the PECL level being permitted to deal with a high frequency, and a level converter circuit (12) for performing a conversion from the ECL to PECL levels both having the same logic level width, which conversion consumes less power than a conversion between the ECL and CMOS levels having different logic level widths. The level conversion of a parallel signal requires less power consumed than a level conversion of a serial signal. The signal processing device further includes a level converter circuit (13) for performing a conversion into the CMOS level after obtaining an intermediate signal (M.sub.3) which is a parallel signal. An intermediate signal (M.sub.4) is at the CMOS level and has a low frequency.
    Type: Grant
    Filed: February 14, 1995
    Date of Patent: December 26, 1995
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Masahiro Ueda, Yasushi Hayakawa
  • Patent number: 5463329
    Abstract: An input circuit which converts an input signal to an output signal. A first level comparator has a first input to which the input signal is applied and a second input to which a first reference voltage is applied for comparison with the input signal, and an output which the output signal is manifested. A second level comparator has a first input connected to the first input of the first level comparator for application one input signal, and a second input to which a second reference voltage is applied for comparison with the input signal, with the second level comparator limiting the voltage at the first input of the first level comparator to substantially the second reference voltage whenever the input signal exceeds the second reference voltage as determined by the second level comparator.
    Type: Grant
    Filed: April 8, 1994
    Date of Patent: October 31, 1995
    Assignee: Canon Kabushiki Kaisha
    Inventors: Somei Kawasaki, Masami Iseki
  • Patent number: 5450024
    Abstract: An ECL to CMOS signal converter circuit including built-in toggle-fault detection circuitry and method of conversion are provided in which an RF transformer is used to translate ECL level digital signals to CMOS level signals. A diode biasing circuit shifts the average DC level of the CMOS level signals in a positive direction to avoid signal undershoot. An AC peak detection circuit is connected to the inactive leg of the RF transformer to monitor toggling of the ECL level input signal lines. A DC comparator circuit compares the detected peak voltage with a predetermined threshold voltage, and generates an alarm signal representing a toggle-fault whenever the detected peak voltage is lower than the predetermined threshold.
    Type: Grant
    Filed: January 19, 1994
    Date of Patent: September 12, 1995
    Assignee: Alcatel Network Systems, Inc.
    Inventor: Eugen H. Ruegg
  • Patent number: 5428312
    Abstract: A semiconductor integrated circuit device has a circuit construction which is devised with an output circuit for feeding an output current to an operating supply voltage in response to an output signal of a current switch circuit responding to an input signal. A constant current element for producing the operating current of the current switch circuit is fed with a constant voltage through a resistance element. A capacitor is coupled between the input of the constant current element and the operating supply voltage so that it constructs a time constant circuit together with the resistance element. The time constant circuit has a time constant set longer than the period of the output signal of the output circuit.
    Type: Grant
    Filed: May 7, 1993
    Date of Patent: June 27, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Keiichi Higeta, Satoru Isomura, Kazuhiro Akimoto
  • Patent number: 5424658
    Abstract: A level shifting circuit which can be implemented as part of a bipolar ECL integrated circuit, provides reliable switching and level shifted output suitable for driving a low voltage CMOS integrated circuit. The circuit includes a level shifting circuit which is connected to trigger a high gain positive feedback bootstrap circuit to reliably ensure switching even under poor signal conditions. An output taken from one of the switched pair is allowed to go to V.sub.CC, 0 volts, or is clamped by a clamping circuit to -3.3 volts, representing the two output states suitable for driving inverted rail CMOS circuitry.
    Type: Grant
    Filed: December 10, 1993
    Date of Patent: June 13, 1995
    Assignee: Cray Research, Inc.
    Inventors: Mark R. Sikkink, Terrance L. Bowman