Abstract: A signal output circuit is disclosed that supplies a signal from a first circuit that is driven based on a first reference voltage to a second circuit that is driven based on a second reference voltage. The signal output circuit includes a first control circuit that draws a current to the first reference voltage according to an output signal from the first circuit and supplies a signal to the second circuit according to the drawn current, and a second control circuit that draws a current from the second circuit to the second reference voltage.

Abstract: A display control device includes a controller, a scaling engine, a timing controller, a selector and an interface circuit. The controller is for providing a mode-control signal. The scaling engine is for producing a first interface signal. The timing controller is for converting the first interface signal into a second interface signal. The selector selects either the first interface signal or the second interface signal to serve as a reference signal according to the mode-control signal. The interface circuit converts the reference signal into an output signal according to the mode-control signal. When the mode-control signal is under a first mode, the output signal is virtually the first interface signal. When the mode-control signal is under a second mode, the output signal is virtually the second interface signal. When the mode-control signal is under a third mode, the interface circuit converts the first interface signal into a third interface signal to serve as the output signal.

Abstract: A voltage level conversion circuit for converting a voltage level of a low voltage system input signal into a voltage level of a high voltage system signal comprises a latch circuit comprising plural high-breakdown-voltage MOS transistors having a high power supply voltage as a breakdown voltage, a first high-breakdown-voltage N channel MOS transistor which discharges one of the latch nodes of the latch circuit, and a second high-breakdown-voltage N channel MOS transistor which discharges the other latch node, and a pulse signal obtained by boosting a low voltage system pulse signal is applied to a gate of the first or second high-breakdown voltage N channel MOS transistor when the input signal transits.

Abstract: A semiconductor integrated circuit device includes a level-shifting circuit, a current mirror circuit and a switch circuit. The level-shifting circuit level-shifts an input signal having a first amplitude to an output signal having a second amplitude. The current mirror circuit charges or discharges an output node of the level-shifting circuit. The switch circuit operates the current mirror circuit during a period from the inversion of the input signal to the inversion of the output signal.

Abstract: An ultra high speed Emitter Coupled Logic (ECL) flip-flop is provided and a method of operating the same. The ECL flip-flop provides for clock levels that operate at logic levels above the data levels. Since the clock operates at logic levels above the data, the clock experiences level shifts that are less than the level shifts of the data. Therefore, the clock will provide a higher fidelity signal relative to the conventional clock signal. The ECL flip-flop can operate at significantly higher data rates than conventional flip-flop circuitry.

Abstract: An improved ECL circuit, based upon an ECL circuit of conventional design, functions as the required transceiver for the bi-directional data transmission between a computer and an electronic device with a specific interface of USB 2.0. The value of an emitter resistor within an emitter resistance network in the conventional ECL circuit is adjusted till its output voltage amplitude meets the USB 2.0 specification. A number of voltage level shifting and capacitive coupling circuits are added to both the input and output sections of the conventional ECL circuit making it directly interfaceable with the popular CMOS logic family. A collector electrode switch network is also added to the conventional ECL circuit to make its output terminals tri-statable thus compatible with the communication scheme of half duplexing under the USB 2.0 specification.

Abstract: An interface circuit from Common Mode Logic to a low voltage, fixed common mode output, with high current drive. The CML signal is received, and then re-referenced to a low-voltage band-gap supply. The circuit is arranged to provide an output data signal referenced to a second positive reference voltage supply responsive to receipt of a common mode input data signal referenced to a first positive reference voltage supply. The circuit avoids use of vertical PNP transistors in the signal path.

Abstract: A transistor output circuit featuring a low power consumption, high speed and stabilized operation is realized.

Abstract: An integrated circuit device in which the magnitude of the output voltage swings of outputs in a circuit having emitter coupled output transistors is programmable includes a variable bias generator that produces a bias voltage. The bias voltage is connected to the base of a current source transistor in order to program the magnitude of the output voltage swings. An electrical connection area of the integrated circuit device is connected to the bias voltage generator. An external programming circuit can be connected to the electrical connection area in order to set the bias voltage, to thereby program the desired magnitude of the output voltage swings. The external programming circuit typically can be a resistance or an external voltage source.

Abstract: An integrated circuit device having emitter follower outputs with adjustable output currents includes a variable bias generator that produces a bias voltage. The bias voltage is connected to the bases of current source transistors in order to program the output currents. The variable bias generator is connected to an electrical connection area of the integrated circuit device. An external programming circuit can be connected to the electrical connection area in order to set the bias voltage, to thereby program the desired amount of current in the output current sources. The external programming circuit typically can be a resistance or an external voltage source. The variable bias generator can be any of a number of circuits that produce a bias voltage that is dependent upon the external programming circuit connected to the electrical connection area.

Abstract: A level converter circuit includes a differential amplifier 20 having a load resistor 8 supplied at its one end with a voltage which is stabilized against the variation of a power voltage by an emitter-follower transistor 4 receiving at its base a bias voltage from a bias circuit 9, 12-14. An intermediate signal is derived from the other end of the load resistor and supplied to a level shift circuit 25.

Abstract: A translator in an element of a wideband network transforms a format restored by a CCITT information cell into other predetermined formats. It performs this function by inserting cells from a microprocessor into network data flow in asynchronous transfer mode (ATM) and extracting from the network data flow cells addressed to the microprocessor. The translator includes an input portion for receiving input data cells from the network data flow and for modifying a header of cells in the input data so as to adapt them to perform functions in the ATM layer. Preferably, the translator is implemented as an integrated circuit which serves as an interface between the network and the microprocessor, and which configures and manages asynchronous transfer mode multiplexer functions.

Abstract: A drive transistor has its base coupled to a circuit input and its collector coupled to provide an output current at a circuit output. The output current is responsive to a base current received at the base of the drive transistor. A voltage induced across a resistor connected between the circuit input and the base of the drive transistor indicates the amount of drive transistor base current. A portion of an input current presented at the circuit input is diverted to the circuit output based on the indicated amount of drive transistor base current. The remaining portion of the input current is provided as the drive transistor base current. The drive transistor is thus prevented from saturating.

Abstract: A semiconductor integrated circuit device has a first ground to which a first circuit is connected and whose level is fluctuate due to noise and a second ground to which a second circuit, which provides an output to the first circuit, is connected and whose level is stable. The semiconductor integrated circuit device includes a fluctuation detecting unit for detecting a fluctuation in the level of the first ground according to the level of the second ground serving as a reference; and a level controlling unit for controlling the level of the output of the second circuit, to cancel the fluctuation detected by the fluctuation detecting unit. The semiconductor integrated circuit device detects a fluctuation in the level of the first ground, which is easily affected by noise, according to the level of the second ground, which is stable, and controls the level of the output of the second circuit, to cancel the detected fluctuation.

Abstract: A translator circuit (21) converts an ECL logic level to a TTL logic level. The translator circuit (21) operates at high speeds, rejects power supply noise, and does not use Schottky diodes for preventing transistors from saturating. The translator circuit comprises a differential input stage (22), a level shift stage (23), a differential stage (24), and an output stage (25). The differential input stage (22) is responsive to an ECL signal and provides a differential output signal. The level shift stage (23) level shifts the differential output signal of the differential input stage a predetermined DC voltage. The differential stage (24) is responsive to the level shift stage (23) and generates first and second output signals. The differential stage (24) rejects power supply noise coupled from the level shift stage (23).

Abstract: Switching between two logic circuits that produce outputs at different respective logic levels is accomplished by means of a common input differential switch that has a branch in each logic circuit. A common current source supplies current to the branches within each logic circuit. The current source remains on regardless of which logic level is selected, thereby enhancing switching speed. The logic circuits produce logic outputs at a common output differential switch, which in turn provides a selected output to a single output terminal. The logic circuits are configured so that the output from the circuit corresponding to the selected logic level dominates the output from the other logic circuit at the output differential switch.