Having Plural Output Pull-up Or Pull-down Transistors Patents (Class 326/87)
  • Patent number: 11251756
    Abstract: A reconfigurable power detector is described. The reconfigurable power detector includes a first power detector circuit. The first power detector circuit includes a pair of coupled first-type transistors to switch a first-type positive output and a first-type negative output. The reconfigurable power detector includes a second power detector circuit. The second power detector circuit includes a pair of coupled second-type transistors to switch a second-type positive output and a second-type negative output. The reconfigurable power detector includes a switch matrix. The switch matrix includes switches to select the second-type positive output and the second-type negative output in a first configuration, the first-type positive output and the first-type negative output in a second configuration, and the first-type positive output and the second-type positive output in a third configuration.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: February 15, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Lai Kan Leung, Aleksandar Miodrag Tasic
  • Patent number: 11190172
    Abstract: Examples described herein generally relate to integrated circuits that include a latch-based level shifter circuit with self-biasing. In an example, an integrated circuit includes first and second latches and an output stage circuit. Each of the first and second latches includes a bias circuit electrically connected to a respective latch node and configured to provide a bias voltage at the respective latch node, which is electrically coupled to a signal input node. The output stage circuit has first and second input nodes electrically connected to first and second output nodes of the first and second latches, respectively, and a third output node. The output stage circuit is configured to responsively pull up and pull down a voltage of the third output node in response to respective voltages of the first and second input nodes.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: November 30, 2021
    Assignee: XILINX, INC.
    Inventors: Mayank Raj, Parag Upadhyaya
  • Patent number: 11158359
    Abstract: A storage device includes a nonvolatile memory device, and a controller that exchanges a data signal with the nonvolatile memory device through a data input and output line and exchanges a data strobe signal with the nonvolatile memory device through a data strobe line. In a training operation, at least one of the nonvolatile memory device and the controller performs a coarse training of adjusting a delay of the data signal with a first stride and a fine training of adjusting the delay of the data signal with a second stride smaller than the first stride.
    Type: Grant
    Filed: February 18, 2021
    Date of Patent: October 26, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyungjin Kim, Soong-Man Shin
  • Patent number: 10984709
    Abstract: A display panel has a display area and a peripheral area disposed adjacent to the display area. The display panel includes a pixel array, a plurality of gate lines, a plurality of first wirings, and a first gate driving circuit. The pixel array is disposed in the display area. The gate lines are coupled to the pixel array. The plurality of first wirings are coupled to the pixel array. The first gate driving circuit is disposed in the peripheral area and coupled to the pixel array via at least a portion of the plurality of first wirings and at least a portion of the plurality of gate lines. In the display area, the plurality of gate lines extend along a first direction and the plurality of first wirings extend along a second direction, and the first direction and the second direction are different.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: April 20, 2021
    Assignee: INNOLUX CORPORATION
    Inventors: Min-Hsin Lo, Kung-Chen Kuo, Hung-Sheng Liao, Yi-Hua Hsu
  • Patent number: 10892747
    Abstract: Circuits, methods, and systems are provided for setting a current level to be used by a current-mode gate driver. The current level may be used to source, sink, or both source and sink current to/from the gate terminal of a power device. The current level is based upon a current or voltage level input from an analog current-setting terminal. This input current or voltage level may take a value from a continuous range of current or voltage values.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: January 12, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Giuseppe Bernacchia, Adriano Sambucco
  • Patent number: 10826480
    Abstract: An integrated circuit includes a gate driver circuit that controls high side and low side transistors to operate in buck or boost mode. In buck operating mode, after switching off the low side transistor, the gate driver circuit controls the high side transistor in a constant current mode. After the low side transistor is disabled and no longer conducts current, then the gate driver circuit controls the high side transistor to operate in full-enhancement mode. In boost operating mode, after switching off the high side transistor, the gate driver circuit controls the low side transistor in a constant current mode. After the high side transistor is disabled, then the gate driver circuit controls the low side switching transistor to operate in full-enhancement mode. In both buck and boost operation, the gate driver circuit operates without dead time in which both the high side and low side transistors are off.
    Type: Grant
    Filed: July 1, 2017
    Date of Patent: November 3, 2020
    Assignee: Active-Semi, Inc.
    Inventors: Thinh Ba Nguyen, Thien Khanh Luong, Thuc Huu Lam, Hue Khac Trinh
  • Patent number: 10804901
    Abstract: A signal transfer circuit for receiving a first signal to transfer the received first signal as a second signal by using an operating power source having a second voltage level, the signal transfer circuit may include: a first setting circuit; and a second setting circuit, the first signal may swing between a first voltage level and a ground level, and the second signal may swing between a third voltage level and the ground level, the first setting circuit may be configured to set the third voltage level to be same as the second voltage level, when the first voltage level is higher than the second voltage level, and the second setting circuit may be configured to set the third voltage level to be same as the first voltage level, by detecting when the first voltage level is lower than or equal to the second voltage level.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: October 13, 2020
    Assignee: SK hynix Inc.
    Inventor: Hee-Jun Kim
  • Patent number: 10790812
    Abstract: An integrated circuit includes a gate driver circuit that controls high side and low side transistors to operate in buck or boost mode. In buck operating mode, after switching off the low side transistor, the gate driver circuit controls the high side transistor in a constant current mode. After the low side transistor is disabled and no longer conducts current, then the gate driver circuit controls the high side transistor to operate in full-enhancement mode. In boost operating mode, after switching off the high side transistor, the gate driver circuit controls the low side transistor in a constant current mode. After the high side transistor is disabled, then the gate driver circuit controls the low side switching transistor to operate in full-enhancement mode. In both buck and boost operation, the gate driver circuit operates without dead time in which both the high side and low side transistors are off.
    Type: Grant
    Filed: July 1, 2017
    Date of Patent: September 29, 2020
    Assignee: Active-Semi, Inc.
    Inventors: Thinh Ba Nguyen, Thien Khanh Luong, Thuc Huu Lam, Hue Khac Trinh
  • Patent number: 10622984
    Abstract: A radio frequency switching circuit includes a switching circuit comprising a plurality of switching transistors connected between a first terminal and a second terminal, a gate resistor circuit comprising a plurality of gate resistors, each of the plurality of gate resistors having a first node connected to a respective gate of each of the plurality of switching transistors, and a gate buffer circuit comprising a plurality of gate buffers, each of the plurality of gate buffers being connected to a respective second node of each of the plurality of gate resistors, wherein each of the plurality the gate buffers is configured to provide a first gate signal to the gate of each of the plurality of switching transistors through each of the plurality of gate resistors.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: April 14, 2020
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Byeong Hak Jo, Hyun Paek, Jeong Hoon Kim
  • Patent number: 10382041
    Abstract: A buffer circuit may include an input unit coupled among first and second output nodes and a common node. The input unit may be configured to change voltage levels of first and second output nodes based on an input signal. The buffer circuit may generate an output signal swinging between a voltage and a first voltage in a first operation mode, and may generate an output signal swinging between the voltage and a second voltage having a different level from the first voltage in a second operation mode.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: August 13, 2019
    Assignee: SK hynix Inc.
    Inventor: Gi Moon Hong
  • Patent number: 10235309
    Abstract: A method, having steps of monitoring a bus for a change in an aggregated ready/busy indicator from a busy status to a ready status, the change in the aggregated ready/busy indicator to the ready status indicating at least one die is ready to perform a computer function, scheduling at least one logic queue with a next command to the ready die when the aggregated ready/busy indicator is in a ready status and setting the aggregated ready/busy indicator to a busy status after the scheduling of the at least one logic queue.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: March 19, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Yoav Markus, Alexander Bazarsky
  • Patent number: 10230359
    Abstract: According to a first aspect of the present inventive concept there is provided an equalizer system comprising a decision feedback equalizer (DFE), the DFE comprising: a static comparator configured as a decision device of the DFE; and a feedback path comprising a set of filter taps including at least a first filter tap; wherein the static comparator presents hysteresis and wherein a tap coefficient of the first filter tap is set such that an input signal level of the static comparator is shifted to compensate for the hysteresis.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: March 12, 2019
    Assignee: IMEC VZW
    Inventors: Oscar Elisio Mattia, Davide Guermandi
  • Patent number: 10224918
    Abstract: A device is described that includes a gate driver configured to output, to a gate of a switch, a turn-on voltage for activating the switch in response to receiving an indication to activate the switch and an active gate bias driver configured to actively drive a voltage at the gate of the switch to a bias voltage in response to receiving an indication to deactivate the switch. The bias voltage is less than the turn-on voltage and wherein the bias voltage is greater than a ground voltage of the gate driver.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: March 5, 2019
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Rajeev-Krishna Vytla, Danish Khatri, Min Fang
  • Patent number: 10079603
    Abstract: A driver circuit for an integrated circuit (IC) is configurable to operate in three different signaling modes, namely, differential signaling mode, single-ended current mode, and single-ended voltage mode. The driver circuit receives first and second input signals from a pre-driver and outputs first and second output signals that conform with the selected one of the three signaling modes.
    Type: Grant
    Filed: April 8, 2018
    Date of Patent: September 18, 2018
    Assignee: NXP B.V.
    Inventor: Chinmayee Kumari Panigrahi
  • Patent number: 9948508
    Abstract: A method for changing an operating mode of a processing unit of a network node is described. The processing unit is connected to a communication and supply line for providing data communication and for providing a supply voltage. The method includes an establishing of a communication connection of the processing unit of the network node via the communication and supply line, a determination of a change of the supply voltage of the communication and supply line by the processing unit, and a setting of an operation mode of the processing unit based on the determined change of the supply voltage.
    Type: Grant
    Filed: June 24, 2014
    Date of Patent: April 17, 2018
    Assignee: Airbus Operations GmbH
    Inventors: Peter Klose, Oliver Hanka
  • Patent number: 9729149
    Abstract: A low-power storage device is provided. The storage device includes a first transistor, a second transistor, a logic element, and a semiconductor element. The second transistor controls supply of a first signal to a gate of the first transistor. When the potential of a second signal to be input is changed from a first potential into a second potential lower than the first potential, the logic element changes the potential of a first terminal of the first transistor from a third potential lower than the second potential into the first potential after the logic element changes the potential of the first terminal of the first transistor from the second potential into the third potential. The semiconductor element has a function of making a second terminal of the first transistor floating. The first transistor includes a channel formation region in an oxide semiconductor film.
    Type: Grant
    Filed: April 14, 2014
    Date of Patent: August 8, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Takayuki Ikeda
  • Patent number: 9660631
    Abstract: A duty cycle detection circuit may include: a timing signal generation unit to generate a plurality of timing signal groups by selectively combining multi-phase clock signals according to an enable signal; and a detection unit to generate a duty detection signal by selectively combining signals of the plurality of timing signal groups according to the enable signal.
    Type: Grant
    Filed: February 19, 2015
    Date of Patent: May 23, 2017
    Assignee: SK hynix Inc.
    Inventors: Young Suk Seo, Da In Im
  • Patent number: 9621138
    Abstract: An apparatus includes a swing control circuit, a slew control circuit, and a driver circuit. The swing control circuit is configured and arranged to be powered by an input supply voltage, to receive an input data signal and, in response, to generate a first internal signal having a swing level corresponding to the input supply voltage. The slew control circuit, including a switched capacitor circuit, is configured and arranged to receive the first internal signal and, in response, to generate a second internal signal using the switched capacitor circuit that is configured to set a slew rate for the second internal signal. Further, the driver circuit is configured and arranged to receive the second internal signal and, in response, to generate an output signal that is based upon the swing level and the slew rate of the second internal signal.
    Type: Grant
    Filed: November 5, 2015
    Date of Patent: April 11, 2017
    Assignee: NXP B.V.
    Inventors: Xu Zhang, Siamak Delshadpour, Ahmad Yazdi
  • Patent number: 9553587
    Abstract: A data output circuit of a semiconductor apparatus includes a pull-up driver including a first plurality of leg units commonly electrically coupled to a data output pad and configured to pull up the data output pad in response to a first code signals, a pull-down driver including a second plurality of leg units commonly electrically coupled to the data output pad and configured to pull down the data output pad to a second code signals, and a code generator configured to generate the first and second code signals. The code generator generates the second code signals by comparing a replica voltage to a reference voltage.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: January 24, 2017
    Assignee: SK HYNIX INC.
    Inventor: Hae Kang Jung
  • Patent number: 9423815
    Abstract: A semiconductor device and a highly reliable circuit are realized using the transistors having a lower withstand voltage. There are provided a differential pair including a first and a second transistor which respectively receive input signals having mutually reversed phases; a third and a fourth transistor respectively cascode-coupled to the first and the second transistor, and having the same conductivity type as the first and the second transistor; a first and a second output terminal coupled to respective drains of the third and the fourth transistor; and a voltage divider circuit which divides an intermediate potential between respective potentials of the first and the second output terminal and supplies the divided potential to gates of the third and the fourth transistor.
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: August 23, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Masafumi Mitsuishi, Masayasu Komyo, Souji Sunairi
  • Patent number: 9263431
    Abstract: In certain examples an integrated circuit protection circuit can include a circuit module, and an isolation device. The isolation device can be configured to couple a ground node of the circuit module to a power ground in an on state, and to isolate the ground node of the circuit module from the power ground in an off state, wherein the isolation module is configured to enter the off state when the IC receives a negative input voltage.
    Type: Grant
    Filed: April 12, 2013
    Date of Patent: February 16, 2016
    Assignee: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventors: Sam Zheng, Gary Sun, Steven M. Leibiger, Tyler Daigle, Julie Lynn Stultz
  • Patent number: 9224566
    Abstract: Fuse driver circuits, fuse driver testing circuitry, and methods for testing the fuse driver circuits using the testing circuitry are described. In some embodiments, the fuse driver circuit can be made using a fuse, a NMOS transistor, and a PMOS transistor. The drain of the NMOS transistor can be connected to the negative end of the fuse. The source of the NMOS transistor can be connected to ground. The drain of the PMOS transistor can be connected to a positive end of the fuse. The NMOS and PMOS transistors provide enhanced robustness to the fuse driver circuit in both undervoltage and overvoltage conditions. Other embodiments are also described.
    Type: Grant
    Filed: December 10, 2010
    Date of Patent: December 29, 2015
    Assignee: Fairchild Semiconductor Coporation
    Inventors: Kenneth P. Snowdon, William Robert Newberry, James Hall, Roy Yarbrough
  • Patent number: 9210011
    Abstract: A transmitter, such as a voltage mode driver (VMD)-based push-pull source-series terminated (SST) transmitter, is provided that can consume less current as the amplitude of a voltage output is decreased. The transmitter includes a transmitter circuit having a first branch and a second branch. While the first branch is activated to send an analog output signal, the second branch is deactivated, and vice versa. One or more bit values of an input binary signal can be used to selectively activate and deactivate the first and second branches.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: December 8, 2015
    Assignee: Intel Corporation
    Inventors: Giacomo Rinaldi, Stefano Giaconi
  • Patent number: 9160952
    Abstract: The present invention discloses a device of CMOS image sensor, exactly, relates to a kind of CMOS charge pump circuit. The invention compromises: two current mirrors and two operational amplifiers are added into the CMOS charge pump circuit. The feed-through current is suppressed when signal switches in the said circuit. It solved the problem of the big voltage jump of the output voltage when the logic signal switches. It guarantees the stabilities of the circuit and the output voltage.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: October 13, 2015
    Assignee: Shanghai Huali Microelectronics Corporation
    Inventors: Ning Zhang, Benyan Wang
  • Patent number: 9099036
    Abstract: An active-matrix-type light-emitting device includes: a pixel circuit including a light-emitting element, a driving transistor that drives the light-emitting element, a holding capacitor whose one end is connected to the driving transistor and which stores electric charges corresponding to written data, at least a control transistor that controls an operation associated with writing of data into the holding capacitor, and an emission control transistor; a first scanning line for controlling ON/OFF of the control transistor and a second scanning line for controlling ON/OFF of the emission control transistor; a data line through which the written data is transmitted to the pixel circuit; and a scanning line driving circuit which drives the first and second scanning lines and in which a current drive capability associated with the second scanning line is set to be lower than a current drive capability associated with the first scanning line.
    Type: Grant
    Filed: July 11, 2007
    Date of Patent: August 4, 2015
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Takayuki Kitazawa
  • Patent number: 9070546
    Abstract: Provided is a semiconductor device in which change in characteristics of a transistor is suppressed and an output signal is changed sharply without increasing W/L of the transistor can be provided. Two transistors are connected in parallel between a wiring to which a low potential is supplied and an output terminal. When the low potential is output from the output terminal, both of the two transistors are turned on and then one of them is turned off. Thus, change in characteristics of the transistor can be suppressed and an output signal can be changed sharply without increasing W/L of the transistor.
    Type: Grant
    Filed: August 16, 2013
    Date of Patent: June 30, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Atsushi Umezaki
  • Patent number: 9048941
    Abstract: Techniques for extracting the characteristic response of a non-linear channel are presented. In various implementations of the invention, a channel's characteristic response may be determined by identifying a first input sequence, determining the ones compliment of the first input sequence and then determining the response of the channel to these two input sequences. Subsequently, two input matrices and two response matrices may be generated based upon the two input sequences and their corresponding responses. Given these four matrices, a symmetrical response component may be determined by iteratively solving a system of equations formed from the columns of each matrix. Subsequently, given the symmetric component and these four matrices, an asymmetrical response component may be determined by again iteratively solving the system of equations for the columns of each matrix.
    Type: Grant
    Filed: January 24, 2011
    Date of Patent: June 2, 2015
    Assignee: Mentor Graphics Corporation
    Inventor: Vladimir B. Dmitriev-Zdorov
  • Patent number: 9030229
    Abstract: An impedance tuning circuit includes a calibration unit and a post-processing unit. The calibration unit generates an initial pull-up code and an initial pull-down code by performing a calibration operation using an external resistor during an initial impedance tuning operation. The post-processing unit outputs the initial pull-up code and the initial pull-down code as a final pull-up code and a final pull-down code during the initial impedance tuning operation, and generates the final pull-up code and the final pull-down code by using the initial pull-up code and the initial pull-down code during a subsequent impedance tuning operation.
    Type: Grant
    Filed: October 25, 2012
    Date of Patent: May 12, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Kyung Hoi Koo
  • Patent number: 9018973
    Abstract: A device, comprising an output terminal; an output circuit coupled to the output terminal and having an adjustable impedance; and an impedance adjustment circuit adjusting stepwise the adjustable impedance so as to head toward a first reference impedance. The impedance adjustment circuit changes the adjustable impedance by a first amount when the adjustable impedance is within a first range, and changes the adjustable impedance by a second amount when the adjustable impedance is out of the first range. The first amount is smaller than the second amount.
    Type: Grant
    Filed: October 4, 2012
    Date of Patent: April 28, 2015
    Assignee: PS4 Luxco S.A.R.L.
    Inventors: Nakaba Kaiwa, Yutaka Ikeda
  • Patent number: 9000803
    Abstract: A high-speed signaling system with adaptive transmit pre-emphasis. A transmit circuit has a plurality of output drivers to output a first signal onto a signal path. A receive circuit is coupled to receive the first signal via the signal path and configured to generate an indication of whether the first signal exceeds a threshold level. A first threshold control circuit is coupled to receive the indication from the receive circuit and configured to adjust the threshold level according to whether the first signal exceeds the threshold level. A drive strength control circuit is coupled to receive the indication from the receive circuit and configured to adjust a drive strength of at least one output driver of the plurality of output drivers according to whether the first signal exceeds the threshold level.
    Type: Grant
    Filed: June 7, 2013
    Date of Patent: April 7, 2015
    Assignee: Rambus Inc.
    Inventors: Vladimir M. Stojanovic, Andrew C. Ho, Anthony Bessios, Fred F. Chen, Elad Alon, Mark A. Horowitz
  • Patent number: 8994403
    Abstract: Apparatus and methods related to data transmission are disclosed. One such apparatus includes a transmitter, a receiver, and a channel. The transmitter includes a pair of current sources and a pair of switches. Each of the switches conducts one of the current sources to the channel in response to input data. The receiver includes a first node configured to receive a signal over the channel. The receiver also includes a resistance generating a voltage drop between the first node and a second node. The receiver further includes a first transistor and a second transistor that are together configured to provide a voltage level to the second node based at least partly on the voltage drop. The resistance provides a negative feedback to center the mean signal level, thereby reducing intersymbol interference.
    Type: Grant
    Filed: August 16, 2012
    Date of Patent: March 31, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Timothy M. Hollis
  • Patent number: 8988100
    Abstract: Described are amplifiers that facilitate high-speed communication with calibrated drive strength and termination impedance. Drivers and termination elements can be divided into a number N of parallel portions, one or more of which can be disabled and updated without interfering with signal (e.g., clock or data) transmission. Some embodiments identify inactive elements by examining incoming signals.
    Type: Grant
    Filed: August 6, 2012
    Date of Patent: March 24, 2015
    Assignee: Rambus Inc.
    Inventors: Huy M. Nguyen, Vijay Gadde, Sivakumar Doraiswamy
  • Patent number: 8981817
    Abstract: A circuit having a centralized PT compensation circuit to provide compensation signals to localized I/O blocks on the chip. Process variations and temperature variations tend to be approximately uniform across an integrated circuit chip. Thus, a single, centralized PT compensation circuit may be used instead of one PT compensation circuit per I/O section as with solutions of the past. Further, the PT compensation circuit may generate a digital code indicative of the effects of process and temperature. Further yet, each section of I/O block may have a local voltage compensation circuit to compensate the voltage variation of the I/O block. The voltage compensation circuit utilizes an independent reference voltage. The reference voltage is generated by the PT compensation circuit, which is placed centrally in the IC chip and hence any need to repeat the reference generation for each I/O block is eliminated.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: March 17, 2015
    Assignees: STMicroelectronics International N.V., STMicroelectronics (Crolles 2) SAS
    Inventors: Vinod Kumar, Pradeep Kumar Badrathwal, Saiyid Mohammad Irshad Rizvi, Paras Garg, Kallol Chatterjee, Pierre Dautriche
  • Patent number: 8963577
    Abstract: A termination impedance apparatus includes a variable pull-up resistor, a variable pull-down resistor, and a small-signal calibration circuit. The variable pull-up resistor is coupled between a first power supply voltage terminal and an output terminal. The variable pull-down resistor is coupled between the output terminal and a second power supply voltage terminal. The small-signal calibration circuit is for calibrating the variable pull-up resistor and the variable pull-down resistor to achieve a desired small-signal impedance.
    Type: Grant
    Filed: April 24, 2013
    Date of Patent: February 24, 2015
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Warren R. Anderson, Shyam S. Sivakumar, Austen J. Hypher
  • Patent number: 8952725
    Abstract: A low voltage differential signal driving circuit including positive and negative differential output terminals, an automatic level selector, an output level detector and a transition accelerator. The positive and negative differential output terminals provide a transmission interface with a differential output signal for transmission of a data signal. The automatic level selector outputs a reference voltage corresponding to the transmission interface. The output level detector generates a low-high (or high-low) transition acceleration control signal based on the data signal, the reference voltage, and VTXP signal at the positive differential output terminal (or VTXN signal at the negative differential output terminal).
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: February 10, 2015
    Assignee: Via Technologies, Inc.
    Inventors: Yeong-Sheng Lee, Kuen-Chir Wang
  • Patent number: 8952719
    Abstract: Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including first and second transmitter-receivers that execute transmission and reception of data through a signal line. The first transmitter-receiver includes a first termination circuit that includes a first resistor and a first switch, the first resistor being provided between a first power supply terminal and the signal line, the first switch controlling a current flowing through the first resistor to be turned on and off, and a control circuit that outputs a first control signal to the first termination circuit so that the first switch is turned on when the first transmitter-receiver receives data, the first switch is turned off when the first transmitter-receiver transmits the data, and the first switch is continuously on during a first predetermined period after receiving the data when the first transmitter-receiver further receives another data after receiving the data.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: February 10, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Masayasu Komyo, Yoichi Iizuka
  • Patent number: 8941410
    Abstract: Buffer circuit embodiments are described. A buffer circuit includes an input configured to receive an input signal and a buffer configured to generate an output signal based on the input signal. In one embodiment, the buffer circuit includes a programmable chopping module coupled with the buffer, wherein the programmable chopping module is programmable with a selected configuration from a plurality of configurations, and wherein the programmable chopping modulates the input signal based on the selected configuration. In another embodiment, the buffer circuit further includes a programmable output filter coupled with the buffer, wherein the programmable output filter is programmable with a selected configuration form a plurality of configurations, and wherein the programmable output filter filters a frequency band of the output signal based on the selected configuration.
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: January 27, 2015
    Assignee: Cypress Semiconductor Corporation
    Inventors: Gajender Rohilla, Eashwar Thiagarajan, Harold Kutz, Monte Mar, Mohandas Palatholmana Sivadasan
  • Patent number: 8937490
    Abstract: An integrated circuit comprising an output driver including an output terminal, and a receiving circuit including a termination resistor connected between the output terminal and a ground. The output driver comprising a first NMOS transistor configured to pull up a voltage of the output terminal to a pull-up voltage in response to a pull-up signal, and a second NMOS transistor configured to pull down the output terminal to a ground voltage in response to a pull-down signal.
    Type: Grant
    Filed: October 24, 2012
    Date of Patent: January 20, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: David Moon, Yong Cheol Bae, Min Su Ahn, Young Jin Jeon
  • Patent number: 8933729
    Abstract: Differential receivers are “stacked” and independently calibrated to different common-mode voltages. The different common-mode voltages may correspond to the common-mode voltages of stacked transmission circuits. Multiple stacks of samplers are connected to the same channels. The clocking of each stack of sampler circuits is phased (timed) such that the samplers in a given stack are not resolving at the same time. Samplers in a different stack and receiving a different common-mode voltage resolve at the same time.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: January 13, 2015
    Assignee: Rambus Inc.
    Inventors: Xudong Shi, Reza Navid, Jason Chia-Jen Wei, Huy M. Nguyen, Kambiz Kaviani
  • Patent number: 8922240
    Abstract: A termination circuit includes: a pull-up termination unit configured to pull-up terminate an interface node in response to a pull-up signal; a pull-down termination unit configured to pull-down terminate the interface node in response to a pull-down signal; one or more pull-up resistors connected to the interface node and enabled to affect termination resistance in response to a pull-up setting value when a termination signal is activated; and one or more pull-down resistors connected to the interface node and enabled to affect termination resistance in response to a pull-down setting value when the termination signal is activated.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: December 30, 2014
    Assignee: SK Hynix Inc.
    Inventor: Seong-Hwi Song
  • Patent number: 8917131
    Abstract: Apparatus and methods may operate so that arrival times of a data signal at gates of transistors are controlled to switch the transistors at different times to modulate the slew rate of a signal on a node. Additional embodiments are also described.
    Type: Grant
    Filed: December 9, 2011
    Date of Patent: December 23, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Daesik Song
  • Patent number: 8912818
    Abstract: A calibration circuit includes an amplifier, a current steering digital-to-analog converter (DAC), a comparator, a slew calibration network, and an on-die termination (ODT) network. The amplifier generally has a first input, a second input, and an output. The first input generally receives a reference signal. The current steering digital-to-analog converter (DAC) generally has a first input coupled to the output of the amplifier, a first output coupled to the second input of the amplifier, and a second output coupled to a circuit node. The comparator generally has a first input receiving the reference signal, a second input coupled to the circuit node, and an output at which an output of the calibration circuit may be presented. The slew calibration network is generally coupled to the circuit node and configured to adjust a slew rate of the calibration circuit. The on-die termination (ODT) network is generally coupled to the circuit node.
    Type: Grant
    Filed: October 30, 2012
    Date of Patent: December 16, 2014
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Dharmesh Bhakta, Hong-Him Lim, Cheng-Gang Kong, Todd Randazzo
  • Patent number: 8907699
    Abstract: Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including a data transmitting circuit that transmits data in parallel through a plurality of signal lines and a data receiving circuit that receives the data. The data transmitting circuit includes a plurality of data output circuits that output the data in a data transmission mode or set an output to a high impedance state in a HiZ mode, a plurality of data selection circuits that select one of the data and fixed data and output the selected data to the data output circuits, and a control circuit that controls the data output circuits to output the fixed data during a period between a time when a mode is switched from the HiZ mode to the data transmission mode and a time when the data output circuits start to output the data.
    Type: Grant
    Filed: January 6, 2014
    Date of Patent: December 9, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Masayasu Komyo, Yoichi Iizuka
  • Patent number: 8896343
    Abstract: An adjustable impedance circuit includes a calibration module, an impedance module, a first switch module and a second switch module. The calibration module is arranged to generate a calibration signal. The impedance module has a plurality of impedance elements. The first switch module is coupled to the calibration module, and is arranged to receive the calibration signal and make a first portion of the impedance elements be selectively coupled between a differential input port and at least one reference voltage according to the calibration signal. The second switch module is coupled to a common-mode voltage output node, and is arranged to receive a control signal and make a second portion of the impedance elements be selectively coupled between the common-mode voltage output node and the differential input port according to the control signal.
    Type: Grant
    Filed: August 25, 2013
    Date of Patent: November 25, 2014
    Assignee: Realtek Semiconductor Corp.
    Inventor: Lifang Ge
  • Patent number: 8878565
    Abstract: Disclosed herein is a semiconductor device that includes a first transistor unit coupled to the data terminal, and a plurality of second transistor units coupled to the calibration terminal. The first transistor unit includes a plurality of first transistors having a first conductivity type connected in parallel to each other so that an impedance of the first transistor unit is adjustable. Each of the second transistor units includes a plurality of second transistors having the first conductivity type connected in parallel to each other so that an impedance of each of the second transistor units is adjustable. The semiconductor device further includes an impedance control circuit that reflects the impedance of each of the second transistor units to the first transistor unit.
    Type: Grant
    Filed: October 5, 2012
    Date of Patent: November 4, 2014
    Assignee: PS4 Luxco S.A.R.L
    Inventor: Kentaro Hara
  • Patent number: 8872540
    Abstract: A method of sharing in use an impedance matching circuit of a memory circuit to perform an initial calibration and a full time refresh mode calibration includes supplying power to the memory circuit, utilizing the impedance matching circuit to perform the initial calibration on the memory circuit, the memory circuit exiting the initial calibration, the memory circuit entering a driving mode, the memory circuit exiting the driving mode every a predetermined interval, utilizing the impedance matching circuit to perform the full time refresh mode calibration on the memory circuit according to a refresh command, an output voltage detection circuit determining a level of an output voltage of the memory circuit, and performing a corresponding operation according to a determination result generated by the output voltage detection circuit.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: October 28, 2014
    Assignee: Etron Technology, Inc.
    Inventors: Chun Shiah, Sen-Fu Hong, Wen-Wey Chen
  • Patent number: 8872541
    Abstract: An embodiment of the invention includes dynamically adjusting gain peaking of circuit logic such that error rates are acceptable across various process/voltage/temperature (PVT) ranges. An embodiment uses PVT dependant programming, such as but not limited to resistance compensation (RCOMP) codes, to control impedance compensation logic, such as but not limited to a Continuous Time Linear Equalization (CTLE) circuit. The PVT programming may be used to control gain peaking amplitude and gain peaking frequency across ranges of different PVTs. As a result, error performance is not impaired across different PVT corners and gain peaking is more consistent across different PVT corners. Other embodiments are included herein.
    Type: Grant
    Filed: January 21, 2013
    Date of Patent: October 28, 2014
    Assignee: Intel Corporation
    Inventor: Subratakumar Mandal
  • Patent number: 8868990
    Abstract: A semiconductor memory device is disclosed that includes an ODT circuit configured to be connected to a bus which transmits a data signal or a data strobe signal between a memory block and an input-output terminal; a first switch configured to be inserted into the bus between the memory block and the ODT circuit; a mode controller configured to switch off the first switch during a test of the memory block; and an oscillator configured to be connected to the ODT circuit, wherein a test signal is supplied to the ODT circuit from the oscillator during the test of the memory block.
    Type: Grant
    Filed: March 27, 2012
    Date of Patent: October 21, 2014
    Assignee: Fujitsu Limited
    Inventors: Rikizo Nakano, Osamu Ishibashi, Sadao Miyazaki
  • Patent number: 8860462
    Abstract: To provide a circuit used for a shift register or the like. The basic configuration includes first to fourth transistors and four wirings. The power supply potential VDD is supplied to the first wiring and the power supply potential VSS is supplied to the second wiring. A binary digital signal is supplied to each of the third wiring and the fourth wiring. An H level of the digital signal is equal to the power supply potential VDD, and an L level of the digital signal is equal to the power supply potential VSS. There are four combinations of the potentials of the third wiring and the fourth wiring. Each of the first transistor to the fourth transistor can be turned off by any combination of the potentials. That is, since there is no transistor that is constantly on, deterioration of the characteristics of the transistors can be suppressed.
    Type: Grant
    Filed: November 13, 2012
    Date of Patent: October 14, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Atsushi Umezaki
  • Patent number: RE45246
    Abstract: An on-die termination circuit is capable of increasing a resolution without enlargement of a chip or a layout size. The on-die termination circuit includes a control means, a termination resistance supply means, a code signal generating means. The control means sequentially generates a plurality of control signals in a response to a driving signal. The termination resistance supply means supplies a termination resistance in response to a coarse code signal having a plurality of bits and a fine code signal having a plurality of bits. The code signal generating means controls the fine code signal and the coarse code signal in response to the plurality of the control signals in order that the termination resistance has a level which is correspondent to an input resistance.
    Type: Grant
    Filed: December 6, 2012
    Date of Patent: November 18, 2014
    Assignee: Conversant IP N.B. 868 Inc.
    Inventor: Jung-Hoon Park