Abstract: A digital-to-analog converter (DAC)-based voltage-mode transmit driver architecture. One example transmit driver circuit generally includes an impedance control circuit coupled to a plurality of DAC driver slices. The impedance control circuit generally includes a tunable impedance configured to be adjusted to match a load impedance for the transmit driver circuit. Another example transmit driver circuit generally has an output impedance that is smaller than the load impedance for the transmit driver circuit, such that an output voltage swing at differential output nodes of the transmit driver circuit is greater than a voltage of a power supply rail. Another example transmit driver circuit generally includes a predriver circuit with a first inverter coupled to a first output of the predriver circuit and a second inverter coupled to a second output of the predriver circuit, the transistors in at least one of the first inverter or the second inverter having different strengths.

Abstract: A line driver includes a first resistive component, a second resistive component, an operational amplifier and an adjustable current mirror array circuit. A first terminal of the second resistive component and the first resistive component are coupled to a node, and a second terminal of the second resistive component is coupled to an output terminal. The operational amplifier receives a common mode voltage through the first resistive component, and generates a first signal and a second signal according to the common mode voltage and an input signal. The adjustable current mirror array circuit generates a first current to the node and a second current to the output terminal in response to the first and second signals, and adjusts a ratio of the second current to the first current in response to multiple control bits so as to set an output impedance of the output terminal.

Abstract: A method includes: selectively generating a first current by a first current generating circuit according to a first control signal; generating a second current by a second current generating circuit; and comparing a first input signal and a second input signal at a common node to generate an output signal according to the first current, the second current, and a second control signal. The second control signal and the first control signal are in-phase with each other.

Abstract: The systems and methods described herein consider a first channel width of transistors of driver circuitry, where the first channel width may be set to match a second channel width of a power control transistor. A control circuit, for example, may match a second channel width of a set of power control transistors to the first channel width by turning on one or more of the set of power control transistors. Matching the width of the switches of driver circuitry and the width of the set of power control transistors may reduce losses by helping to maintain impedances of the driver circuitry.

Abstract: A semiconductor device, includes: a first inverter that operates on a first supply voltage and includes a transistor with a first polarity and a transistor with a second polarity different from the first polarity; a first inverter array that is connected to a gate of the transistor with the first polarity, includes a predetermined plural number of inverters connected in series, and operates on the first supply voltage; and a second inverter array that is connected to a gate of the transistor with the second polarity and includes inverters of the predetermined plural number connected in series, wherein a first stage inverter in the second inverter array operates on a second supply voltage that is higher than the first supply voltage, and a subsequent stage inverter subsequent to the first stage inverter operates on the first supply voltage.

Abstract: A processing device in a memory sub-system determines whether to check a status of one or more memory dies of the memory device and sends a multi-unit status command to the memory device, the multi-unit status command specifying a plurality of memory units associated with the one or more memory dies of the memory device. The processing device further receives a response to the multi-unit status command, the response comprising a multi-bit value comprising a plurality of bits, wherein each bit of the plurality of bits represents a status of one or more parameters of a plurality of parameters for a corresponding one of the plurality of memory units.

Abstract: A voltage-controlled delay buffer includes a plurality of inverters configured in a cascade topology to receive an input signal from a source circuit and output an output signal to an output circuit. The plurality of inverters includes a voltage-controlled inverter controlled by a control signal having a first voltage and a second voltage. The voltage-controlled inverter includes a PMOS transistor configured to assist a low-to-high transition of an outgoing signal, and an NMOS transistor configured to assist a high-to-low transition of the outgoing signal. Two varactors, one forward connected and the other backward connected are configured to adjust a delay of a transition of an incoming signal. Another two varactors, one forward connected and the other backward connected, configured to adjust a delay of a transition of the outgoing signal in accordance with the first voltage and the second voltage.

Abstract: This invention provides a resistance-adjustable means using at a pull-up driver and/or a pull-down driver of an OCD circuit. When the resistance-adjustable means is applicable to the pull-up driver, the resistance-adjustable means includes a triode-mode PMOS coupled to a circuit of the pull-up driver and at least one of one or more adjustable resistors and/or a fixed resistor, which are connected in series and coupled to the triode-mode PMOS, and the at least one of the adjustable resistors or the fixed resistor is coupled to an IO (input/output) pad. When the resistance-adjustable means is applicable to the pull-down driver, a triode-mode NMOS is used to replace the triode-mode PMOS for the resistance-adjustable means.

Abstract: A reconfigurable power detector is described. The reconfigurable power detector includes a first power detector circuit. The first power detector circuit includes a pair of coupled first-type transistors to switch a first-type positive output and a first-type negative output. The reconfigurable power detector includes a second power detector circuit. The second power detector circuit includes a pair of coupled second-type transistors to switch a second-type positive output and a second-type negative output. The reconfigurable power detector includes a switch matrix. The switch matrix includes switches to select the second-type positive output and the second-type negative output in a first configuration, the first-type positive output and the first-type negative output in a second configuration, and the first-type positive output and the second-type positive output in a third configuration.

Abstract: Examples described herein generally relate to integrated circuits that include a latch-based level shifter circuit with self-biasing. In an example, an integrated circuit includes first and second latches and an output stage circuit. Each of the first and second latches includes a bias circuit electrically connected to a respective latch node and configured to provide a bias voltage at the respective latch node, which is electrically coupled to a signal input node. The output stage circuit has first and second input nodes electrically connected to first and second output nodes of the first and second latches, respectively, and a third output node. The output stage circuit is configured to responsively pull up and pull down a voltage of the third output node in response to respective voltages of the first and second input nodes.

Abstract: A storage device includes a nonvolatile memory device, and a controller that exchanges a data signal with the nonvolatile memory device through a data input and output line and exchanges a data strobe signal with the nonvolatile memory device through a data strobe line. In a training operation, at least one of the nonvolatile memory device and the controller performs a coarse training of adjusting a delay of the data signal with a first stride and a fine training of adjusting the delay of the data signal with a second stride smaller than the first stride.

Abstract: A display panel has a display area and a peripheral area disposed adjacent to the display area. The display panel includes a pixel array, a plurality of gate lines, a plurality of first wirings, and a first gate driving circuit. The pixel array is disposed in the display area. The gate lines are coupled to the pixel array. The plurality of first wirings are coupled to the pixel array. The first gate driving circuit is disposed in the peripheral area and coupled to the pixel array via at least a portion of the plurality of first wirings and at least a portion of the plurality of gate lines. In the display area, the plurality of gate lines extend along a first direction and the plurality of first wirings extend along a second direction, and the first direction and the second direction are different.

Abstract: Circuits, methods, and systems are provided for setting a current level to be used by a current-mode gate driver. The current level may be used to source, sink, or both source and sink current to/from the gate terminal of a power device. The current level is based upon a current or voltage level input from an analog current-setting terminal. This input current or voltage level may take a value from a continuous range of current or voltage values.

Abstract: An integrated circuit includes a gate driver circuit that controls high side and low side transistors to operate in buck or boost mode. In buck operating mode, after switching off the low side transistor, the gate driver circuit controls the high side transistor in a constant current mode. After the low side transistor is disabled and no longer conducts current, then the gate driver circuit controls the high side transistor to operate in full-enhancement mode. In boost operating mode, after switching off the high side transistor, the gate driver circuit controls the low side transistor in a constant current mode. After the high side transistor is disabled, then the gate driver circuit controls the low side switching transistor to operate in full-enhancement mode. In both buck and boost operation, the gate driver circuit operates without dead time in which both the high side and low side transistors are off.

Abstract: A signal transfer circuit for receiving a first signal to transfer the received first signal as a second signal by using an operating power source having a second voltage level, the signal transfer circuit may include: a first setting circuit; and a second setting circuit, the first signal may swing between a first voltage level and a ground level, and the second signal may swing between a third voltage level and the ground level, the first setting circuit may be configured to set the third voltage level to be same as the second voltage level, when the first voltage level is higher than the second voltage level, and the second setting circuit may be configured to set the third voltage level to be same as the first voltage level, by detecting when the first voltage level is lower than or equal to the second voltage level.

Abstract: An integrated circuit includes a gate driver circuit that controls high side and low side transistors to operate in buck or boost mode. In buck operating mode, after switching off the low side transistor, the gate driver circuit controls the high side transistor in a constant current mode. After the low side transistor is disabled and no longer conducts current, then the gate driver circuit controls the high side transistor to operate in full-enhancement mode. In boost operating mode, after switching off the high side transistor, the gate driver circuit controls the low side transistor in a constant current mode. After the high side transistor is disabled, then the gate driver circuit controls the low side switching transistor to operate in full-enhancement mode. In both buck and boost operation, the gate driver circuit operates without dead time in which both the high side and low side transistors are off.

Abstract: A radio frequency switching circuit includes a switching circuit comprising a plurality of switching transistors connected between a first terminal and a second terminal, a gate resistor circuit comprising a plurality of gate resistors, each of the plurality of gate resistors having a first node connected to a respective gate of each of the plurality of switching transistors, and a gate buffer circuit comprising a plurality of gate buffers, each of the plurality of gate buffers being connected to a respective second node of each of the plurality of gate resistors, wherein each of the plurality the gate buffers is configured to provide a first gate signal to the gate of each of the plurality of switching transistors through each of the plurality of gate resistors.

Abstract: A buffer circuit may include an input unit coupled among first and second output nodes and a common node. The input unit may be configured to change voltage levels of first and second output nodes based on an input signal. The buffer circuit may generate an output signal swinging between a voltage and a first voltage in a first operation mode, and may generate an output signal swinging between the voltage and a second voltage having a different level from the first voltage in a second operation mode.

Abstract: A method, having steps of monitoring a bus for a change in an aggregated ready/busy indicator from a busy status to a ready status, the change in the aggregated ready/busy indicator to the ready status indicating at least one die is ready to perform a computer function, scheduling at least one logic queue with a next command to the ready die when the aggregated ready/busy indicator is in a ready status and setting the aggregated ready/busy indicator to a busy status after the scheduling of the at least one logic queue.

Abstract: According to a first aspect of the present inventive concept there is provided an equalizer system comprising a decision feedback equalizer (DFE), the DFE comprising: a static comparator configured as a decision device of the DFE; and a feedback path comprising a set of filter taps including at least a first filter tap; wherein the static comparator presents hysteresis and wherein a tap coefficient of the first filter tap is set such that an input signal level of the static comparator is shifted to compensate for the hysteresis.

Abstract: A device is described that includes a gate driver configured to output, to a gate of a switch, a turn-on voltage for activating the switch in response to receiving an indication to activate the switch and an active gate bias driver configured to actively drive a voltage at the gate of the switch to a bias voltage in response to receiving an indication to deactivate the switch. The bias voltage is less than the turn-on voltage and wherein the bias voltage is greater than a ground voltage of the gate driver.

Abstract: A driver circuit for an integrated circuit (IC) is configurable to operate in three different signaling modes, namely, differential signaling mode, single-ended current mode, and single-ended voltage mode. The driver circuit receives first and second input signals from a pre-driver and outputs first and second output signals that conform with the selected one of the three signaling modes.

Abstract: A method for changing an operating mode of a processing unit of a network node is described. The processing unit is connected to a communication and supply line for providing data communication and for providing a supply voltage. The method includes an establishing of a communication connection of the processing unit of the network node via the communication and supply line, a determination of a change of the supply voltage of the communication and supply line by the processing unit, and a setting of an operation mode of the processing unit based on the determined change of the supply voltage.

Abstract: A low-power storage device is provided. The storage device includes a first transistor, a second transistor, a logic element, and a semiconductor element. The second transistor controls supply of a first signal to a gate of the first transistor. When the potential of a second signal to be input is changed from a first potential into a second potential lower than the first potential, the logic element changes the potential of a first terminal of the first transistor from a third potential lower than the second potential into the first potential after the logic element changes the potential of the first terminal of the first transistor from the second potential into the third potential. The semiconductor element has a function of making a second terminal of the first transistor floating. The first transistor includes a channel formation region in an oxide semiconductor film.

Abstract: A duty cycle detection circuit may include: a timing signal generation unit to generate a plurality of timing signal groups by selectively combining multi-phase clock signals according to an enable signal; and a detection unit to generate a duty detection signal by selectively combining signals of the plurality of timing signal groups according to the enable signal.

Abstract: An apparatus includes a swing control circuit, a slew control circuit, and a driver circuit. The swing control circuit is configured and arranged to be powered by an input supply voltage, to receive an input data signal and, in response, to generate a first internal signal having a swing level corresponding to the input supply voltage. The slew control circuit, including a switched capacitor circuit, is configured and arranged to receive the first internal signal and, in response, to generate a second internal signal using the switched capacitor circuit that is configured to set a slew rate for the second internal signal. Further, the driver circuit is configured and arranged to receive the second internal signal and, in response, to generate an output signal that is based upon the swing level and the slew rate of the second internal signal.

Abstract: A data output circuit of a semiconductor apparatus includes a pull-up driver including a first plurality of leg units commonly electrically coupled to a data output pad and configured to pull up the data output pad in response to a first code signals, a pull-down driver including a second plurality of leg units commonly electrically coupled to the data output pad and configured to pull down the data output pad to a second code signals, and a code generator configured to generate the first and second code signals. The code generator generates the second code signals by comparing a replica voltage to a reference voltage.

Abstract: A semiconductor device and a highly reliable circuit are realized using the transistors having a lower withstand voltage. There are provided a differential pair including a first and a second transistor which respectively receive input signals having mutually reversed phases; a third and a fourth transistor respectively cascode-coupled to the first and the second transistor, and having the same conductivity type as the first and the second transistor; a first and a second output terminal coupled to respective drains of the third and the fourth transistor; and a voltage divider circuit which divides an intermediate potential between respective potentials of the first and the second output terminal and supplies the divided potential to gates of the third and the fourth transistor.

Abstract: In certain examples an integrated circuit protection circuit can include a circuit module, and an isolation device. The isolation device can be configured to couple a ground node of the circuit module to a power ground in an on state, and to isolate the ground node of the circuit module from the power ground in an off state, wherein the isolation module is configured to enter the off state when the IC receives a negative input voltage.

Abstract: Fuse driver circuits, fuse driver testing circuitry, and methods for testing the fuse driver circuits using the testing circuitry are described. In some embodiments, the fuse driver circuit can be made using a fuse, a NMOS transistor, and a PMOS transistor. The drain of the NMOS transistor can be connected to the negative end of the fuse. The source of the NMOS transistor can be connected to ground. The drain of the PMOS transistor can be connected to a positive end of the fuse. The NMOS and PMOS transistors provide enhanced robustness to the fuse driver circuit in both undervoltage and overvoltage conditions. Other embodiments are also described.

Abstract: A transmitter, such as a voltage mode driver (VMD)-based push-pull source-series terminated (SST) transmitter, is provided that can consume less current as the amplitude of a voltage output is decreased. The transmitter includes a transmitter circuit having a first branch and a second branch. While the first branch is activated to send an analog output signal, the second branch is deactivated, and vice versa. One or more bit values of an input binary signal can be used to selectively activate and deactivate the first and second branches.

Abstract: The present invention discloses a device of CMOS image sensor, exactly, relates to a kind of CMOS charge pump circuit. The invention compromises: two current mirrors and two operational amplifiers are added into the CMOS charge pump circuit. The feed-through current is suppressed when signal switches in the said circuit. It solved the problem of the big voltage jump of the output voltage when the logic signal switches. It guarantees the stabilities of the circuit and the output voltage.

Abstract: An active-matrix-type light-emitting device includes: a pixel circuit including a light-emitting element, a driving transistor that drives the light-emitting element, a holding capacitor whose one end is connected to the driving transistor and which stores electric charges corresponding to written data, at least a control transistor that controls an operation associated with writing of data into the holding capacitor, and an emission control transistor; a first scanning line for controlling ON/OFF of the control transistor and a second scanning line for controlling ON/OFF of the emission control transistor; a data line through which the written data is transmitted to the pixel circuit; and a scanning line driving circuit which drives the first and second scanning lines and in which a current drive capability associated with the second scanning line is set to be lower than a current drive capability associated with the first scanning line.

Abstract: Provided is a semiconductor device in which change in characteristics of a transistor is suppressed and an output signal is changed sharply without increasing W/L of the transistor can be provided. Two transistors are connected in parallel between a wiring to which a low potential is supplied and an output terminal. When the low potential is output from the output terminal, both of the two transistors are turned on and then one of them is turned off. Thus, change in characteristics of the transistor can be suppressed and an output signal can be changed sharply without increasing W/L of the transistor.

Abstract: Techniques for extracting the characteristic response of a non-linear channel are presented. In various implementations of the invention, a channel's characteristic response may be determined by identifying a first input sequence, determining the ones compliment of the first input sequence and then determining the response of the channel to these two input sequences. Subsequently, two input matrices and two response matrices may be generated based upon the two input sequences and their corresponding responses. Given these four matrices, a symmetrical response component may be determined by iteratively solving a system of equations formed from the columns of each matrix. Subsequently, given the symmetric component and these four matrices, an asymmetrical response component may be determined by again iteratively solving the system of equations for the columns of each matrix.

Abstract: An impedance tuning circuit includes a calibration unit and a post-processing unit. The calibration unit generates an initial pull-up code and an initial pull-down code by performing a calibration operation using an external resistor during an initial impedance tuning operation. The post-processing unit outputs the initial pull-up code and the initial pull-down code as a final pull-up code and a final pull-down code during the initial impedance tuning operation, and generates the final pull-up code and the final pull-down code by using the initial pull-up code and the initial pull-down code during a subsequent impedance tuning operation.

Abstract: A device, comprising an output terminal; an output circuit coupled to the output terminal and having an adjustable impedance; and an impedance adjustment circuit adjusting stepwise the adjustable impedance so as to head toward a first reference impedance. The impedance adjustment circuit changes the adjustable impedance by a first amount when the adjustable impedance is within a first range, and changes the adjustable impedance by a second amount when the adjustable impedance is out of the first range. The first amount is smaller than the second amount.

Abstract: A high-speed signaling system with adaptive transmit pre-emphasis. A transmit circuit has a plurality of output drivers to output a first signal onto a signal path. A receive circuit is coupled to receive the first signal via the signal path and configured to generate an indication of whether the first signal exceeds a threshold level. A first threshold control circuit is coupled to receive the indication from the receive circuit and configured to adjust the threshold level according to whether the first signal exceeds the threshold level. A drive strength control circuit is coupled to receive the indication from the receive circuit and configured to adjust a drive strength of at least one output driver of the plurality of output drivers according to whether the first signal exceeds the threshold level.

Abstract: Apparatus and methods related to data transmission are disclosed. One such apparatus includes a transmitter, a receiver, and a channel. The transmitter includes a pair of current sources and a pair of switches. Each of the switches conducts one of the current sources to the channel in response to input data. The receiver includes a first node configured to receive a signal over the channel. The receiver also includes a resistance generating a voltage drop between the first node and a second node. The receiver further includes a first transistor and a second transistor that are together configured to provide a voltage level to the second node based at least partly on the voltage drop. The resistance provides a negative feedback to center the mean signal level, thereby reducing intersymbol interference.

Abstract: Described are amplifiers that facilitate high-speed communication with calibrated drive strength and termination impedance. Drivers and termination elements can be divided into a number N of parallel portions, one or more of which can be disabled and updated without interfering with signal (e.g., clock or data) transmission. Some embodiments identify inactive elements by examining incoming signals.

Abstract: A circuit having a centralized PT compensation circuit to provide compensation signals to localized I/O blocks on the chip. Process variations and temperature variations tend to be approximately uniform across an integrated circuit chip. Thus, a single, centralized PT compensation circuit may be used instead of one PT compensation circuit per I/O section as with solutions of the past. Further, the PT compensation circuit may generate a digital code indicative of the effects of process and temperature. Further yet, each section of I/O block may have a local voltage compensation circuit to compensate the voltage variation of the I/O block. The voltage compensation circuit utilizes an independent reference voltage. The reference voltage is generated by the PT compensation circuit, which is placed centrally in the IC chip and hence any need to repeat the reference generation for each I/O block is eliminated.

Abstract: A termination impedance apparatus includes a variable pull-up resistor, a variable pull-down resistor, and a small-signal calibration circuit. The variable pull-up resistor is coupled between a first power supply voltage terminal and an output terminal. The variable pull-down resistor is coupled between the output terminal and a second power supply voltage terminal. The small-signal calibration circuit is for calibrating the variable pull-up resistor and the variable pull-down resistor to achieve a desired small-signal impedance.

Abstract: A low voltage differential signal driving circuit including positive and negative differential output terminals, an automatic level selector, an output level detector and a transition accelerator. The positive and negative differential output terminals provide a transmission interface with a differential output signal for transmission of a data signal. The automatic level selector outputs a reference voltage corresponding to the transmission interface. The output level detector generates a low-high (or high-low) transition acceleration control signal based on the data signal, the reference voltage, and VTXP signal at the positive differential output terminal (or VTXN signal at the negative differential output terminal).

Abstract: Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including first and second transmitter-receivers that execute transmission and reception of data through a signal line. The first transmitter-receiver includes a first termination circuit that includes a first resistor and a first switch, the first resistor being provided between a first power supply terminal and the signal line, the first switch controlling a current flowing through the first resistor to be turned on and off, and a control circuit that outputs a first control signal to the first termination circuit so that the first switch is turned on when the first transmitter-receiver receives data, the first switch is turned off when the first transmitter-receiver transmits the data, and the first switch is continuously on during a first predetermined period after receiving the data when the first transmitter-receiver further receives another data after receiving the data.

Abstract: Buffer circuit embodiments are described. A buffer circuit includes an input configured to receive an input signal and a buffer configured to generate an output signal based on the input signal. In one embodiment, the buffer circuit includes a programmable chopping module coupled with the buffer, wherein the programmable chopping module is programmable with a selected configuration from a plurality of configurations, and wherein the programmable chopping modulates the input signal based on the selected configuration. In another embodiment, the buffer circuit further includes a programmable output filter coupled with the buffer, wherein the programmable output filter is programmable with a selected configuration form a plurality of configurations, and wherein the programmable output filter filters a frequency band of the output signal based on the selected configuration.

Abstract: An integrated circuit comprising an output driver including an output terminal, and a receiving circuit including a termination resistor connected between the output terminal and a ground. The output driver comprising a first NMOS transistor configured to pull up a voltage of the output terminal to a pull-up voltage in response to a pull-up signal, and a second NMOS transistor configured to pull down the output terminal to a ground voltage in response to a pull-down signal.

Abstract: Differential receivers are “stacked” and independently calibrated to different common-mode voltages. The different common-mode voltages may correspond to the common-mode voltages of stacked transmission circuits. Multiple stacks of samplers are connected to the same channels. The clocking of each stack of sampler circuits is phased (timed) such that the samplers in a given stack are not resolving at the same time. Samplers in a different stack and receiving a different common-mode voltage resolve at the same time.

Abstract: A termination circuit includes: a pull-up termination unit configured to pull-up terminate an interface node in response to a pull-up signal; a pull-down termination unit configured to pull-down terminate the interface node in response to a pull-down signal; one or more pull-up resistors connected to the interface node and enabled to affect termination resistance in response to a pull-up setting value when a termination signal is activated; and one or more pull-down resistors connected to the interface node and enabled to affect termination resistance in response to a pull-down setting value when the termination signal is activated.

Abstract: Apparatus and methods may operate so that arrival times of a data signal at gates of transistors are controlled to switch the transistors at different times to modulate the slew rate of a signal on a node. Additional embodiments are also described.

Abstract: A calibration circuit includes an amplifier, a current steering digital-to-analog converter (DAC), a comparator, a slew calibration network, and an on-die termination (ODT) network. The amplifier generally has a first input, a second input, and an output. The first input generally receives a reference signal. The current steering digital-to-analog converter (DAC) generally has a first input coupled to the output of the amplifier, a first output coupled to the second input of the amplifier, and a second output coupled to a circuit node. The comparator generally has a first input receiving the reference signal, a second input coupled to the circuit node, and an output at which an output of the calibration circuit may be presented. The slew calibration network is generally coupled to the circuit node and configured to adjust a slew rate of the calibration circuit. The on-die termination (ODT) network is generally coupled to the circuit node.