Current Driving (e.g., Fan In/out, Off Chip Driving, Etc.) Patents (Class 326/82)
  • Patent number: 11509307
    Abstract: In examples, a system includes a differential input device having a first input and a second input. The system includes a window generator configured to output, at a first output, a first voltage above a reference voltage and a second voltage, at a second output, below the reference voltage. The system includes a multiplexer coupled to the first output and the second output, the multiplexer configured to receive the first voltage, the second voltage, and an input voltage. The system includes a selector coupled to the multiplexer and configured to select the first voltage, the second voltage, or the input voltage based on a value of the input voltage, where the selector is configured to cause the multiplexer to provide the selected voltage to the first input of the differential input device, where a voltage source provides the reference voltage to the second input of the differential input device.
    Type: Grant
    Filed: November 12, 2021
    Date of Patent: November 22, 2022
    Assignee: Texas Instruments Incorporated
    Inventors: Damien Valentin Thibault Telenczak, Mikhail Valeryevich Ivanov
  • Patent number: 11489696
    Abstract: A single wire digital communication system for use with an ultrasonic surgical instrument and an ultrasonic surgical instrument including a single wire digital communication system. The single wire digital communication system includes first transmitter logic buffer and first receiver logic buffer operably coupled to a first single wire device via a first single wire communication bus. The single wire digital communication system also includes a first differential transceiver operational amplifier operably coupled to the first transmitter logic buffer via a first transmitter signal line and operably coupled to the first receiver logic buffer via a first receiver signal line. A second differential transceiver operational amplifier is operably coupled to the first differential transceiver operational amplifier via at least one differential bus. A second single wire device is operably coupled to the differential bus and configured to communicate with the first single wire device.
    Type: Grant
    Filed: October 29, 2020
    Date of Patent: November 1, 2022
    Assignee: Covidien LP
    Inventor: Travis Jones
  • Patent number: 11482989
    Abstract: Apparatuses and methods for calibrating adjustable impedances of a semiconductor device are disclosed in the present application. An example apparatus includes a register configured to store impedance calibration information and further includes programmable termination resistances having a programmable impedance. The example apparatus further includes an impedance calibration circuit configured to perform a calibration operation to determine calibration parameters for setting the programmable impedance of the programmable termination resistances. The impedance calibration circuit is further configured to program the impedance calibration information in the register related to the calibration operation.
    Type: Grant
    Filed: December 11, 2020
    Date of Patent: October 25, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Dean Gans
  • Patent number: 11476839
    Abstract: A low voltage differential signal driver includes an output driver including an N-channel source follower, a P-channel source follower, and a plurality of differential switching circuits, a plurality of high-potential output control circuits to control a terminal of the N-channel source follower of the output driver to make a high-potential output of the differential output from the output driver have a prescribed value, a plurality of low-potential output control circuits to control a terminal of the P-channel source follower of the output driver to make a low-potential output of the differential output from the output driver have a prescribed value, a high-potential generation circuit used in common for the plurality of high-potential output control circuits, and a low-potential generation circuit used in common for the plurality of low-potential output control circuits. The output driver outputs a differential output, and one of the plurality of high-potential output control circuits.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: October 18, 2022
    Assignee: RICOH COMPANY, LTD.
    Inventor: Yuji Watabe
  • Patent number: 11431531
    Abstract: A termination for a high-frequency transmission line includes a first resistor that has a first terminal coupled to a first end of a transmission line and a second terminal coupled to a first input/output pad, and a second resistor that has a first terminal coupled to the first input/output pad. The first resistor and the second resistor may provide a combined resistance that matches a nominal value of a characteristic impedance of the transmission line. The apparatus may include a third resistor having a first terminal coupled to a second end of a transmission line, and a second terminal coupled to a second input/output pad, and a fourth resistor having a first terminal coupled to the second input/output pad. The third resistor and the fourth resistor may provide a combined resistance that matches the nominal value of the characteristic impedance of the transmission line.
    Type: Grant
    Filed: March 10, 2021
    Date of Patent: August 30, 2022
    Assignee: QUALCOMM INCORPORATED
    Inventors: Chulkyu Lee, Hyunjeong Park
  • Patent number: 11431338
    Abstract: A semiconductor system includes a semiconductor apparatus and an external apparatus. The semiconductor apparatus includes a calibration code generating circuit, a code shifting circuit, and a main driver. The calibration code generating circuit performs a calibration operation to generate a calibration code. The code shifting circuit changes, based on a shifting control signal, a value of the calibration code. A resistance value of the main driver may be set on the basis of the calibration code and a shifted calibration code. The external apparatus generates the shifting control signal based on the resistance value of the main driver.
    Type: Grant
    Filed: July 7, 2021
    Date of Patent: August 30, 2022
    Assignee: SK hynix Inc.
    Inventor: Ji Hyo Kang
  • Patent number: 11316556
    Abstract: A signal transmitting circuit and a signal receiving circuit for serial communication, and an electronic device are provided. The signal transmitting circuit includes a control module, a first transmitter, a second transmitter, a first differential pin, and a second differential pin, wherein the control module is configured to control the first transmitter to output a first signal via the first differential pin, and control the second transmitter to output a second signal via the second differential pin to record target information with a target signal after differentiating between the first signal and the second signal; and wherein if the target information includes data information and instant information, the data information is recorded in the target signal with a third signal with a first frequency while recording the instant information with a fourth signal with a second frequency, the first frequency is different from the second frequency.
    Type: Grant
    Filed: March 23, 2021
    Date of Patent: April 26, 2022
    Assignee: SHANGHAI GEOMICRO DEVICES CO., LTD
    Inventors: YiXin Wang, Hengsheng Liu, Kang Chen
  • Patent number: 11276789
    Abstract: A first wafer of semiconductor material has a surface. A second wafer of semiconductor material includes a substrate and a structural layer on the substrate. The structural layer integrates a detector device for detecting electromagnetic radiation. The structural layer of the second wafer is coupled to the surface of the first wafer. The substrate of the second wafer is shaped to form a stator, a rotor, and a mobile mass of a micromirror. The stator and the rotor form an assembly for capacitively driving the mobile mass.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: March 15, 2022
    Assignee: STMicroelectronics S.r.l.
    Inventors: Luca Seghizzi, Linda Montagna, Giuseppe Visalli, Mikel Azpeitia Urquia
  • Patent number: 11270614
    Abstract: A data transmission method, a timing controller, a source driver and a display device, and a data transmission technology. The method includes: a timing controller generating an idle signal, which may be a random signal with a clock edge; and the timing controller sending the idle signal to a source driver, wherein the source driver may judge whether a clock signal of the source driver is synchronous with that of the timing controller according to the idle signal.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: March 8, 2022
    Assignees: BEIJING BOE DISPLAY TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xin Duan, Hao Zhu, Jieqiong Wang, Ming Chen, Xibin Shao
  • Patent number: 11211905
    Abstract: According to one embodiment, in a first differential amplifier circuit of a semiconductor device, a first transistor receives an input signal at the gate. A second transistor forms a differential pair with the first transistor. The second transistor receives a reference signal at the gate. A third transistor is connected in series with the first transistor. A fourth transistor is connected in series with the second transistor. A fifth transistor is disposed on the output side. The fifth transistor forms a first current mirror circuit with the fourth transistor. A sixth transistor is connected to the drain of the second transistor in parallel with the fourth transistor. The sixth transistor forms a second current mirror circuit with the fifth transistor. A first discharge circuit is connected to the source of the sixth transistor.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: December 28, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Yohei Yasuda, Hidefumi Kushibe, Toshihiro Yagi
  • Patent number: 11126153
    Abstract: The system generally includes a crosspoint switch in a local data collection system having multiple inputs and multiple outputs including a first input connected to a first sensor and a second input connected to a second sensor. The multiple outputs include a first output and a second output configured to be switchable between a condition in which the first output is configured to switch between delivery of a first sensor signal and a second sensor signal and a condition in which there is simultaneous delivery of the first sensor signal and the second sensor signal. Each of multiple inputs is configured to be individually assigned to any of the multiple outputs. The local data collection system includes multiple data acquisition units each having an onboard card set configured to store calibration information and maintenance history. The local data collection system is configured to manage data collection bands.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: September 21, 2021
    Assignee: Strong Force IOT Portfolio 2016, LLC
    Inventors: Charles Howard Cella, Gerald William Duffy, Jr., Jeffrey P. McGuckin
  • Patent number: 11127441
    Abstract: A semiconductor storage device includes a first input driver configured to receive a first signal from a memory controller, a second input driver configured to receive a chip enable signal from the memory controller, and a first control circuit. The first control circuit is configured to set the semiconductor storage device in an enabled state or a disabled state depending on whether or not the first signal which is received during a time period that starts with assertion of the chip enable signal and is prior to receipt of a command sequence, corresponds to a first chip address.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: September 21, 2021
    Assignee: KIOXIA CORPORATION
    Inventor: Tetsuaki Utsumi
  • Patent number: 11095284
    Abstract: Embodiments include a power conversion circuit comprising first and second semiconductor switches, and a drive circuit configured to create a period of operational overlap for the first and second switches by setting a gate voltage of the first switch to an intermediate value above a threshold voltage of the first switch, during turn-on and turn-off operations of the second switch. Embodiments also include a method of operating first and second semiconductor devices, comprising: reducing a gate voltage of the first device to an intermediate value above a threshold voltage while the second device is off; turning off the first device after the second device is on; increasing the gate voltage of the first device to the intermediate value while the second device is on; and fully turning on the first device after the second device is off.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: August 17, 2021
    Assignee: Ford Global Technologies, LLC
    Inventors: Krishna Prasad Bhat, Chingchi Chen
  • Patent number: 11068433
    Abstract: A serial bus repeater includes a port circuit and a low power state detection circuit. The port circuit is configured to communicate via a serial bus. The low power state detection circuit includes a power state transaction identification circuit and a bus state identification circuit. The power state transaction identification circuit is configured to identify a power state transaction on the serial bus. The power state transaction is indicative of entering a reduced power state. The bus state identification circuit is configured to identify a value of termination resistance on the serial bus that is indicative of entering the reduced power state.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: July 20, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Win Naing Maung, Suzanne Mary Vining
  • Patent number: 11011971
    Abstract: A rectifying circuit includes a HEMT, a diode connected in antiparallel to the HEMT; and a gate drive circuit, wherein the gate drive circuit includes a gate drive power supply, a first transistor, a second transistor configured to turn on in a complementary manner with the first transistor, a first capacitor including an input capacitance of the HEMT, a second capacitor provided on a pathway configured to charge the input capacitance, a first resistor connected in parallel to the first capacitor, and a second resistor connected in parallel to the second capacitor, the gate drive circuit is configured to control a gate voltage of the HEMT to make the gate voltage lower than a source voltage of the HEMT when the HEMT is turned off.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: May 18, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Takeshi Shiomi
  • Patent number: 10999922
    Abstract: Systems and methods that may be implemented to provide on-board trace impedance testing for a system level board of an information handling system. A printed circuit board (PCB) of the system level board may include built-in test trace circuitry that may be used to measure board trace impedance so that the trace impedance of a fully assembled system level board may be tested and verified for compliance with trace impedance specification, and without requiring any disassembly of the board.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: May 4, 2021
    Assignee: Dell Products L.P.
    Inventors: Charles Ziegler, Jason Pritchard
  • Patent number: 10944385
    Abstract: In certain aspects, a delay circuit includes a multiplexer, a first delay path coupled between an input of the delay circuit and a first input of the multiplexer, and a second delay path coupled between the input of the delay circuit and a second input of the multiplexer. The first delay path includes a first delay device, and the second delay path includes a first inverter, a second delay device, and a second inverter. In other aspects, a delay circuit includes a latch including a first input, a second input, and an output. The first input of the latch is coupled to an input of the delay circuit. The delay circuit also includes a delay path coupled between the input of the delay circuit and the second input of the latch, wherein the delay path includes a pulse generator and a delay device.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: March 9, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Subbarao Surendra Chakkirala, Sherif Galal
  • Patent number: 10924102
    Abstract: Disclosed is a method for driving a transistor device and an electronic circuit. The method includes: in an on-state of the transistor device (1), reducing a drive voltage (VGS) of the transistor device (1) from a maximum voltage level (VMAX) to an intermediate voltage level (VINT) that is higher than a threshold voltage level (VTH) of the transistor device (1); maintaining the intermediate voltage level (VINT) for a predefined time period (TINT); and reducing the drive voltage (VGS) to below the threshold voltage level (VTH) after the predefined time period (TINT) to switch the transistor device to an off-state.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: February 16, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Stefan H. Groiss, Aliaksandr Subotski
  • Patent number: 10886906
    Abstract: A duty-cycle adjustment circuit receives a differential pair of input signals and generates an output signal based on the differential pair. The duty-cycle adjustment circuit drives the output signal to a logic-high state based on transitions of a first polarity in a first input signal of the differential pair, and drives the output signal to a logic-low state based on transitions of the first polarity in a second input signal of the differential pair. For example, rising-edge transitions of the output signal may be aligned with rising-edge transitions of the first input signal, and falling-edge transitions of the output signal may be aligned with rising-edge transitions of the second input signal. Alternatively, rising-edge transitions of the output signal may be aligned with falling-edge transitions of the first input signal, and falling-edge transitions of the output signal may be aligned with falling-edge transitions of the second input signal.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: January 5, 2021
    Assignee: Xilinx, Inc.
    Inventors: Bob W. Verbruggen, Christophe Erdmann, Conrado K. Mesadri
  • Patent number: 10880133
    Abstract: Devices and methods for finite impulse response (FIR) feed forward equalization (FFE) at a transmitter are provided. A voltage-mode driver circuit has a main driver and an equalization driver. The main driver drives the digital output signal based on a received digital input signal. The equalization function of the equalization driver is enabled or disabled for a short duration of time to provide at least one of FIR equalization and pre-emphasis to the digital output signal. Pre-emphasis is effected by enabling a low-resistance path of the equalization driver based on the digital input signal such that, when the low-resistance path is enabled, it reduces the transmission resistance for a short period of time.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: December 29, 2020
    Assignee: Huawei Technologies Co., Ltd.
    Inventor: Euhan Chong
  • Patent number: 10868520
    Abstract: A radio frequency switch includes a control buffer circuit to generate a first gate voltage and a first body voltage; and a switching circuit to switch at least one signal path in response to the first gate voltage and the first body voltage. The control buffer circuit includes an off voltage detection circuit to detect whether the off voltage is a negative voltage or a ground voltage and output a voltage detection signal, a first gate buffer circuit to output a first gate voltage having a voltage level based on the voltage detection signal and the band selection signal, and a first body buffer circuit to output a first body voltage having a voltage level based on the voltage detection signal, the band selection signal, and the mode signal.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: December 15, 2020
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Byeong Hak Jo, Jeong Hoon Kim, Hyun Paek
  • Patent number: 10841133
    Abstract: Methods, systems, and apparatus to increase common-mode transient immunity in isolation devices is disclosed. An example apparatus includes a current mirror including an input terminal and an output terminal; a transistor including a gate terminal, a first current terminal, and a second current terminal, the gate terminal coupled to a reference voltage terminal, the first current terminal coupled to the input terminal of the current mirror, and the second current terminal coupled to an input node; a buffer including an input terminal and an output terminal, the input terminal of the buffer coupled to the output terminal of the current mirror; and a logic gate including an input terminal and an output terminal, the input terminal of the logic gate coupled to the output terminal of the buffer.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: November 17, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Zhidong Liu, James Michael Walden, Satish Kumar Vemuri
  • Patent number: 10840795
    Abstract: A driver for driving a power transistor, the driver having: a first transistor, and a second transistor; wherein (1) when the first transistor is turned on, the second transistor is simultaneously turned on, and wherein after the second transistor remains on for a first time period, the second transistor is turned off for a second time period during when a switching voltage at a second terminal of the power transistor is rising, and the second transistor is turned on after the second time period is over; and (2) when the first transistor is turned off, the second transistor is simultaneously turned off.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: November 17, 2020
    Assignee: Monolithic Power Systems, Inc.
    Inventor: James Nguyen
  • Patent number: 10834672
    Abstract: A first method includes determining a total length of pending packets for a network link, determining a currently preferred power mode for the network link based on the total length of pending packets for the network link, and changing a current power mode for the network link to the currently preferred power mode. A corresponding apparatus is also disclosed herein. A second method includes determining a utilization for a network link, determining a currently preferred power mode for the network link based on the utilization for the network link, and changing a current power mode for the network link to the currently preferred power mode. A corresponding apparatus is also disclosed herein.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Dong Chen, Paul W. Coteus, Noel A. Eisley, Philip Heidelberger, Robert M. Senger, Burkhard Steinmacher-Burow, Yutaka Sugawara
  • Patent number: 10826810
    Abstract: A method and apparatus in a receiver to determine if a high speed communication link is in an idle mode or in an active mode. Signals during the idle mode are of lower amplitude and lower frequency compared to amplitude and frequency in the active mode. A signal detector in the receiver determines if the high speed communication link has transitioned from idle mode to active mode and, if so, wakes up high power circuitry in the receiver to receive data.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: November 3, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Yang You, Pier Andrea Francese, Glen Wiedemeier, Daniel M. Dreps, Chad Andrew Marquart
  • Patent number: 10748890
    Abstract: Disclosed herein is an electronic device including an IO node, with a receiver coupled to receive input from the IO node. A transmitter driver has a first n-channel DMOS with a source coupled to the IO node. A pass gate circuit decouples the IO node from the receiver based upon presence of a negative voltage at the IO node and couples the IO node to the receiver based upon lack of presence of the negative voltage at the IO node. A transmit protection circuit applies the negative voltage from the IO node to the gate and bulk of the first n-channel DMOS based upon the presence of the negative voltage at the IO node.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: August 18, 2020
    Assignee: STMicroelectronics International N.V.
    Inventor: Ravinder Kumar
  • Patent number: 10749511
    Abstract: The present disclosure provides an IO circuit and an access control signal generation circuit for the IO circuit. In one implementation, the access control signal generation circuit includes: a bias module coupled with an IO port, for generating an access control signal according to an IO port signal and an IO control signal, where a voltage value of the access control signal is a maximum value of a voltage value of an IO port voltage division signal and a voltage value of the IO control signal, and the voltage value of the IO port voltage division signal is a percentage of a voltage value of the IO port signal; an access control module coupled with the bias module, the access control module configured to control cut-off or conduction when receiving the access control signal and the IO port signal and outputting a first interface signal; and a higher-selection module configured to generate a second interface signal according to an IO power source signal and the IO port signal.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: August 18, 2020
    Assignees: Semiconductor Manufacturing (Beijing) International Corporation, Semiconductor Manufacturing (Shanghai) International Corporation
    Inventors: Yan Geng, Jie Chen, Xiao Yuan Ma, Kai Zhu, Yan Ling
  • Patent number: 10749519
    Abstract: Turn-on and turn-off of a semiconductor device are controlled through control of a gate voltage in accordance with a driving control signal. At a first time after a start of a Miller period of a gate voltage in driving a gate of the semiconductor device in accordance with the driving control signal, a driving signal is changed from “1” to “0” to thereby make a gate driving ability temporarily lower than the gate driving ability during a period from a starting time of the turn-on operation to the first time. Further, at a second time corresponding to an end of the Miller period, the driving signal is changed from “0” to “1” to thereby increase the gate driving ability.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: August 18, 2020
    Assignee: MITUSHIBHI ELECTRIC CORPORATION
    Inventor: Yukihiko Wada
  • Patent number: 10749429
    Abstract: Methods and systems of reducing a substrate noise in a charge pump having a flying capacitor are provided. An input node of the flying capacitor is pre-charged at a first slew rate. The input node of the flying capacitor is charged at a second slew rate that is faster than the first slew rate. The input node of the flying capacitor is pre-discharged at a third slew rate. The input node of the flying capacitor is discharged at a fourth slew rate that is faster than the first slew rate.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: August 18, 2020
    Assignee: Linear Technology LLC
    Inventor: Barry Harvey
  • Patent number: 10741142
    Abstract: One or more resistors or resistances are integrated in a 7-bit DVR or PVCOM integrated circuit. A 7-bit DVR or PVCOM integrated circuit includes a 7-bit DAC. The integrated resistors or resistances (R1, R2, or RSET, or any combination) reduces the number of external components, reduces the number of pins, and increases the accuracy of the DVR or PVCOM circuit. The least significant bit (LSB) of the DAC depends only on ratios of internal resistors, which can be made very accurate and independent of temperature.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: August 11, 2020
    Assignee: IML International
    Inventors: Alberto Giovanni Viviani, ChinFa Kao, Chiayao S. Tung
  • Patent number: 10700685
    Abstract: A high-speed signal driving device includes an assist driver, a delay adjuster, and a plurality of drivers. The assist driver receives a control signal and is coupled to a first output node and a second output node to output a first current to the first output node or the second output node. The delay adjuster receives the control signal to generate a plurality of delay signals. Each of the delay signals has a different delay time corresponding to the control signal. One of the drivers receives the control signal, and other drivers correspondingly receive the plurality of delay signals. The plurality of drivers are coupled to the first output node and the second output node via a first output end and a second output end.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: June 30, 2020
    Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
    Inventor: Hongwei Si
  • Patent number: 10659051
    Abstract: A voltage translator having first and second one-shots shifts a voltage level of a first voltage signal to generate a second voltage signal, and vice-versa. The first one-shot generates a first driver signal when the first voltage signal goes from low to high based on a time duration for which the first voltage signal remains high. The second voltage signal is generated based on the first driver signal. Similarly, the second one-shot generates the first voltage signal when the second voltage signal goes from a low to high based on a time duration for which the second voltage signal remains high.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: May 19, 2020
    Assignee: NXP USA, Inc.
    Inventor: Chandra Prakash Tiwari
  • Patent number: 10629287
    Abstract: A semiconductor apparatus may include a degradation detection circuit and a circuit block. The degradation detection circuit may detect a degradation occurred in a semiconductor apparatus and generate degradation information. The circuit block may include at least one transistor configured to receive a variable bias voltage and a variable gate voltage.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: April 21, 2020
    Assignee: SK hynix Inc.
    Inventors: Woongrae Kim, Bok Rim Ko, Keun Soo Song
  • Patent number: 10528018
    Abstract: The methods and systems for data collection, processing, and utilization of signals with a platform monitoring at least a first element in a first machine in an industrial environment generally include obtaining, automatically with a computing environment, at least a first sensor signal and a second sensor signal with a local data collection system that monitors at least the first machine and connecting a first input of a crosspoint switch of the local data collection system to a first sensor and a second input of the crosspoint switch to a second sensor in the local data collection system.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: January 7, 2020
    Assignee: Strong Force IOT Portfolio 2016, LLC
    Inventors: Charles Howard Cella, Gerald William Duffy, Jr., Jeffrey P. McGuckin
  • Patent number: 10488836
    Abstract: The methods and systems for data collection, processing, and utilization of signals with a platform monitoring at least a first element in a first machine in an industrial environment generally include obtaining, automatically with a computing environment, at least a first sensor signal and a second sensor signal with a local data collection system that monitors at least the first machine and connecting a first input of a crosspoint switch of the local data collection system to a first sensor and a second input of the crosspoint switch to a second sensor in the local data collection system.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: November 26, 2019
    Assignee: Strong Force IOT Portfolio 2016, LLC
    Inventors: Charles Howard Cella, Gerald William Duffy, Jr., Jeffrey P. McGuckin
  • Patent number: 10488914
    Abstract: Apparatuses in data input/output circuits of a semiconductor device are described. An example apparatus includes an output driver and a pre-output driver. The pre-output driver includes: an output terminal coupled to the output driver and provides an output signal to the output driver; an output stage that receives a data signal and provides the output signal to the output terminal responsive, at least in part, to the data signal; and a slew rate control stage coupled to the output stage and controls a current flowing through the output stage. The output stage is disposed between the slew rate control stage and the output terminal.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: November 26, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Mieko Kojima
  • Patent number: 10441972
    Abstract: A transmission channel transmits high-voltage pulses in a transmission phase and receives echoes of the high-voltage pulses in a receiving phase. The transmission channel includes a buffer with anti-memory circuitry to couple drain conduction terminals of buffer transistors of a high-side of a buffer of the transmission channel to a low-side reference voltage of a low-side of the buffer and couple drain conduction terminals of buffer transistors of the low-side of the buffer to a high-side reference voltage of the high-side of the buffer during the clamping phase.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: October 15, 2019
    Assignee: STMicroelectronics S.r.l.
    Inventors: Davide Ugo Ghisu, Sandro Rossi, Dario Bianchi
  • Patent number: 10305483
    Abstract: A receiving circuit includes a first amplification circuit and a second amplification circuit. The first amplification circuit may generate a first output signal by asymmetrically and differentially amplifying first and second signals. The second amplification circuit may generate a second output signal by asymmetrically and differentially amplifying the second and first signals.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: May 28, 2019
    Assignee: SK hynix Inc.
    Inventor: Hyun Bae Lee
  • Patent number: 10298241
    Abstract: A bidirectional clock synchronization circuit is provided. The circuit includes a bidirectional port having an input/output terminal and a transceiver, having a first interface with a unidirectional input and a unidirectional output, and a second interface with a bidirectional input/output coupled to the input/output terminal of the bidirectional port. The circuit includes a phase locked loop (PLL), having an output coupled to the unidirectional input of the transceiver, and having an input coupled to the unidirectional output of the transceiver, the phase locked loop selectable as to frequency range for the input or the output of the phase locked loop.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: May 21, 2019
    Assignee: ARISTA NETWORKS, INC.
    Inventor: David Anthony Cananzi
  • Patent number: 10234887
    Abstract: An electronic circuit includes semiconductor substrate having a first doping type and a reference terminal coupled to the semiconductor substrate. A tub area having a second doping type is formed in the semiconductor substrate. A well area having the first doping type is formed within the tub area. A driver circuit comprising a transistor is formed within the well area and has an output terminal. A control circuit is coupled to the driver circuit for controlling the driver circuit. A second transistor is within the well area and coupled in series between the driver circuit and the output terminal, the second transistor having a first terminal coupled to the driver circuit and a second terminal coupled to the output terminal. A biasing circuit is coupled to a gate terminal of the second transistor and configured to bias the transistor to a conducting state.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: March 19, 2019
    Assignee: Allegro MicroSystems, LLC
    Inventors: Richard B. Cooper, Maxim Klebanov, Washington Lamar, Devon Fernandez
  • Patent number: 10230364
    Abstract: A device comprises a first diode and a second diode connected in series between a first terminal and a second terminal of a switching element, wherein an anode of the first diode is directly connected to an anode of the second diode, a third diode connected between the first terminal and the second terminal of the switching element and a first switch connected in parallel with the first diode.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: March 12, 2019
    Assignee: Futurewei Technologies, Inc.
    Inventors: Dianbo Fu, Zhaohui Wang, Jun Zhang, Lei Shi
  • Patent number: 10171070
    Abstract: A first circuit outputs transmission signals that change between “H” and “L” in a period of an oscillation signal in addition to a transition time of an input signal when it changes to “H” or “L”. Control protection elements invalidate induced voltage signals obtained from transformers for first and second mask periods in response to transmission signals. Buffer circuits and Schmitt circuits generate a first signal and a second signal, each indicating “H” for a relatively long period, on the basis of “H” of the induced voltage signals. A control circuit invalidates the first signal and the second signal when both the first signal and the second signal indicate “H”.
    Type: Grant
    Filed: May 12, 2016
    Date of Patent: January 1, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kenichi Morokuma, Jun Tomisawa, Tetsuya Uchida, Shoichi Orita
  • Patent number: 10156893
    Abstract: Apparatuses in data input/output circuits of a semiconductor device are described. An example apparatus includes an output driver and a pre-output driver. The pre-output driver includes: an output terminal coupled to the output driver and provides an output signal to the output driver; an output stage that receives a data signal and provides the output signal to the output terminal responsive, at least in part, to the data signal; and a slew rate control stage coupled to the output stage and controls a current flowing through the output stage. The output stage is disposed between the slew rate control stage and the output terminal.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: December 18, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Mieko Kojima
  • Patent number: 10135443
    Abstract: An off chip driver circuit includes a bias circuit and a driver sub-cell circuit. The bias circuit and off chip driver sub-cell circuit are in electrical communication with each other. The bias circuit includes two serially aligned diodes which are in an off-state when the driver sub-cell is in a functional mode and which are in an on-state when the driver sub-cell is in a cold spare mode. The arrangement of the diodes enables the off chip driver circuit to handle similar voltage signals in both the functional mode and the cold spare mode.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: November 20, 2018
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventor: Jason F. Ross
  • Patent number: 10121523
    Abstract: A memory array contains a plurality of banks coupled to each other by a plurality of data lines. Each of the data lines is divided into a plurality of segments within the array. Respective bidirectional buffers couple read data from one of the segments to another in a first direction, and to couple write data from one of the segments to another in a second direction that is opposite the first direction. The data lines may be local data read/write lines that couple different banks of memory cells to each other and to respective data terminals, digit lines that couple memory cells in a respective column to respective sense amplifiers, word lines that activate memory cells in a respective row, or some other signal line within the array. The memory array also includes precharge circuits for precharging the segments of respective data lines to a precharge voltage.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: November 6, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Aidan Shori, Sumit Chopra
  • Patent number: 10084619
    Abstract: A method and system of optical communication are provided. An optical modulator device includes a first and a second waveguide segment, and is configured to modulate an incident optical signal. A first feed-forward equalization (FFE) circuit including an inner first tap and an inner second tap, is configured to equalize the first waveguide segment. A second FFE circuit including a first inner tap and a second inner tap, is configured to equalize the second waveguide segment. An FFE recombination of the first inner tap and the second inner tap of the first and second FFE circuits, is in the electrical domain, respectively. An FFE recombination of the first and second modulation signals, operative to equalize a combination of the first second waveguide segments, is in the optical domain.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: September 25, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Nicolas Dupuis, Tam N. Huynh, Benjamin G. Lee, Jonathan E. Proesel, Renato Rimolo-Donadio, Alexander V. Rylyakov, Clint L. Schow
  • Patent number: 10056894
    Abstract: A drive unit of a semiconductor element including: a drive circuit for driving a control electrode of a voltage control semiconductor element to which a freewheeling diode is connected in anti-parallel; a resistor connected between the control electrode and the drive circuit; a capacitor having one terminal connected between the resistor and the control electrode; and a switch element connected between another terminal of the capacitor and a low-voltage-side electrode of the voltage control semiconductor element, wherein a control electrode of the switch element is connected to a connection point of the resistor and the capacitor.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: August 21, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Shuangching Chen, Shogo Ogawa
  • Patent number: 10031877
    Abstract: Including control data in a serial audio stream is presented herein. A device can include a clock component that is configured to send, via a clock pin of the device, a bit clock signal directed to a slave device. A frame component can send, via a frame pin of the device, a frame clock signal directed to the slave device. A control component can receive, via a data pin of the device during a first portion of a phase of a period of the frame clock signal, slave data from the slave device on a bit-by-bit basis based on the bit clock signal according to an integrated interchip sound (I2S) based protocol; and send, via the data pin during a second portion of the phase after the first portion, a set of control bits directed to the slave device on the bit-by-bit basis based on the bit clock signal.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: July 24, 2018
    Assignee: INVENSENSE, INC.
    Inventors: Jerad M. Lewis, Kieran P. Harney, Aleksey S. Khenkin
  • Patent number: 10033384
    Abstract: Disclosed herein is a driver circuit including a first group of transistors provided between first and second nodes and including n of the transistor(s) where n is equal to or greater than one, and a second group of transistors provided in parallel with the first group of transistors and including m of the transistor(s) where m is equal to or greater than one and not equal to n, the m transistors being connected together in series. The n-channel transistor in the first group and at least one of the two n-channel transistors in the second group have their gate connected to an input node.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: July 24, 2018
    Assignee: Socionext Inc.
    Inventors: Tsuyoshi Koike, Yasuhiro Agata, Yoshinobu Yamagami
  • Patent number: 10033378
    Abstract: A solid state power control apparatus includes: (a) at least one IGBT and at least one FET, for supplying current to a load, and (b) a current controller for shutting off the IGBT and FET. The current controller is arranged to start shut off of the IGBT before it starts shut off of the FET. Further, the current controller is arranged to reduce current flow prior to start of the turn off of the IGBT and FET.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: July 24, 2018
    Assignee: ROLLS-ROYCE PLC
    Inventor: Simon Turvey