Current Driving (e.g., Fan In/out, Off Chip Driving, Etc.) Patents (Class 326/82)
  • Patent number: 10305483
    Abstract: A receiving circuit includes a first amplification circuit and a second amplification circuit. The first amplification circuit may generate a first output signal by asymmetrically and differentially amplifying first and second signals. The second amplification circuit may generate a second output signal by asymmetrically and differentially amplifying the second and first signals.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: May 28, 2019
    Assignee: SK hynix Inc.
    Inventor: Hyun Bae Lee
  • Patent number: 10298241
    Abstract: A bidirectional clock synchronization circuit is provided. The circuit includes a bidirectional port having an input/output terminal and a transceiver, having a first interface with a unidirectional input and a unidirectional output, and a second interface with a bidirectional input/output coupled to the input/output terminal of the bidirectional port. The circuit includes a phase locked loop (PLL), having an output coupled to the unidirectional input of the transceiver, and having an input coupled to the unidirectional output of the transceiver, the phase locked loop selectable as to frequency range for the input or the output of the phase locked loop.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: May 21, 2019
    Assignee: ARISTA NETWORKS, INC.
    Inventor: David Anthony Cananzi
  • Patent number: 10234887
    Abstract: An electronic circuit includes semiconductor substrate having a first doping type and a reference terminal coupled to the semiconductor substrate. A tub area having a second doping type is formed in the semiconductor substrate. A well area having the first doping type is formed within the tub area. A driver circuit comprising a transistor is formed within the well area and has an output terminal. A control circuit is coupled to the driver circuit for controlling the driver circuit. A second transistor is within the well area and coupled in series between the driver circuit and the output terminal, the second transistor having a first terminal coupled to the driver circuit and a second terminal coupled to the output terminal. A biasing circuit is coupled to a gate terminal of the second transistor and configured to bias the transistor to a conducting state.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: March 19, 2019
    Assignee: Allegro MicroSystems, LLC
    Inventors: Richard B. Cooper, Maxim Klebanov, Washington Lamar, Devon Fernandez
  • Patent number: 10230364
    Abstract: A device comprises a first diode and a second diode connected in series between a first terminal and a second terminal of a switching element, wherein an anode of the first diode is directly connected to an anode of the second diode, a third diode connected between the first terminal and the second terminal of the switching element and a first switch connected in parallel with the first diode.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: March 12, 2019
    Assignee: Futurewei Technologies, Inc.
    Inventors: Dianbo Fu, Zhaohui Wang, Jun Zhang, Lei Shi
  • Patent number: 10171070
    Abstract: A first circuit outputs transmission signals that change between “H” and “L” in a period of an oscillation signal in addition to a transition time of an input signal when it changes to “H” or “L”. Control protection elements invalidate induced voltage signals obtained from transformers for first and second mask periods in response to transmission signals. Buffer circuits and Schmitt circuits generate a first signal and a second signal, each indicating “H” for a relatively long period, on the basis of “H” of the induced voltage signals. A control circuit invalidates the first signal and the second signal when both the first signal and the second signal indicate “H”.
    Type: Grant
    Filed: May 12, 2016
    Date of Patent: January 1, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kenichi Morokuma, Jun Tomisawa, Tetsuya Uchida, Shoichi Orita
  • Patent number: 10156893
    Abstract: Apparatuses in data input/output circuits of a semiconductor device are described. An example apparatus includes an output driver and a pre-output driver. The pre-output driver includes: an output terminal coupled to the output driver and provides an output signal to the output driver; an output stage that receives a data signal and provides the output signal to the output terminal responsive, at least in part, to the data signal; and a slew rate control stage coupled to the output stage and controls a current flowing through the output stage. The output stage is disposed between the slew rate control stage and the output terminal.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: December 18, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Mieko Kojima
  • Patent number: 10135443
    Abstract: An off chip driver circuit includes a bias circuit and a driver sub-cell circuit. The bias circuit and off chip driver sub-cell circuit are in electrical communication with each other. The bias circuit includes two serially aligned diodes which are in an off-state when the driver sub-cell is in a functional mode and which are in an on-state when the driver sub-cell is in a cold spare mode. The arrangement of the diodes enables the off chip driver circuit to handle similar voltage signals in both the functional mode and the cold spare mode.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: November 20, 2018
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventor: Jason F. Ross
  • Patent number: 10121523
    Abstract: A memory array contains a plurality of banks coupled to each other by a plurality of data lines. Each of the data lines is divided into a plurality of segments within the array. Respective bidirectional buffers couple read data from one of the segments to another in a first direction, and to couple write data from one of the segments to another in a second direction that is opposite the first direction. The data lines may be local data read/write lines that couple different banks of memory cells to each other and to respective data terminals, digit lines that couple memory cells in a respective column to respective sense amplifiers, word lines that activate memory cells in a respective row, or some other signal line within the array. The memory array also includes precharge circuits for precharging the segments of respective data lines to a precharge voltage.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: November 6, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Aidan Shori, Sumit Chopra
  • Patent number: 10084619
    Abstract: A method and system of optical communication are provided. An optical modulator device includes a first and a second waveguide segment, and is configured to modulate an incident optical signal. A first feed-forward equalization (FFE) circuit including an inner first tap and an inner second tap, is configured to equalize the first waveguide segment. A second FFE circuit including a first inner tap and a second inner tap, is configured to equalize the second waveguide segment. An FFE recombination of the first inner tap and the second inner tap of the first and second FFE circuits, is in the electrical domain, respectively. An FFE recombination of the first and second modulation signals, operative to equalize a combination of the first second waveguide segments, is in the optical domain.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: September 25, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Nicolas Dupuis, Tam N. Huynh, Benjamin G. Lee, Jonathan E. Proesel, Renato Rimolo-Donadio, Alexander V. Rylyakov, Clint L. Schow
  • Patent number: 10056894
    Abstract: A drive unit of a semiconductor element including: a drive circuit for driving a control electrode of a voltage control semiconductor element to which a freewheeling diode is connected in anti-parallel; a resistor connected between the control electrode and the drive circuit; a capacitor having one terminal connected between the resistor and the control electrode; and a switch element connected between another terminal of the capacitor and a low-voltage-side electrode of the voltage control semiconductor element, wherein a control electrode of the switch element is connected to a connection point of the resistor and the capacitor.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: August 21, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Shuangching Chen, Shogo Ogawa
  • Patent number: 10031877
    Abstract: Including control data in a serial audio stream is presented herein. A device can include a clock component that is configured to send, via a clock pin of the device, a bit clock signal directed to a slave device. A frame component can send, via a frame pin of the device, a frame clock signal directed to the slave device. A control component can receive, via a data pin of the device during a first portion of a phase of a period of the frame clock signal, slave data from the slave device on a bit-by-bit basis based on the bit clock signal according to an integrated interchip sound (I2S) based protocol; and send, via the data pin during a second portion of the phase after the first portion, a set of control bits directed to the slave device on the bit-by-bit basis based on the bit clock signal.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: July 24, 2018
    Assignee: INVENSENSE, INC.
    Inventors: Jerad M. Lewis, Kieran P. Harney, Aleksey S. Khenkin
  • Patent number: 10033384
    Abstract: Disclosed herein is a driver circuit including a first group of transistors provided between first and second nodes and including n of the transistor(s) where n is equal to or greater than one, and a second group of transistors provided in parallel with the first group of transistors and including m of the transistor(s) where m is equal to or greater than one and not equal to n, the m transistors being connected together in series. The n-channel transistor in the first group and at least one of the two n-channel transistors in the second group have their gate connected to an input node.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: July 24, 2018
    Assignee: Socionext Inc.
    Inventors: Tsuyoshi Koike, Yasuhiro Agata, Yoshinobu Yamagami
  • Patent number: 10033378
    Abstract: A solid state power control apparatus includes: (a) at least one IGBT and at least one FET, for supplying current to a load, and (b) a current controller for shutting off the IGBT and FET. The current controller is arranged to start shut off of the IGBT before it starts shut off of the FET. Further, the current controller is arranged to reduce current flow prior to start of the turn off of the IGBT and FET.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: July 24, 2018
    Assignee: ROLLS-ROYCE PLC
    Inventor: Simon Turvey
  • Patent number: 10008146
    Abstract: A source driving circuit is provided. The source driving circuit includes a digital-to-analog conversion module configured for converting raw image data into gray-scale image data; an optimization module configured for obtaining an optimal output sequence of the gray-scale values in pixel units for each row in a display panel and outputting the gray-scale values of each pixel in pixel units corresponding to data lines by following the order of the optimal output sequence to form a first image data; and a buffer module configured for enhancing a load driving capability of the first image data outputted by the optimization module.
    Type: Grant
    Filed: September 6, 2015
    Date of Patent: June 26, 2018
    Assignees: Shenzhen China Star Optoelectronics Technology Co., Ltd., Wuhan China Star Optoelectronics Technology Co., Ltd.
    Inventors: Xingling Guo, Taisheng An, Man Li
  • Patent number: 9985526
    Abstract: A switching voltage converter is disclosed. The voltage converter includes a controller configured to generate first and second control signals, and a switch stack including six serially connected switches configured to receive a plurality of fixed voltages and the first and second control signals. The switch stack is configured to generate a voltage signal at a switch node based on the fixed voltages and on the control signals. In addition, the voltage signal is controlled to be substantially equal to a first fixed supply voltage or substantially equal to a second fixed supply voltage according to the first and second control signals, and an output filter connected to the switch node and configured to generate an output voltage based on the voltage at the switch node.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: May 29, 2018
    Assignee: EMPOWER SEMICONDUCTOR
    Inventor: Parag Oak
  • Patent number: 9978442
    Abstract: A memory is disclosed. The memory includes a memory array having a plurality of memory cells. The memory also includes an address decoder configured to assert a wordline to enable the memory cells. Additionally, the memory includes a tracking circuit configured to vary a duration of asserting the wordline as a function of which one of the memory cells is accessed. A method is also disclosed. The method includes asserting a wordline to enable the memory cells and varying a duration of asserting the wordline as a function of which one of a plurality of memory cells is accessed.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: May 22, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Bin Liang, Tony Chung Yiu Kwok, Rui Li, Sei Seung Yoon
  • Patent number: 9940278
    Abstract: A system on chip, semiconductor device, and/or method are provided that include a plurality of masters, an interface, and a semaphore unit. The interface interfaces the plurality of masters with a slave device. The semaphore unit detects requests of the plurality of masters, controlling the salve device, about an access to the interface and assigns a semaphore about each of the plurality of masters by a specific operation unit according to the detection result.
    Type: Grant
    Filed: October 7, 2015
    Date of Patent: April 10, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: DongSik Cho, Jeonghoon Kim, Rohitaswa Bhattacharya, Jaeshin Lee, Honggi Jeong
  • Patent number: 9934169
    Abstract: A method of operating an input/output interface includes selecting one of a plurality of output driver circuits according to a mode selection signal, and outputting a data signal using the selected one of the plurality of output driver circuits. Another method of operating an includes generating a mode selection signal based on a received command signal, and controlling an on-die termination (ODT) circuit included in the input/output interface according to the mode selection signal. Another method of operating an includes generating a mode selection signal based on a received command signal, and controlling an ODT circuit included in the input/output interface according to the mode selection signal.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: April 3, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young Chul Cho, Jung Bae Lee, Jung Hwan Choi
  • Patent number: 9928208
    Abstract: System, methods and apparatus are described that offer improved performance of an Inter-Integrated Circuit (I2C) bus. Primary data may be encoded in first signaling in accordance with I2C bus protocols, and the first signaling may be combined with second signaling to obtain combined signaling for transmission on an I2C bus. Secondary data may be encoded in the second signaling with the combined signaling remaining compatible with the I2C bus protocols. The second signaling may modulate a voltage level of at least one signal in the first signaling. The second signaling may pulse-width modulate a clock signal transmitted on the I2C bus. The second signaling may modify a start condition between bytes transmitted on the I2C bus. The second signaling may add a plurality of short pulses to a clock signal transmitted in the first signaling.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: March 27, 2018
    Assignee: QUALCOMM Incorporated
    Inventor: Shoichiro Sengoku
  • Patent number: 9923506
    Abstract: A high-efficiency motor control system and method is presented for controlling an electric motor. The system can feature a multi-phase inverter having a logic control device and associated control circuity, a plurality of floating charge pumps and pump circuitry, a multi-phase bridge having a plurality of power switching devices and a bootstrap capacitor circuit having a floating ground. The floating charge pumps feature grounds electrically coupled to motor phase leads. The bootstrap circuit can feature a floating ground, with a floating voltage being carried across the bootstrap circuit and delivered to the switching devices to produce an indefinite on-time for the switching devices for switching the high-side of a power supply to a load.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: March 20, 2018
    Assignee: METROPOLITAN INDUSTRIES, INC.
    Inventors: John Kochan, Jr., James Andrew Nimmer, John Brian Dempster
  • Patent number: 9905287
    Abstract: An apparatus includes an interface and a circuit. The interface may be configured to generate a read signal that carries read data from a memory channel. The circuit may be configured to (i) modify the read signal with a de-emphasis on each pull up of the read signal and a pre-emphasis on each pull down of the read signal and (ii) transfer the read signal as modified to a memory controller.
    Type: Grant
    Filed: April 6, 2017
    Date of Patent: February 27, 2018
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventors: Yanbo Wang, Praveen Rajan Singh, Yue Yu, Craig DeSimone
  • Patent number: 9880610
    Abstract: The present disclosure discloses a power supplying method, a power supplying system, and an electronic device to address the technical problems in the related art that the structure of an electronic device is complex, thereby achieving the technical effect that the internal structure of an electronic device is simplified and the cost for manufacturing the electronic device is reduced.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: January 30, 2018
    Assignees: BEIJING LENOVO SOFTWARE LTD., LENOVO (BEIJING) LIMITED
    Inventors: Dongzhe Liu, Wei Liu, Yuanyuan Wu
  • Patent number: 9871539
    Abstract: A driver circuit for receiving a data input and generating an output signal to a termination element according to at least the first data input is provided. The driver circuit includes a first output terminal, a current mode drive unit and a voltage mode drive unit. The current mode drive unit is arranged for selectively outputting a first reference current from the first output terminal to the termination element according to the first data input, and selectively receiving the first reference current through the first output terminal according to the first data input. The voltage mode drive unit is arranged for coupling one of a first reference voltage and a second reference voltage different from the second reference voltage to the first output terminal according to the first data input.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: January 16, 2018
    Assignee: MEDIATEK INC.
    Inventors: Chien-Hua Wu, Yan-Bin Luo
  • Patent number: 9871506
    Abstract: Aspects of an integrated circuit are disclosed. The integrated circuit includes a first circuit configured to be powered by a first voltage source, a second circuit configured to be powered by a second voltage source, a decoupling capacitor, and a controller configured to switch the decoupling capacitor between the first and second voltage source.
    Type: Grant
    Filed: April 16, 2014
    Date of Patent: January 16, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Ryan Michael Coutts, Mikhail Popovich
  • Patent number: 9853637
    Abstract: Switch devices using switch transistors with dual gates are provided. The dual gates may be controlled independently from each other by first and second gate driver circuits.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: December 26, 2017
    Assignee: Infineon Technologies AG
    Inventors: Andreas Meiser, Anton Mauder, Jens Barrenscheen
  • Patent number: 9836105
    Abstract: A power-off control circuit applied in an electronic device includes a switch, a first control unit, a first buffer unit, a second control unit, and a second buffer unit. A first control unit coupled to the second terminal of the switch. The first control unit receives a first logic signal when the switch is pressed, and outputs a first control signal. A first buffer unit is coupled to an output of the first control unit to receive the first control signal, and outputs a second control signal. A second buffer unit is coupled to the second terminal of the switch to receive the first logic signal, and outputs a third control signal. A second control unit is coupled to an output of the second buffer unit to receive the third control signal, and outputs a power-off control signal to make the electronic device to power-off.
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: December 5, 2017
    Assignees: HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD., HON HAI PRECISION INDUSTRY CO., LTD.
    Inventor: Jin-Shan Ma
  • Patent number: 9831665
    Abstract: A sensing transistor is provided to supply a detection current in proportion to a current flowing to an output transistor. A shunt resistor is connected between a source of the sensing transistor and the ground. A voltage follower circuit receives a terminal voltage of the shunt resistor and have a base-emitter path of each of transistors in a path between its input and its output. An output voltage of the voltage follower circuit is applied to a current generation resistor. A current drawing circuit draws a control current, which corresponds to a current flowing in the current generation resistor, from a gate control line extending from a gate control circuit to a gate of the output transistor.
    Type: Grant
    Filed: March 24, 2015
    Date of Patent: November 28, 2017
    Assignee: DENSO CORPORATION
    Inventor: Junichi Yoshida
  • Patent number: 9754550
    Abstract: One or more resistors or resistances are integrated in a 7-bit DVR or PVCOM integrated circuit. A 7-bit DVR or PVCOM integrated circuit includes a 7-bit DAC. The integrated resistors or resistances (R1, R2, or RSET, or any combination) reduces the number of external components, reduces the number of pins, and increases the accuracy of the DVR or PVCOM circuit. The least significant bit (LSB) of the DAC depends only on ratios of internal resistors, which can be made very accurate and independent of temperature.
    Type: Grant
    Filed: January 17, 2017
    Date of Patent: September 5, 2017
    Assignee: IML International
    Inventors: Alberto Giovanni Viviani, ChinFa Kao, Chiayao S. Tung
  • Patent number: 9735662
    Abstract: An insulation communication device includes a transmission circuit having a primary coil; and a reception circuit including a secondary coil, and is configured to transmit a signal from the transmission circuit to the reception circuit by magnetic coupling between the primary coil and the secondary coil. The transmission circuit includes an edge detection circuit, a bridge circuit, a coil current information detection circuit, and a pulse signal control circuit. The reception circuit includes a first detection circuit, a second detection circuit and an output signal generation circuit.
    Type: Grant
    Filed: December 26, 2014
    Date of Patent: August 15, 2017
    Assignee: DENSO CORPORATION
    Inventors: Kohei Ikegawa, Shuntaro Okada, Takeshi Nakamura
  • Patent number: 9698787
    Abstract: An integrated circuit includes a low voltage differential signaling (LVDS) output circuit, a high-speed current steering logic (HCSL) output circuit, a bias control circuit, a programmable voltage reference circuit coupled to the bias control circuit, an output stage circuit coupled to the HCSL output circuit, a first plurality of switches to switchably couple the bias control circuit to the LVDS output circuit, a second plurality of switches to switchably couple the bias control circuit to the output stage circuit and to the HCSL output circuit and a logic control circuit coupled to the programmable voltage reference circuit, the first plurality of switches and the second plurality of switches. The logic control circuit is configured to activate either the LVDS output circuit or the HCSL output circuit.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: July 4, 2017
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventors: Vikas Agrawal, Feng Qiu, John C. Hsu
  • Patent number: 9684350
    Abstract: An apparatus is described herein. The apparatus includes a plurality of electrical components, wherein at least one component is to increase a total impedance at a port. The apparatus also includes a comparator, wherein the comparator is to determine an additional impedance from the plurality of electrical components at the port and adjust the impedance to maintain signal integrity along a trace to the port in response to a device being coupled with the port.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: June 20, 2017
    Assignee: Intel Corporation
    Inventor: Chia How Low
  • Patent number: 9680458
    Abstract: Disclosed herein are various implementations of input-controlled multiple threshold debounce circuits or algorithms. In one embodiment, an input-controlled multiple threshold debounce system is configured to receive an input signal and to control an output. An analysis subsystem may determine when an input signal exceeds an assertion threshold and may assess at least one additional characteristic of the input signal. Supervisory logic in communication with the analysis subsystem may select a variable delay based on the at least one additional characteristic of the input signal. A delay subsystem controlled by the supervisory logic may assert a first signal after the input signal remains above the assertion threshold for longer than the variable delay. Finally, a system output may be configured to receive the first signal and may be configured to assert the debounce system output based on the first signal.
    Type: Grant
    Filed: August 11, 2016
    Date of Patent: June 13, 2017
    Assignee: Schweitzer Engineering Laboratories, Inc.
    Inventors: Tracey G. Windley, Veselin Skendzic
  • Patent number: 9673805
    Abstract: A method and system for reducing leakage current in a testing circuit are provided. Embodiments include a testing circuit that includes a digital buffer that includes a first transistor operatively coupled to a second transistor, where a drain of the first transistor is operatively coupled to a source of the second transistor. The second transistor is switched into cutoff mode. The digital buffer also includes a reference voltage generation circuit. The reference voltage generation circuit is operatively connected to the drain of the first transistor and the source of the second transistor. The reference voltage generation circuit is configured to reduce the leakage current in the digital buffer.
    Type: Grant
    Filed: August 21, 2014
    Date of Patent: June 6, 2017
    Assignee: International Business Machines Corporation
    Inventors: Sarveswara Bade, Shiu Chung Ho, Marcel A. Kossel, Pradeep Thiagarajan
  • Patent number: 9667255
    Abstract: Circuits and corresponding methods that provide for selection among multiple different positive and/or multiple different negative FET gate drive voltages for FETs in which well-tuned gate drive voltages are needed or desirable for optimal results in a radio frequency integrated circuit. Embodiments include FET gate drive variable voltage generator configurations which provide multiple different positive and/or multiple different negative FET gate drive voltages. In alternative embodiments, an IC may include multiple positive voltage generators and/or multiple negative voltage generators, each voltage generator providing an output voltage different from at least one other voltage generator. The voltage generators include charge pump based circuits and digital-to-analog converters. Each FET device requiring a well-tuned gate drive voltage is selectably coupled to at least one set of positive and negative voltage generators.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: May 30, 2017
    Assignee: Peregrine Semiconductor Corporation
    Inventor: Robert Mark Englekirk
  • Patent number: 9660513
    Abstract: A control circuit is driven by a driving voltage (VOC) generated by a generator circuit, and outputs a control signal. A drive circuit is driven by a driving voltage (VOD) generated by another generator circuit, and turns a switching element inside a switching circuit on or off by supplying, to the switching circuit, a drive signal based on the control signal. During activation of a switching device, a voltage generation controller detects a voltage value of the output voltage (VOC) of the generator circuit, and allows activation of the other generator circuit after verifying that the detected voltage value is at or above a designated threshold.
    Type: Grant
    Filed: March 24, 2014
    Date of Patent: May 23, 2017
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Kohtaroh Kataoka, Masaru Nomura, Takeshi Shiomi, Shuji Wakaiki, Akihide Shibata, Hiroshi Iwata
  • Patent number: 9653147
    Abstract: An apparatus includes an interface and a circuit. The interface may be configured to generate a memory signal that carries read data from a memory channel. The circuit may be configured to modify a read signal that transfers the read data across a read line to a memory controller. A filter may delay the memory signal to generate a delayed signal. A driver generally amplifies the memory signal to generate the read signal. The driver may modify the read signal with a de-emphasis on each pull up of the memory signal and a pre-emphasis on each pull down of the memory signal based on the delayed signal.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: May 16, 2017
    Assignee: INTEGRATED DEVICE TECHNOLOGY INC.
    Inventors: Yanbo Wang, Praveen Rajan Singh, Yue Yu, Craig DeSimone
  • Patent number: 9621162
    Abstract: A high side driver component for generating a drive signal at an output thereof for driving a high side switching device within a high voltage driver circuit. The high side driver component is arranged to operate in at least one reduced slew rate mode in which at least one drive stages is arranged to be in a non-drive state, and the high side driver component further comprises at least one discharge protection component arranged to, when the high side driver component is operating in the at least one reduced slew rate mode, receive an indication of the high voltage driver circuit being in an idle state, and cause the second switching device within the at least one drive stage in a non-drive state to be turned on, in response to the indication of the high voltage driver circuit being in an idle state.
    Type: Grant
    Filed: December 1, 2014
    Date of Patent: April 11, 2017
    Assignee: NXP USA, Inc.
    Inventors: Kamel Abouda, Estelle Huynh, Thierry Michel Laplagne
  • Patent number: 9614517
    Abstract: An adaptive driver includes a gate driver having at least one driving transistor for driving a control node of switching transistor(s) that includes an output node (OUT) which provides Vout. An adjustable current source is in series with the driving transistor, a high pass filter (HPF) is between OUT and ground for detecting a slew rate of the switching transistor and outputting a voltage pulse (Vslp) output having a peak voltage amplitude at least monotonically reflecting a slope of Vout during switching. Detection signal processing circuitry is coupled to the output of the HPF for processing Vslp and slew rate control circuitry has an input coupled to the output of the detection signal processing circuitry. The output of the slew rate control circuitry is coupled to the current source for controlling its current level for changing the slew rate of the switching transistor to provide a desired slew rate range.
    Type: Grant
    Filed: July 10, 2015
    Date of Patent: April 4, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Kannan Krishna
  • Patent number: 9583209
    Abstract: Various implementations described herein are directed to an integrated circuit having high density memory architecture. The integrated circuit may include a plurality of bank arrays having multiple segments of bitcells configured to share local control. The integrated circuit may include a plurality of control lines coupling the local control to each of the multiple segments of bitcells. In some instances, during activation of a segment of bitcells by the local control via one of the control lines, another segment of bitcells may be deactivated by the local control via another of the control lines.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: February 28, 2017
    Assignee: ARM Limited
    Inventors: Rajiv Kumar Roy, Fakhruddin Ali Bohra, Manish Trivedi, Sumant Kumar Thapliyal, Vikash
  • Patent number: 9571771
    Abstract: A data transfer circuit includes a plurality of data transfer sections which transfer pixel signals of pixel columns which are different from each other, wherein the plurality of data transfer sections include transfer lines which transfer the pixel signals read from the pixel columns of an image sensor; and amplifying sections which amplify the pixel signals output from the transfer lines, and wherein the plurality of data transfer sections are connected to each other in series.
    Type: Grant
    Filed: September 12, 2013
    Date of Patent: February 14, 2017
    Assignee: Sony Corporation
    Inventor: Shingo Sanada
  • Patent number: 9548723
    Abstract: One or more resistors or resistances are integrated in a 7-bit DVR or PVCOM integrated circuit. A 7-bit DVR or PVCOM integrated circuit includes a 7-bit DAC. The integrated resistors or resistances (R1, R2, or RSET, or any combination) reduces the number of external components, reduces the number of pins, and increases the accuracy of the DVR or PVCOM circuit. The least significant bit (LSB) of the DAC depends only on ratios of internal resistors, which can be made very accurate and independent of temperature.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: January 17, 2017
    Assignee: IML International
    Inventors: Alberto Giovanni Viviani, ChinFa Kao, Chiayao S. Tung
  • Patent number: 9491394
    Abstract: In one embodiment, an internal buffer may be provided within an integrated circuit (IC) to convert a signal to an output current to be output via a pin of the IC, under control of a switch which can be controlled based on a configuration setting of the IC, and may selectively directly couple the signal to the pin when the IC is coupled to an external driver circuit.
    Type: Grant
    Filed: April 16, 2014
    Date of Patent: November 8, 2016
    Assignee: Silicon Laboratories Inc.
    Inventors: András Vince Horvath, Abdulkerim L. Coban, Pio Balmelli, Ramin Khoini-Poorfard, Alessandro Piovaccari
  • Patent number: 9484921
    Abstract: First and second devices may simultaneously communicate bidirectionally with each other using only a single pair of LVDS signal paths. Each device includes an input circuit and a differential output driver connected to the single pair of LVDS signal paths. An input to the input circuit is also connected to the input of the driver. The input circuit may also receive an offset voltage. In response to its inputs, the input circuit in each device can use comparators, gates and a multiplexer to determine the logic state being transmitted over the pair of LVDS signal paths from the other device. This advantageously reduces the number of required interconnects between the first and second devices by one half.
    Type: Grant
    Filed: May 9, 2013
    Date of Patent: November 1, 2016
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 9419616
    Abstract: An LVDS driver includes a plurality of differential signal generators to receive adjustment signals generated by a slew rate adjusting unit and generate a differential signal for transmission to a plurality of LVDS receivers through a transmission line. The slew rate adjusting unit receives slew rate control signals from a slew rate control signal setting unit, and a slew rate of the differential signal is adjusted based on the adjustment signals.
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: August 16, 2016
    Assignee: RICOH COMPANY, LTD.
    Inventors: Yohichi Wada, Tohru Kanno
  • Patent number: 9379743
    Abstract: Described is an apparatus for boosting a transition edge of a signal, the apparatus comprises: a logic to provide input data having a Unit Interval (UI); a programmable delay unit to receive the input data and operable to delay the input data by a fraction of the UI to generate a delayed input data; and one or more drivers to drive the input data and the delayed input data to a node.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: June 28, 2016
    Assignee: Intel Corporation
    Inventors: Shenggao Li, Xiaoqing Wang
  • Patent number: 9362877
    Abstract: An electronic component includes: a first amplifier configured to amplify one of differential signals; a second amplifier configured to amplify another one of the differential signals; a sensor configured to measure voltages of a first output signal outputted from the first amplifier and a second output signal outputted from the second amplifier; and a controller configured to control, based on the voltages measured by the sensor, either one or both of a current and a resistance value of the first amplifier so that a common voltage of the first output signal and a common voltage of the second output signal are approximate to each other.
    Type: Grant
    Filed: May 12, 2014
    Date of Patent: June 7, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Masazumi Maeda, Yoshiharu Yoshizawa
  • Patent number: 9219479
    Abstract: A through silicon via (TSV) repair circuit of a semiconductor apparatus is provided. The TSV repair circuit includes a first chip, at least one second chip, at least two TSVs, at least two data path circuits, and an output logic circuit. Each data path circuit includes an input driving circuit, a short-circuit detection circuit, a bias circuit, and a leakage current cancellation circuit. The input driving circuit transforms an input signal into a pending signal and transmits the pending signal to a first terminal of the corresponding TSV. The short-circuit detection circuit detects a short circuit between the corresponding TSV and a silicon substrate according to the input signal and the first terminal of the TSV and generates a short-circuit detection output signal. The leakage current cancellation circuit prevents a leakage current produced by a first level voltage from entering the silicon substrate according to the short-circuit detection output signal.
    Type: Grant
    Filed: April 21, 2013
    Date of Patent: December 22, 2015
    Assignee: Industrial Technology Research Institute
    Inventors: Pei-Ling Tseng, Keng-Li Su
  • Patent number: 9209811
    Abstract: A semiconductor integrated circuit device comprises I/O cells arranged around a core region. Each of the I/O cells comprises a level shifter circuit, an I/O logic circuit, and an I/O buffer circuit. An I/O logic region in which the I/O logic circuit is arranged and an I/O buffer region in which the I/O buffer circuit is arranged overlap with a region in which a pad for the I/O cell is arranged. The I/O logic region and the I/O buffer region are arranged side by side in a direction parallel to a side of the core region.
    Type: Grant
    Filed: August 15, 2014
    Date of Patent: December 8, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Kazuo Sakamoto, Naozumi Morino, Kazuo Tanaka, Hiroyasu Ishizuka
  • Patent number: 9106549
    Abstract: An Ethernet communication circuit includes: a current source; a first transistor coupled between a first node and a third node, and having a control terminal coupled with a first signal pin; a second transistor coupled between the first node and a fourth node, and having a control terminal coupled with a second signal pin; a third transistor coupled between a second node and the fourth node, and having a control terminal coupled with a third signal pin; a fourth transistor coupled between the second node and the third node, and having a control terminal coupled with a fourth signal pin; a first switch coupled between the third node and the current source; a second switch coupled between the fourth node and the current source; and a transconductance circuit for generating an output voltage according to the current passing through the first node and the current passing through the second node.
    Type: Grant
    Filed: February 19, 2013
    Date of Patent: August 11, 2015
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventor: Shan-Chih Tsou
  • Patent number: 9094246
    Abstract: A circuit may include a splitter, a controller, and a termination. The splitter may generate, based upon input signals, a plurality of output signals, wherein at least one of the input signals is in more than one different modes at different times and the output signals comprise a first set of the output signals generated based upon comparison of pairs of signals of the first set against each other and a second set of the output signals generated based upon comparison of each signal of the second set to a predetermined threshold voltage. The controller may determine, based upon the second set of the output signals, whether the input signals are in the one of the more than one different modes to generate one or more control signals. The termination may connect loads to each of the input lines, based upon the one or more control signals.
    Type: Grant
    Filed: April 14, 2014
    Date of Patent: July 28, 2015
    Assignee: ANALOG DEVICES GLOBAL
    Inventors: Xiaoming Chi, Bin Huo