Abstract: A vehicle, slew rate control circuit and method of operating an electric motor of a vehicle. The slew rate control circuit is between a gate driver of the vehicle and an inverter of the vehicle. The slew rate control circuit includes a first branch between the gate driver and the inverter, wherein the inverter provides an electrical signal output to an electric motor of the vehicle, and a second branch between the gate driver and the inverter in parallel with the first branch, wherein current flows through the first branch during a first time period and through the second branch during a second time period, wherein the flow of the current controls a slew rate of the electrical signal output by the inverter to the electric motor.

Abstract: A low voltage differential signaling (LVDS) receiver includes a receiver circuit including first and second inputs coupled to first and second conductive pads, respectively, and an output coupled to an input of a digital controller, and a dummy transmitter circuit including a first input coupled to receive a common mode voltage (VCM) tune signal, a second input coupled to a loopback input signal, a third input coupled to a loopback enable signal, a first output coupled to the first input of the receiver circuit, and a second output coupled to the second input of the receiver circuit. When a test mode of operation is enabled, the digital controller asserts the loopback enable signal, and the dummy transmitter circuit generates a pair of test differential signals based on the VCM tune signal, wherein the VCM tune signal varies to test the LVDS receiver over a range of common mode voltages.

Abstract: An output circuit includes an output driver, a voltage regulator, a control circuit and a charge pump circuit. The output driver includes a signal input terminal, a signal output terminal and a first power receiving terminal. The voltage regulator is coupled to the first power receiving terminal of the output driver. The control circuit is coupled to the signal input terminal of the output driver. The charge pump circuit is coupled to the control circuit and the first power receiving terminal of the output driver.

Abstract: Provided are a display panel and a display device. An isolation dam is provided in a peripheral area of the display panel. The display panel includes: a display functional layer comprising a plurality of display signal traces; and a touch-control functional layer comprising a plurality of touch-control signal traces. On the binding side, there are a first boundary and a second boundary, and a first trace area located between the first boundary and the second boundary, the first boundary is closer to the display area than the second boundary. In the first trace area, the touch-control signal trace is arranged along a first direction and are led out from the binding circuit and connected to the touch-control pattern via the isolation dam and the first trace area in sequence, the display signal trace is arranged along a second direction and intersects with the touch signal trace.

Abstract: An integrated circuit with galvanic isolation is described herein. In accordance with one example, the circuit comprises a galvanic insulation barrier including a first isolation element configured to separate a first isolation domain from a second isolation domain and a first channel configured to transmit—in a first mode of operation and across the first isolation element—a logic signal from a first input in the first isolation domain to a first output in the second isolation domain. The first channel is further configured to transmit—in a second mode of operation and across the first isolation element—a serial data stream from the first input to a logic circuit in the second isolation domain, wherein the logic circuit is configured to receive—in the second mode of operation—the serial data stream and to store configuration information included in the serial data stream in a memory.

Abstract: Various embodiments of the teachings herein include a switching device for a DC voltage grid. The device may include: a first controllable semiconductor switch with a control contact and two load contacts; and a controller for the first switch using a control signal at the control contact. The controller is configured to: actuate the first switch using a control pulse that causes the electrical conductivity of the semiconductor switch to reduce for less than 1 ms; apply a current to a test circuit including the first switch; ascertain a first value representing the voltage or the change in voltage across the first switch as a result of the control pulse and the applied current; analyzing the first value; and generating a signal that represents the functionality of the first semiconductor switch.

Abstract: A circuit includes a power management circuit configured to receive at least a first or a second control signal, and to supply at least a first, second or a third supply voltage. The first control signal has a first voltage swing. The second control signal has a second voltage swing. The power management circuit includes a first level shifter circuit configured to generate a first level shifted signal in response to the first control signal, and a first header circuit coupled to at least the first level shifter circuit, a first voltage supply and a second voltage supply. The first header circuit is configured to supply the first supply voltage of the first voltage supply to the first node in response to the first control signal, and to supply the second supply voltage of the second voltage supply to the second node in response to the first level shifted signal.

Abstract: There is provided an optical communication device having a silicon photonics (SiPh) component configured to perform an optical communication function; a complementary metal oxide semiconductor (CMOS) drive circuit coupled to the SiPh device for operation thereof; and one or more controllably adjustable CMOS impedance circuits coupled to the SiPh component and the electrical drive circuit. In the optical communication device, impedances of each of the CMOS impedance circuits can be adjustable over a respective limited range. The limited range may be designed and configured based at least in part on an anticipated amount of variation in electrical characteristics of the SiPh component, the CMOS electrical drive circuit, or a combination thereof. Such variation may be anticipated due to manufacturing variability.

Abstract: An integrated circuit includes an output pad, and I/O driver that drives data to the output pad, and a predriver that controls the I/O driver. The integrated circuit includes maximum voltage generator that receives a first supply voltage and a second supply voltage and outputs to the predriver a maximum voltage corresponding to the higher of the first supply voltage and the second supply voltage.

Abstract: A digital isolator includes: an edge detection circuit configured to output a first detection signal and a second detection signal; a driving buffer circuit configured to output a first edge signal and a second edge signal; an isolation element configured to output a first edge signal and a second edge signal; a receiving inverter circuit configured to output a first reception signal and a second reception signal; a latch circuit configured to latch data based on the pulse of the first received signal and the pulse of the second received signal, and to output an output signal to an output terminal according to the data; a switch circuit configured to switch a state of conduction between the reference potential and the first output and a state of conduction between the reference potential and the second output; and a control circuit configured to control a switching operation.

Abstract: A differential communication driver circuit includes a drive unit that drives differential signal lines connected via capacitors by a source current and a sink current. When a noise detection unit detects that in-phase noise is applied to the differential signal lines, a drive assisting unit maintains an amplitude of a differential signal output to the differential signal lines by increasing a current drive capability of the sink current.

Abstract: A serial bus repeater includes a port circuit and a low power state detection circuit. The port circuit is configured to communicate via a serial bus. The low power state detection circuit includes a power state transaction identification circuit and a bus state identification circuit. The power state transaction identification circuit is configured to identify a power state transaction on the serial bus. The power state transaction is indicative of entering a reduced power state. The bus state identification circuit is configured to identify a value of termination resistance on the serial bus that is indicative of entering the reduced power state.

Abstract: A semiconductor device, includes: a first first-conductivity-type transistor supplied with a first power source voltage and controlled by an output signal of a first input inverter; a second first-conductivity-type transistor supplied with the first power source voltage and controlled by an output signal of a second input inverter that inverts an output signal of the first input inverter; a first and a second second-conductivity-type transistor supplied with a second power source voltage; and a third and a fourth first-conductivity-type transistor that are connected in parallel either between the first first-conductivity-type transistor and the first second-conductivity-type transistor or between the second first-conductivity-type transistor and the second second-conductivity-type transistor, and that are configured to isolate either a first node connected to the first first-conductivity-type transistor or a second node connected to the second first-conductivity-type transistor from the second power source vo

Abstract: An adapter circuit board includes an input end and an output end. The input end includes an input portion for connecting with a first connector header. The output end includes an output portion and an insertion portion for being inserted into a second connector. The output portion is used for directly or indirectly electrically connecting with cables to transmit high-speed signals. This setting improves the signal integrity of high-speed signals during transmission and therefore improves the quality of data transmission. In addition, the present disclosure also relates to a first connector and a connector assembly having the adapter circuit board.

Abstract: A short-circuit mitigation device for use in an electrolytic cell (101) is disclosed. The device comprises a switch (302) connected in parallel with a damping load (502). The switch is disposed between a contact (102) and an electrode (106) of the cell (101) to selectively provide an electrical conduction path between the contact and the electrode. The switch comprises a plurality of metal-oxide-semiconductor field-effect transistors (MOSFETs) (402) connected in parallel. The device further comprises a switch controller (306) operably associated with the switch (302) to monitor electric current (308) through the switch and to generate a toggle signal (309) to toggle the switch (302) from a conductive closed state to a non-conductive open state when the electric current exceeds a first threshold value.

Abstract: An image display apparatus is disclosed. The image display apparatus includes a signal processing device having a transceiver that includes a current sweep circuit configured to output a plurality of sweep currents, a current selector connected to the current sweep circuit and configured to select a predetermined current from the plurality of sweep currents based on comparison with a reference voltage, and a comparator configured to compare a voltage output from the current selector with the reference voltage. Accordingly, a constant output voltage level can be obtained.

Abstract: A common gate input circuit for III/V D-mode Buffered FET Logic (BFL) maximizes the dynamic range to drive a level shift section to set the proper voltage levels to switch the BFL and allows for decoupling of the switch point from the dynamic range. A common gate switching section includes a D-mode FET (FET1) configured as a load and a D-mode FET (FET2) configured as a common gate connected in series between high and low supplies Vdd and Vee1 (typically ground potential). The gate electrode of FET2 is coupled to Vee1 and the source electrode of FET2 is driven by the external digital signals. This eliminates the additional supply Vss, thus maximizing the dynamic range of the section to switch between Vdd and Vee1 and decouples the dynamic range from the switch point. An input level shift section may shift the Data In to the source electrode of FET2 to shift the switch point and to present a high input impedance.

Abstract: A differential signal driver may include a driver circuit and a feedback loop. The driver circuit may include a first output node coupled to a first termination node for receiving a first termination bias voltage, a second output node coupled to a second termination node for receiving a second termination bias voltage, and a bias network connected to the second output node and to the second termination node. The feedback loop may include a first feedback resistor connected to the first output node at a first end of the first feedback resistor, a second feedback resistor connected to the second output node at a first end of the second feedback resistor, and a feedback amplifier configured to provide a feedback correction current from a common mode voltage to a node within the line from the first output node to the first termination node.

Abstract: A low-voltage differential signaling receiver is provided that amplifies a differential input voltage to produce a differential output voltage. A signal distortion circuit that detects a distortion in a differential output voltage to assert a signal detection signal that adjusts a gate voltage of a pair of load transistors to reduce the distortion. The load transistors are selectively diode connected to reduce power consumption.

Abstract: A transmitter circuit is provided. The transmitter circuit has a first transmission node and a second transmission node and includes a first resistor, a second resistor, a third resistor, a fourth resistor, and a driving circuit. The driving circuit includes a first transistor group, a second transistor group, a third transistor group, and a fourth transistor group. The first resistor is coupled between a first output terminal and the first transmission node. The second resistor is coupled between a second output terminal and the second transmission node. The third resistor is coupled between a third output terminal and the first transmission node. The fourth resistor is coupled between a fourth output terminal and the second transmission node. The first, second, third, and fourth transistor groups are coupled to a first and a second reference voltages and electrically connected to the first, second, third, and fourth output terminals, respectively.

Abstract: A bidirectional level shifter circuit includes first and second driver circuits, first and second comparators, and a control circuit. The first driver circuit includes a first driver output and a first enable input. The second driver circuit includes a second driver output and a second enable input. The first comparator includes a first comparator output, a first reference input, and a first comparator input that is coupled to the second driver output. The second comparator includes a second comparator output, a second reference input, and a second comparator input is coupled to the first driver output. The control circuit includes a first control input coupled to the first comparator output, a second control input coupled to the second comparator output, a first control output coupled to the first enable input, and a second control output coupled to the second enable input.

Abstract: An encapsulation block for a digital signal processing (DSP) block. The encapsulation block includes DSP block having an input terminal, an output terminal, and an input clock. The encapsulation block also includes pacing control network operatively connected with the input terminal, the output terminal, and the input clock of the DSP block. The input terminal of the DSP block is configured to receive a samples-in data stream inputted at a predefined clock period defined by the input clock. The output terminal of the DSP block is configured to receive a samples-out data stream outputted at a predefined paced parameter. The pacing control network is configured to control data flow at the samples-in data stream and the samples-out data stream independently of the DSP block.

Abstract: Methods, systems, and devices for postamble for multi-level signal modulation are described. One or more channels of a bus may be driven with a multi-level signal having at least two (2) distinct signal levels. After driving the bus with the multi-level signal, at least one (1) of the channels may be terminated. In some examples, the channel may be terminated to a relatively high signal level. Before termination, the channel may be driven with a postamble having an intermediate signal level. Driving the channel to an intermediate signal level before terminating the channel (e.g., to a high signal level) may avoid maximum transitions of the signal. For example, transitions between a lowest potential signal level and the high signal level (e.g., the termination level) may be avoided.

Abstract: A Controller Area Network (CAN) system, method, and circuit are provided with a dual mode bus line termination circuit connected between signal lines of a serial bus and optimized for both differential and single-ended communication modes over the serial bus, where the dual mode bus line termination circuit includes first and second resistance termination paths connected in parallel between first and second bus wires of the serial bus to provide an odd mode termination impedance (RODD) that matches an impedance of the serial bus when operating in the differential communication mode, and to also provide an even mode termination impedance (REVEN) that matches an impedance of the serial bus when operating in the single-ended communication mode.

Abstract: A post-driver with low voltage operation and electrostatic discharge protection. In one embodiment, a post-driver structure includes a drive unit including a pull-up driver and a pull-down driver, a pad connected to an external resistance, and an output node connected between the pull-up driver and the pull-down driver, the output node configured to connect to a comparator for impedance calibration of the drive unit. The post-driver structure also includes an operational amplifier connected to a first transistor and the pad in a closed loop configuration, the operational amplifier further connected to a second transistor to form a current mirror circuit between the operational amplifier and the drive unit, wherein the current mirror circuit replicates a voltage at the pad with a voltage at the output node for the impedance calibration.

Abstract: One example discloses a signal driver circuit, including: an input configured to receive an input signal; an output configured to transmit an output signal; a low drop-out voltage regulator (LDO) having a regulated voltage output; a set of voltage-modulated amplifiers having a first input coupled to the regulated voltage output, and a second input configured to receive the input signal; wherein the voltage-modulated amplifier is configured to amplify the input signal and transmit an amplified input signal on the output of the signal driver circuit; a de-emphasis controller, including a set of de-emphasis levels; wherein the de-emphasis controller is configured to selectively switch-on a first subset of the set of voltage-modulated amplifiers and switch-off a second subset of the set of voltage-modulated amplifiers based on the de-emphasis levels.

Abstract: A memory device and a method of operating the same are disclosed. In one aspect, the memory device includes a plurality of memory arrays and a controller including a plurality of buffers including a first buffer connected to a first memory array and a second buffer connected to a second memory array. The first and second memory arrays are disposed on opposing sides of the controller. The memory device can include a first wire extending in a first direction and connected to the first buffer, a second wire extending in the first direction and connected to the second buffer, and a third wire connected to the first and second wires and extending in a second direction that is substantially perpendicular to the first direction. The third wire can be electrically connected to the controller, and respective lengths of the first wire and the second wire are substantially the same.

Abstract: In examples, a system includes a differential input device having a first input and a second input. The system includes a window generator configured to output, at a first output, a first voltage above a reference voltage and a second voltage, at a second output, below the reference voltage. The system includes a multiplexer coupled to the first output and the second output, the multiplexer configured to receive the first voltage, the second voltage, and an input voltage. The system includes a selector coupled to the multiplexer and configured to select the first voltage, the second voltage, or the input voltage based on a value of the input voltage, where the selector is configured to cause the multiplexer to provide the selected voltage to the first input of the differential input device, where a voltage source provides the reference voltage to the second input of the differential input device.

Abstract: Provided is a storage system including a decoupling device having a plurality of unit capacitors. The storage system includes a storage device, a control device, and a decoupling device disposed on a circuit substrate. The storage device is configured to receive and store data from the control device. The control device is configured to generate an inner voltage. The decoupling device is connected to the control device and decouples the inner voltage. The decoupling device includes a plurality of unit capacitors constituting a plurality of decoupling capacitors. Each of the unit capacitors includes a plurality of capacitor elements, a first terminal, and a second terminal. Some of the unit capacitors are selectively connected with each other to constitute the decoupling capacitors having various capacitances.

Abstract: Methods and systems for selecting voltage for a substrate connection of a bypass switch include a bulk voltage generation circuit coupled externally to the regulator. The bulk voltage generation circuit is configured to control selection of a voltage from among an Input/Output (I/O) supply voltage and a core supply voltage for a substrate connection of a bypass switch of the regulator. The bulk voltage generation circuit is configured to select the voltage for the substrate connection of the bypass switch based on a mode of operation of the regulator and at least one of a presence or an arrival sequence of the I/O supply voltage and the core supply voltage.

Abstract: A signal processing apparatus includes a signal processing circuit configured to process a signal obtained from a voltage bus, a high voltage circuit configured to withstand a voltage stress when a high voltage is applied to the voltage bus, and a bypass circuit configured to bypass the high voltage circuit when a low voltage is applied to the voltage bus.

Abstract: A single wire digital communication system for use with an ultrasonic surgical instrument and an ultrasonic surgical instrument including a single wire digital communication system. The single wire digital communication system includes first transmitter logic buffer and first receiver logic buffer operably coupled to a first single wire device via a first single wire communication bus. The single wire digital communication system also includes a first differential transceiver operational amplifier operably coupled to the first transmitter logic buffer via a first transmitter signal line and operably coupled to the first receiver logic buffer via a first receiver signal line. A second differential transceiver operational amplifier is operably coupled to the first differential transceiver operational amplifier via at least one differential bus. A second single wire device is operably coupled to the differential bus and configured to communicate with the first single wire device.

Abstract: A data output buffer includes a first driver configured to drive a data input/output (I/O) pad according to an input signal and allow data drivability to be controlled according to an impedance calibration code and a second driver configured to perform a de-emphasis operation on the data I/O pad and allow de-emphasis drivability to be controlled according to the impedance calibration code.

Abstract: The interface circuit includes a first transistor, a second transistor, a first switch, a first logic circuit and a second logic circuit. The first transistor is controlled by a enable signal. The second transistor is controlled by a first control signal. The first switch is coupled between a second end of the first transistor and the output end of the interface circuit, wherein the first switch is controlled by a second control signal. The first logic circuit generates the first control signal according to the enable signal and at least one indication signal. The second logic circuit generates the second control signal according to the first control signal and the enable signal.

Abstract: A playback device includes a speaker, a controller, a first switch circuit, and a second switch circuit. The speaker has a first terminal and a second terminal. The controller is configured to output a first audio signal and a second audio signal. The controller is coupled to the first terminal of the speaker, and is configured to transmit the first audio signal to the speaker. The second switch circuit is coupled between the second terminal of the speaker and the controller, and is coupled to the first switch circuit. The second switch circuit is configured to transmit the second audio signal from the controller to the speaker when the first switch circuit is turned on.

Abstract: A device may include a ZQ calibration circuit. The ZQ calibration circuit may include a first register configured to store a first impedance code generated responsive to a ZQ calibration command. The ZQ calibration circuit may also include a second register configured to store a shift value. Further, the ZQ calibration circuit may include a compute block configured to generate a second impedance code based on the first impedance code and the shift value. Systems and related methods of operation are also described.

Abstract: A lower-power driving display device and a driving method. The driving method of the display device includes dividing the plurality of output buffers of the data driver into a plurality of output buffer groups, each of the plurality of output buffers being configured to apply the data voltage to each of the plurality of data lines connected with the display panel, and determining the magnitude of a bias current supplied to an output buffer on the basis of a pattern of a data voltage output by the output buffer which belongs to each of the plurality of divided output buffer groups.

Abstract: A circuit includes first through fourth transistors and a device. The first transistor has a control input and first and second current terminals. The control input provides a first input to the circuit. The second transistor has a control input and first and second current terminals. The control input provides a second input to the circuit. The third transistor has a control input and first and second current terminals. The fourth transistor has a control input and first and second current terminals. The second current terminal of the fourth transistor is coupled to the second current terminal of the third transistor, and the control input of the fourth transistor is coupled to the first current terminals of the first and second transistors. The device is configured to provide a fixed voltage to the control input of the third transistor.

Abstract: Memories for receiving or transmitting voltage signals might include an input or output buffer including a first stage having first and second inputs and configured to generate a current sink and source at its first and second outputs responsive to a voltage difference between its first and second inputs, and a second stage having a first input connected to the first output of the first stage, a second input connected to the second output of the first stage, a first voltage signal node connected to its first input through a first resistance, and a second voltage signal node connected to its second input through a second resistance, wherein a first inverter is connected in parallel with the first resistance, a second inverter is connected in parallel with the second resistance, and a pair of cross-coupled inverters are connected between the first voltage signal node and the second voltage signal node.

Abstract: A power amplifier circuit includes a first power supply terminal electrically connected to a first power amplifier; a second power supply terminal electrically connected to a second power amplifier subsequent to the first power amplifier; a first external power supply line configured to electrically connect a power supply circuit configured to output a power supply potential corresponding to an amplitude level of a high-frequency input signal and the first power supply terminal; and a second external power supply line configured to electrically connect the power supply circuit and the second power supply terminal. An inductance value of the first external power supply line is higher than an inductance value of the second external power supply line.

Abstract: The energy storage system includes battery cells, a subrack, a backplane, and a battery management system BMS. The subrack reserves a plurality of battery cell slots, the battery cells are connected to the backplane through the battery cell slots. The backplane is installed in the subrack, a first power terminal is reserved at a position corresponding to the battery cell slot on the backplane, and a plug-in power terminal is formed by a second power terminal of the battery cell together with the first power terminal. A power circuit, a sampling circuit, and an equalizer circuit are integrated into the backplane, and the power circuit, the sampling circuit, and the equalizer circuit are connected after the second power terminal is plugged and docked with the first power terminal. The BMS is connected to the backplane for managing the energy storage system.

Abstract: Disclosed is a method for deadtime optimization in a half-bridge switch or full-bridge switch wherein high-side and low-side switches comprise GaN transistors; a circuit for implementing the method; and a power switching system comprising a GaN half-bridge or a GaN full-bridge and a deadtime optimization system. The circuit comprises a drain current bump filter for generating a current charge output; and circuit elements for comparing the current charge output to a reference current charge Coss and generating a deadtime adjust signal. The deadtime adjust signal may be used to adjust deadtime to reduce or minimize deadtime, and deadtime losses, while avoiding cross-conduction.

Abstract: A chip package includes an interposer comprising a silicon substrate, multiple metal vias passing through the silicon substrate, a first interconnection metal layer over the silicon substrate, a second interconnection metal layer over the silicon substrate, and an insulating dielectric layer over the silicon substrate and between the first and second interconnection metal layers; a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip over the interposer; multiple first metal bumps between the interposer and the FPGA IC chip; a first underfill between the interposer and the FPGA IC chip, wherein the first underfill encloses the first metal bumps; a non-volatile memory (NVM) IC chip over the interposer; multiple second metal bumps between the interposer and the NVM IC chip; and a second underfill between the interposer and the NVM IC chip, wherein the second underfill encloses the second metal bumps.

Abstract: A display control system includes a plurality of driver circuits connected in series. A driver circuit among the plurality of driver circuits includes a receiver, a duty cycle correction circuit and a transmitter. The receiver is configured to receive a first signal from a previous driver circuit among the plurality of driver circuits. The duty cycle correction circuit, coupled to the receiver, is configured to adjust a duty cycle of the first signal to generate a second signal. The transmitter, coupled to the duty cycle correction circuit, is configured to transmit the second signal to a next driver circuit among the plurality of driver circuits.

Abstract: In examples, a system includes a differential input device having a first input and a second input. The system includes a window generator configured to output, at a first output, a first voltage above a reference voltage and a second voltage, at a second output, below the reference voltage. The system includes a multiplexer coupled to the first output and the second output, the multiplexer configured to receive the first voltage, the second voltage, and an input voltage. The system includes a selector coupled to the multiplexer and configured to select the first voltage, the second voltage, or the input voltage based on a value of the input voltage, where the selector is configured to cause the multiplexer to provide the selected voltage to the first input of the differential input device, where a voltage source provides the reference voltage to the second input of the differential input device.

Abstract: A single wire digital communication system for use with an ultrasonic surgical instrument and an ultrasonic surgical instrument including a single wire digital communication system. The single wire digital communication system includes first transmitter logic buffer and first receiver logic buffer operably coupled to a first single wire device via a first single wire communication bus. The single wire digital communication system also includes a first differential transceiver operational amplifier operably coupled to the first transmitter logic buffer via a first transmitter signal line and operably coupled to the first receiver logic buffer via a first receiver signal line. A second differential transceiver operational amplifier is operably coupled to the first differential transceiver operational amplifier via at least one differential bus. A second single wire device is operably coupled to the differential bus and configured to communicate with the first single wire device.

Abstract: Apparatuses and methods for calibrating adjustable impedances of a semiconductor device are disclosed in the present application. An example apparatus includes a register configured to store impedance calibration information and further includes programmable termination resistances having a programmable impedance. The example apparatus further includes an impedance calibration circuit configured to perform a calibration operation to determine calibration parameters for setting the programmable impedance of the programmable termination resistances. The impedance calibration circuit is further configured to program the impedance calibration information in the register related to the calibration operation.

Abstract: A low voltage differential signal driver includes an output driver including an N-channel source follower, a P-channel source follower, and a plurality of differential switching circuits, a plurality of high-potential output control circuits to control a terminal of the N-channel source follower of the output driver to make a high-potential output of the differential output from the output driver have a prescribed value, a plurality of low-potential output control circuits to control a terminal of the P-channel source follower of the output driver to make a low-potential output of the differential output from the output driver have a prescribed value, a high-potential generation circuit used in common for the plurality of high-potential output control circuits, and a low-potential generation circuit used in common for the plurality of low-potential output control circuits. The output driver outputs a differential output, and one of the plurality of high-potential output control circuits.

Abstract: A semiconductor system includes a semiconductor apparatus and an external apparatus. The semiconductor apparatus includes a calibration code generating circuit, a code shifting circuit, and a main driver. The calibration code generating circuit performs a calibration operation to generate a calibration code. The code shifting circuit changes, based on a shifting control signal, a value of the calibration code. A resistance value of the main driver may be set on the basis of the calibration code and a shifted calibration code. The external apparatus generates the shifting control signal based on the resistance value of the main driver.

Abstract: A termination for a high-frequency transmission line includes a first resistor that has a first terminal coupled to a first end of a transmission line and a second terminal coupled to a first input/output pad, and a second resistor that has a first terminal coupled to the first input/output pad. The first resistor and the second resistor may provide a combined resistance that matches a nominal value of a characteristic impedance of the transmission line. The apparatus may include a third resistor having a first terminal coupled to a second end of a transmission line, and a second terminal coupled to a second input/output pad, and a fourth resistor having a first terminal coupled to the second input/output pad. The third resistor and the fourth resistor may provide a combined resistance that matches the nominal value of the characteristic impedance of the transmission line.