Field-effect Transistor Patents (Class 326/83)
  • Patent number: 11463086
    Abstract: A circuit comprises an H-bridge circuit that includes a pair of current sources and a plurality of transistors. The H-bridge circuit includes a first output and a second output. One of the current sources is coupled to receive a supply voltage. A control circuit is configured to control, based on a sum of voltages on the first and second outputs, current of at least one of the current sources through at least some of the plurality of transistors.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: October 4, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Kannan Krishna
  • Patent number: 11431530
    Abstract: A circuit for a transmitter driver is disclosed. The transmitter driver circuit includes a main voltage-mode driver circuit configured to receive an input signal at the input port and to drive an output signal at the output port. The transmitter driver circuit also includes a secondary circuit connected to the input port and the output port in parallel with the main voltage-mode driver circuit. The secondary circuit includes: a secondary voltage-mode driver circuit; a current source connected to the secondary voltage-mode driver circuit and controllable to enable or disable a current boost to the output signal; and a switch connected to the secondary voltage-mode driver circuit and controllable to enable or disable the secondary voltage-mode driver circuit to drive the output signal in parallel with the main voltage-driver circuit.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: August 30, 2022
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventor: Euhan Chong
  • Patent number: 11393845
    Abstract: A microelectronic device comprises first digit lines, second digit lines, and multiplexer devices. The first digit lines are coupled to strings of memory cells. The second digit lines are coupled to additional strings of memory cells. The second digit lines are offset from the first digit lines in a first horizontal direction and are substantially aligned with the first digit lines in a second horizontal direction orthogonal to the first horizontal direction. The multiplexer devices are horizontally interposed between the first digit lines and the second digit lines in the first horizontal direction. The multiplexer devices are in electrical communication with the first digit lines, the second digit lines, and page buffer devices. Additional microelectronic devices, memory devices, and electronic systems are also described.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: July 19, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Koichi Kawai, Yoshihiko Kamata, Yoshiaki Fukuzumi, Tamotsu Murakoshi
  • Patent number: 11349479
    Abstract: An example apparatus according to an embodiment of the disclosure includes first and second voltage terminals, and first, second, and third circuit nodes. A potential of the first circuit node is changed based on an input signal. A flip-flop circuit includes first and second inverters cross-coupled to each other. The first inverter is coupled between the first voltage terminal and the second circuit node. A first transistor is coupled between the second and third circuit nodes, and the first transistor has a control electrode coupled to the first circuit node. A first current control circuit is coupled between the third circuit node and the second voltage terminal, and an amount of current flowing through the first current control circuit being controlled based on a first code signal.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: May 31, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Hiroyuki Matsuno, Shuichi Tsukada
  • Patent number: 11322193
    Abstract: A power gating control circuit includes an operational period signal generating circuit, a period termination detecting circuit, a power gating period signal generating circuit and a power gating control signal generating circuit. The operational period signal generating circuit generates a plurality of operational period signals based on internal clock signals and one or more of command shift signals. The period termination detecting circuit generates a write period termination signal and a read period termination signal based on the command signals and the plurality of operational period signals. The power gating period signal generating circuit generates a first power gating period signal and a second power gating period signal based on the write period termination signal, the read period termination signal and remaining command shift signals other than the one or more command shift signals.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: May 3, 2022
    Assignee: SK hynix Inc.
    Inventors: Woong Rae Kim, Sung Je Roh
  • Patent number: 11276468
    Abstract: Embodiments disclosed herein relate to level shifters of a memory device. Specifically, the level shifters include a first series arrangement of transistors to offset a first transistor. The level shifters also include a second series arrangement of transistors to offset a second transistor. The first series arrangement is opposite the second series arrangement. The output of the first series arrangement is coupled to a first pull-up transistor and configured to cut off a pull-up of the first pull-up transistor to a first voltage. The output of the second series arrangement is coupled to a second pull-up transistor and configured to cut off a pull-up of the second pull-up transistor to the first voltage. The first series arrangement and the second series arrangement are coupled to a second voltage at different times. The series arrangements of transistors enable faster level shifting over conventional level shifters.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: March 15, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Sujeet Ayyapureddi
  • Patent number: 11250914
    Abstract: A control method, for a memory array, the control method comprises programming the bit-cell of the memory array in a programming stage; and discharging the bit-cell of the memory array in a discharge stage; wherein the programming stage comprises: programming the bit-cell of the memory array with a plurality of programming voltage pulses; wherein the discharge stage comprises: isolating a select line of the bit-cell of the memory array; and generating a programming voltage pulse to the bit-cell of the memory array; wherein the programming stage can be suspended to a suspend stage by a suspend command after the discharge stage; wherein the suspend command is received during one of the plurality of programming voltage pulse.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: February 15, 2022
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Zhi Chao Du, Yu Wang, Haibo Li, Ke Jiang, Ye Tian
  • Patent number: 11245398
    Abstract: An electronic device may include one or more output buffers each including a pair of final p-channel metal oxide semiconductor (PMOS) and n-channel metal oxide semiconductor (NMOS) transistors, a first pre-buffer to drive the PMOS transistor, and a second pre-buffer to drive the NMOS transistor. Each output buffer receives power from a pre-buffer supply filtering circuit, which may include a supply capacitor for stabilizing supply voltage, a low-pass first pre-buffer supply filter to filter the voltage supplied to the first pre-buffer, and a low-pass second pre-buffer supply filter the voltage supplied to the second pre-buffer.
    Type: Grant
    Filed: February 17, 2021
    Date of Patent: February 8, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Daniele Vimercati
  • Patent number: 11232846
    Abstract: The present disclosure provides a gate drive unit, a driving method thereof and a gate drive circuit. The gate drive unit includes a shift register and a plurality of output control modules. Each of the output control modules is connected to a corresponding clock scanning signal line and a corresponding first scanning signal output terminal, respectively. Each of the output control modules includes a first output control submodule and an output reset submodule. The first output control submodule is connected to a signal output terminal of the shift register, the corresponding clock scanning signal line and the corresponding first scanning signal output terminal, and configured to send a clock scanning signal of the corresponding clock scanning signal line to the corresponding first scanning signal output terminal, under control of a signal outputted by the signal output terminal of the shift register.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: January 25, 2022
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., CHONGQING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Zhuo Xu, Yuanbo Zhang, Yajie Bai, Heecheol Kim, Peng Liang, Hailong Wu, Yi Dan
  • Patent number: 11137819
    Abstract: A method and apparatus configured to reduce power consumption of a physical (PHY) interface of a digital memory device. In some configurations, the PHY interface is configured to modulate electrical characteristics of a transmitter and/or receiver on the PHY interface according to an idle state of one or more of the digital memory device or a host computing system.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: October 5, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Shay Benisty, Gennady Burdo, Tal Sharifie
  • Patent number: 11139753
    Abstract: A semiconductor device according to an embodiment includes: a first transistor having a first electrode, a second electrode, and a first control electrode, the first transistor performing a switching operation; a second transistor having a third electrode electrically connected to the second electrode, a fourth electrode, and a second control electrode, the second transistor performing an analog operation; and a third transistor having a fifth electrode electrically connected to the fourth electrode, a sixth electrode, and a third control electrode.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: October 5, 2021
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kentaro Ikeda, Kazuto Takao
  • Patent number: 11126581
    Abstract: Described is a reconfigurable transmitter which includes: a first pad; a second pad; a first single-ended driver coupled to the first pad; a second single-ended driver to the second pad; a differential driver coupled to the first and second pads; and a logic unit to enable of the first and second single-ended drivers, or to enable the differential driver.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: September 21, 2021
    Assignee: Intel Corporation
    Inventors: Tzu-Chien Hsueh, Ganesh Balamurugan, Bryan K. Casper
  • Patent number: 11114540
    Abstract: A semiconductor device includes a first potential supply line for supplying a first potential, a second potential supply line for supplying a second potential lower than the first potential, a functional circuit, and at least one of a first switch disposed between the first potential supply line and the functional circuit and a second switch disposed between the second potential supply line and the functional circuit. The first switch and the second switch are negative capacitance FET.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: September 7, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Hsing Lee, Chih-Sheng Chang, Wilman Tsai, Chia-Wen Chang, Ling-Yen Yeh, Carlos H. Diaz
  • Patent number: 11084033
    Abstract: A drive circuit and its drive method, and a panel and its drive method are provided. The drive circuit includes a step-up unit, a plurality of signal input terminals and a signal output terminal, which are electrically connected with each other. The step-up unit includes a first module, a second module, a third module and a first capacitor, which are electrically connected with each other. The first module is configured to transmit a signal of a third signal input terminal to a first electrode of the first capacitor. The second module is configured to transmit a signal of a fourth signal input terminal to a second electrode of the first capacitor. The third module is configured to transmit a signal of the third signal input terminal to the second electrode of the first capacitor, which further increases the signal of the first electrode of the first capacitor.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: August 10, 2021
    Assignee: Shanghai AVIC OPTO Electronics Co., Ltd.
    Inventors: Kerui Xi, Feng Qin, Xiangjian Kong, Jiubin Zhou, Guicai Wang, Yajie Wang, Tingting Cui
  • Patent number: 11075636
    Abstract: A differential output driver circuit includes a drive path having a first output node that provides a first output differential signal and a second output node that provides a complementary second output differential signal to the first output differential signal, a current control transistor to control current of the drive path, and a current measurement resistor circuit located in the drive current path outside of a path segment between the first and second output node. Current flowing through the drive path flows through the current measurement resistor circuit, and a voltage across the current measurement resistor circuit is indicative of an amount of current flowing through the drive path. A transistor control circuit utilizes a voltage across the current measurement resistor circuit to control a control terminal of the current control transistor to control the current in the drive path based on the voltage across the current measurement resistor circuit.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: July 27, 2021
    Assignee: NXP USA, Inc.
    Inventors: Kumar Abhishek, Srikanth Jagannathan
  • Patent number: 11063591
    Abstract: In an embodiment, a method includes programming a control signal that specifies a target resistance and a target voltage in a circuit. The method further includes sending the control signal to at least one transistor configured to control a current flow in the circuit. The method further includes providing, as an output, a signal with the target voltage and target resistance.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: July 13, 2021
    Assignee: MARVELL ASIA PTE, LTD.
    Inventor: Lu Wang
  • Patent number: 11056966
    Abstract: A gate driver for a high-side NMOS power transistor in a DC/DC boost converter includes first and second switches coupled in series between an output pin and the gate of the high-side transistor. A third switch is coupled between the gate and a switch-node between the high-side and low-side transistors, the switch node also being coupled to an input pin. Fourth and fifth switches are coupled in series between the output pin and a clamp pin. Sixth and seventh switch are coupled in series between the output pin and a ground pin. First and second bootstrap capacitors have respective first terminals coupled to a first node between the first and second switches. The first capacitor has a second terminal coupled to a node between the fourth and fifth switches; the second capacitor has a second terminal coupled to a node between the sixth and seventh switches.
    Type: Grant
    Filed: August 18, 2020
    Date of Patent: July 6, 2021
    Assignee: Texas Instruments Incorporated
    Inventors: Eduardas Jodka, Julian Becker, Carsten Stoerk
  • Patent number: 11044115
    Abstract: A portable battery-operated communication device includes a high-speed communication bus, a first high-speed communication processor coupled to the bus and configured for transferring communication signals to a second high-speed communication processor over the bus, and an isolation circuit for the bus with a first terminal coupled to the bus and configured to receive a first communication signal from the first processor via the bus, and a first resistor that is coupled to the first terminal and configured to protect the first terminal from an overcurrent failure condition, in which the isolation circuit is configured to match impendences between the isolation circuit and bus, isolate series inductance associated with the first terminal, protect the first terminal from an overvoltage failure while maintaining signal integrity of the first communication signal, and pass through the first communication signal from the first terminal to a second terminal coupled to the high-speed communication bus.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: June 22, 2021
    Assignee: Motorola Solutions, Inc.
    Inventors: Wai Mun Lee, Peter J. Bartels, Yoke Peir Lim, Kah Khoon Khoo
  • Patent number: 11031054
    Abstract: Apparatuses and methods for pre-emphasis control are described. An example apparatus includes a pull-up circuit and a pull-down circuit. The pull-up circuit is configured to receive a pull-up data activation signal and drive a data terminal to a pull-up voltage responsive to an active pull-up data activation signal. The pull-down circuit is configured to receive a pull-down activation signal and drive a data terminal to a pull-down voltage responsive to an active pull-down data activation signal. The example apparatus further includes a pull-up pre-emphasis circuit that includes a pre-emphasis timing control circuit configured to provide a timing control signal, and further includes a pull-up logic circuit. A pull-up pre-emphasis control signal based on pull-up data activation signal is provided to control providing pull-up pre-emphasis for greater than one unit interval of data when the pull-up data activation signal remains active for greater than one unit interval.
    Type: Grant
    Filed: January 22, 2020
    Date of Patent: June 8, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Tetsuya Arai, Junki Taniguchi
  • Patent number: 11012074
    Abstract: An off chip driving circuit includes a decision circuit, a first compensation circuit, a second compensation circuit, a pull-up circuit and a pull-down circuit. The decision circuit is configured to output a first decision signal and a second decision signal according to a clock and an input data. The first compensation circuit is coupled to the decision circuit and configured to generate a first control signal in response to the first decision signal and the second decision signal. The second compensation circuit is coupled to the decision circuit and configured to generate a second control signal in response to the first decision signal and the second decision signal. The pull-up circuit is configured to be enabled in response to the first control signal. The pull-down circuit is configured to be enabled in response to the second control signal.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: May 18, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chang-Ting Wu, Hao-Huan Hsu
  • Patent number: 10950290
    Abstract: A memory device is provided. The memory device includes a plurality of memory cell blocks and a source voltage generator. Each of the memory cell blocks has at least one memory cell. The source voltage generator is coupled to the plurality of memory cell blocks and configured to cause a source voltage of the memory cell block to be a first voltage according to that a memory cell in each of the memory cell blocks is in a selected state and cause a source voltage of the memory cell block to be a second voltage according to that all memory cells in each of the memory cell blocks are in an unselected state, wherein an absolute value of the first voltage is less than an absolute value of the second voltage. In addition, an operating method of the memory device is also provided.
    Type: Grant
    Filed: July 5, 2019
    Date of Patent: March 16, 2021
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chun-Chang Lu, Wen-Jer Tsai
  • Patent number: 10929329
    Abstract: Methods and systems are described for receiving a set of input bits at a plurality of drivers and responsively generating an ensemble of signals, each respective signal of the ensemble of signals generated by receiving a subset of input bits at a respective driver connected to a respective wire of a multi-wire bus, the received subset of bits corresponding to sub-channels associated with the respective wire, generating a plurality of weighted analog signal components, each weighted analog signal component (i) having a corresponding weight and sign selected from a set of wire-specific sub-channel weights associated with the respective wire and (ii) modulated by a corresponding bit of the received subset of bits, and generating the respective signal by forming a summation of the plurality of weighted analog signal components at a common node connected to the respective wire for transmission over the respective wire of the multi-wire bus.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: February 23, 2021
    Assignee: KANDOU LABS, S.A.
    Inventors: Omid Talebi Amiri, Armin Tajalli
  • Patent number: 10931201
    Abstract: Techniques are provided for providing and maintaining an efficient deadtime for a switching circuit as the input voltage varies. In example, a switching circuit can include a control circuit configured to alternately switch the first switch and the second switch into and out of a low impedance state, and to prevent the first switch and the second switch from shorting the first supply rail with the second supply rail using a dead-time before a transition to the low impedance state of each of the first and second switches. The control circuit can a delay element that includes a compensation delay circuit configured to change in-kind with a change of a voltage difference between a first input supply rail and a second input supply rail of the switching circuit, and to limit a range of the dead-time over a range of the voltage difference.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: February 23, 2021
    Assignee: Analog Devices International Unlimited Company
    Inventors: Danzhu Lu, Langyuan Wang, Jie He
  • Patent number: 10924064
    Abstract: Included are: a first power source 3 configured to output a voltage required for a first gate bias voltage for turning a power amplifier 2 to an ON state; a second power source 4 configured to output a voltage required for a second gate bias voltage for turning the power amplifier 2 to an OFF state; a changeover switch 5 connected between the first power source 3 and the power amplifier 2 and configured to supply either the first gate bias voltage or the second gate bias voltage to the power amplifier 2 by switching a state between the first power source 3 and the power amplifier 2 to either an open state or a short-circuit state on the basis of a control signal related to on-off control of the power amplifier 2; and a resistance value varying unit 15 connected between the second power source 4 and the power amplifier 2 and configured such that a resistance value thereof is variable.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: February 16, 2021
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Hideki Tango, Tatsuya Hashinaga, Harutoshi Tsuji
  • Patent number: 10911043
    Abstract: A device and a method for switching over a semiconductor switch with a switching signal acting on a control connection of the semiconductor switch, the switching signal being switched over as a response to registering a switchover of an activation signal; a down time being ascertained between the start of the switchover of the switching signal and the switchover of the semiconductor switch; the switchover of the semiconductor switch being delayed by a waiting period, for example by delaying the output of the switching signal and/or changing the signal level, so that an actual switching time, corresponding to a setpoint switching time, between the registration of the switchover of the activation signal and the switchover of the semiconductor switch is obtained.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: February 2, 2021
    Assignee: Robert Bosch GmbH
    Inventors: Frank Ueltzhoeffer, Daniel Marquardt, Bernd Wichert, Ralf Henne
  • Patent number: 10892749
    Abstract: An electronic circuit of the embodiments includes at least one first n-type transistor, at least one first p-type transistor, a supply circuit, a detection circuit, and a control circuit. The supply supplies current to a control terminal of a semiconductor switching element. The detection circuit acquires a value associated with a voltage at a first terminal of the semiconductor switching element. The control circuit causes one type of transistors of the first n-type transistors and the first p-type transistors to be in the non-driven state and causing at least one of the other type of transistors to be in the driven state, at least based on the value associated with the voltage. The first n-type transistor is electrically connected to a reference potential and the control terminal, and the first p-type transistor is electrically connected to a power supply potential and the control terminal.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: January 12, 2021
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Shusuke Kawai
  • Patent number: 10891914
    Abstract: A control buffer in a source driver includes a first CMOS inverter configured to output a switch signal to control turning on and off of a switch, and a first tri-state inverter that is connected to the first CMOS inverter and configured to selectively adjust a size of the control buffer, wherein a slew rate of the switch signal is adjusted depending on the size of the control buffer.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: January 12, 2021
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Eun Kyu Seong, Hyoung Kyu Kim
  • Patent number: 10868132
    Abstract: A semiconductor device includes a first potential supply line for supplying a first potential, a second potential supply line for supplying a second potential lower than the first potential, a functional circuit, and at least one of a first switch disposed between the first potential supply line and the functional circuit and a second switch disposed between the second potential supply line and the functional circuit. The first switch and the second switch are negative capacitance FET.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Hsing Lee, Chih-Sheng Chang, Wilman Tsai, Chia-Wen Chang, Ling-Yen Yeh, Carlos H. Diaz
  • Patent number: 10862399
    Abstract: Communicating information stored at a secondary controller to a primary controller in a secondary-controlled flyback converter is described. In one embodiment, a method includes storing, by a secondary-side controller of a power converter, calibration information associated with a primary-side controller of the power converter. The power converter is a secondary-controlled alternating current to direct current (AC-DC) flyback converter comprising a galvanic isolation barrier. The method further includes sending, by the secondary-side controller, the calibration information to the primary-side controller across the galvanic isolation barrier in response to power-up of the power converter.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: December 8, 2020
    Assignee: Cypress Semiconductor Corporation
    Inventor: Hariom Rai
  • Patent number: 10855263
    Abstract: Aspects provide for a circuit including a voltage supply, a driver, and a feedback bias circuit. The driver includes a first p-type field effect transistor (FET) and a first n-type FET. The voltage supply has an input and an output. The driver has a first input coupled to the voltage supply output, a second input coupled to a first node, and an output coupled to a second node. The first p-type FET has a gate coupled to the output of the driver, a source coupled to the voltage supply output, and a drain coupled to the second node. The first n-type FET has a gate coupled to the output of the second driver, a drain coupled to the second node, and a source coupled to a ground node. The feedback bias circuit has an input coupled to the second node and an output coupled to the voltage supply input.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: December 1, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Shuing Ju, Wenxiao Tan, Arun Rao
  • Patent number: 10833899
    Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within electronic equipment. Transmission lines are selectively terminated in an N-phase polarity encoded transmitter when the transmission lines would otherwise be undriven. Data is mapped to a sequence of symbols to be transmitted on a plurality of wires. The sequence of symbols is encoded in three signals. A first terminal of a plurality of terminals may be driven such that transistors are activated to couple the first terminal to first and second voltage levels. The first terminal may further be driven such that a dedicated transistor is activated to couple the first terminal to an intermediate voltage level.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: November 10, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Shih-Wei Chou, Chulkyu Lee, Dhaval Sejpal
  • Patent number: 10794971
    Abstract: An approach for accurately setting a duty cycle of PA switching waveforms uses an all-digital PVT sensor circuit. In various embodiments, the all-digital PVT sensor circuit measures a pulse width of a periodic reference signal using digital delay line, and subsequently, implements an off-chip digital calculation to program the digital delay line to delay this periodic reference signal so that, when the delayed periodic reference signal is combined with the original (undelayed) reference via a logical AND operation, the resulting signal conforms to a desired duty cycle. In one implementation, the PA is a class-D PA, which may have a single-ended configuration or a differential configuration having two single-ended structures operating in opposite phases.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: October 6, 2020
    Assignee: WaveGuide Corporation
    Inventor: Alexander Alexeyev
  • Patent number: 10784861
    Abstract: Systems, methods, and apparatus for biasing a high speed and high voltage driver using only low voltage transistors are described. The apparatus and method are adapted to control biasing voltages to the low voltage transistors such as not to exceed operating voltages of the low voltage transistors while allowing for DC to high speed operation of the driver at high voltage. A stackable and modular architecture of the driver and biasing stages is provided which can grow with a higher voltage requirement of the driver. Capacitive voltage division is used for high speed bias voltage regulation during transient phases of the driver, and resistive voltage division is used to provide bias voltage at steady state. A simpler open-drain configuration is also presented which can be used in pull-up or pull-down modes.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: September 22, 2020
    Assignee: pSemi Corporation
    Inventor: Gary Chunshien Wu
  • Patent number: 10783097
    Abstract: A receiver includes an amplification circuit and a compensation circuit. The amplification circuit changes a voltage level of a first output node based on an input signal and changes a voltage level of a second output node based on a reference voltage. The compensation circuit changes the voltage level of the second output node based on the input signal and changes the voltage level of the first output node based on the reference voltage. The amplification circuit includes first type transistors configured to receive the input signal and the reference voltage. The compensation circuit includes second type transistors configured to receive the input signal and the reference voltage.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: September 22, 2020
    Assignee: SK hynix Inc.
    Inventor: Kyu Dong Hwang
  • Patent number: 10778195
    Abstract: Provided is a gate drive circuit and a gate drive system, with which current unevenness among power devices connected in parallel can be reduced more. A gate drive circuit includes: an objective waveform generation unit configured to generate an objective waveform; a drive waveform generation unit configured to generate a drive waveform from the objective waveform, by referring to on-timing set information and off-timing set information; a drive control unit configured to drive the power device to turn the power device on/off, based on the drive waveform; a state detection unit configured to detect the state of the power device; a predicted waveform generation unit configured to generate a predicted waveform of a voltage; and an update unit configured to update the on-timing set information and the off-timing set information, based on the result of the state detection and the result of comparison to the predicted waveform.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: September 15, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventor: Hiroshi Gokan
  • Patent number: 10770597
    Abstract: A logic circuit includes a thin film transistor having a channel formation region formed using an oxide semiconductor, and a capacitor having terminals one of which is brought into a floating state by turning off the thin film transistor. The oxide semiconductor has a hydrogen concentration of 5×1019 (atoms/cm3) or less and thus substantially serves as an insulator in a state where an electric field is not generated. Therefore, off-state current of a thin film transistor can be reduced, leadind to suppressing the leakage of electric charge stored in a capacitor, through the thin film transistor. Accordingly, a malfunction of the logic circuit can be prevented. Further, the excessive amount of current which flows in the logic circuit can be reduced through the reduction of off-state current of the thin film transistor, resulting in low power consumption of the logic circuit.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: September 8, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Masashi Tsubuku, Kosei Noda
  • Patent number: 10769977
    Abstract: The present disclosure provides a shift register. The shift register includes: a first node control module configured to control level at a first node based on a first clock signal and a second clock signal; a second node control module configured to control level at a second node based on level at the first node, the first clock signal, the second clock signal, a first low level signal and a high level signal; an output control module configured to control an output terminal to output high or low level based on level at the first node, level at the second node, the high level signal and a second low level signal; and a carry control module configured to control a carry terminal to output high or low level based on level at the second node, level at the output terminal, the high level signal and the second low level signal.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: September 8, 2020
    Assignee: SHANGHAI TIANMA AM-OLED CO., LTD.
    Inventors: Dongxu Xiang, Yue Li, Renyuan Zhu, Yana Gao, Xing Yao Zhou, Juan Zhu, Zhonglan Cai, Yilin Xu, Gaojun Huang
  • Patent number: 10763845
    Abstract: A semiconductor device capable of enhancing uniformity of temperatures of transistors in an active clamp state while maintaining current performance is provided. A power transistor is connected to a power transistor in parallel. An active clamp circuit is provided in a path from a connection point between the power transistors to a gate of the power transistor and is conducted in a case where a voltage of the connection point exceeds a first threshold. An active clamp cutoff circuit is provided in a path from the active clamp circuit to a gate of the power transistor and cuts off or suppresses a current flowing into the path.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: September 1, 2020
    Assignee: Hitachi Automotive Systems, Ltd.
    Inventors: Shinichirou Wada, Masahito Sonehara
  • Patent number: 10763846
    Abstract: An analog switch circuit is provided. The circuit includes a branch coupled between an input terminal and an output terminal. The branch is configured to transfer an input signal at the input terminal to the output terminal when a control signal is at a first state. A transistor in the branch includes a current electrode coupled at the input terminal and is configured for receiving the input signal having a voltage exceeding a voltage rating of the transistor. A level shifter includes an output coupled to a control electrode of the transistor and is configured to provide a first voltage sufficient to cause the transistor to be conductive without exceeding the voltage rating of the first transistor when the control signal is at the first state. A voltage generator is coupled to the level shifter and is configured to generate the first voltage based on the input signal.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: September 1, 2020
    Assignee: NXP USA, Inc.
    Inventors: Marcos Mauricio Pelicia, Ivan Carlos Ribeiro do Nascimento, Bruno Bastos Cardoso
  • Patent number: 10756078
    Abstract: An integrated circuit having a CML driver including a driver biasing network. A first output pad and a second output pad are connected to a voltage pad. A first driver is connected to the first output pad and the voltage pad. A second driver is connected to the second output pad and the voltage pad. A first ESD circuit is connected to the voltage pad, the first output pad, and the first driver. A second ESD circuit is connected to the voltage pad, the second output pad, and the second driver. The first ESD circuit biases the first driver toward a voltage of the voltage pad when an ESD event occurs at the first output pad, and the second ESD circuit biases the second driver toward the voltage of the voltage pad when an ESD event occurs at the second output pad.
    Type: Grant
    Filed: January 5, 2017
    Date of Patent: August 25, 2020
    Assignee: International Business Machines Corporation
    Inventors: James P. Di Sarro, Robert J. Gauthier, Jr., Nathan D. Jack, JunJun Li, Souvick Mitra
  • Patent number: 10742181
    Abstract: A buffer circuit includes a first buffer configured to operate at an external power voltage, generate first and second buffer signals by comparing an input signal with a reference voltage, and control potential levels of the first and second buffer signals in response to a common mode feedback voltage; a second buffer configured to operate at an internal power voltage and generate an output signal in response to the first and second buffer signals; and a replica circuit configured to generate the common mode feedback voltage to be less than the internal power voltage.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: August 11, 2020
    Assignee: SK hynix Inc.
    Inventors: Dong Hyun Kim, Eun Ji Choi, Yo Han Jeong, Jae Heung Kim
  • Patent number: 10739424
    Abstract: Systems and methods for reducing variability in the output impedance of an integrated switch-mode power amplifier (PA) split the output impedance between passive resistor, which may be on-chip, and a MOSFET switch of the amplifier. The PA may have a single-ended configuration or a differential configuration having two single-ended structures operating with opposite phases. In one implementation, the size of the MOSFET switch is larger than that of the MOSFET switch implemented in a conventional PA, but the size is still acceptable to operate the PA at a desired frequency. In addition, a calibration approach may be utilized to ensure that the MOSFET switch has a controlled and calibrated ON resistance, thereby providing stable output power levels of the PA and ensuring consistency and repeatability in NMR measurements.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: August 11, 2020
    Assignee: WAVEGUIDE CORPORATION
    Inventor: Alexander Alexeyev
  • Patent number: 10734083
    Abstract: A voltage driver includes a voltage divider, a first transistor and a second transistor. The voltage divider is connected with a first voltage source and a second voltage source, and generates a first bias voltage. A drain terminal of the first transistor is connected with a third voltage source. A gate terminal of the first transistor is connected with the voltage divider to receive the first bias voltage. A drain terminal of the second transistor is connected with a source terminal of the first transistor. A gate terminal of the second transistor receives a second bias voltage. A source terminal of the second transistor is connected with a fourth voltage source. The first transistor and the second transistor are of the same conductivity type and match each other. The source terminal of the first transistor generates an output voltage.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: August 4, 2020
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventors: Yu Wu, Wei-Chiang Ong, Chih-Yang Huang
  • Patent number: 10700610
    Abstract: Communicating information stored at a secondary controller to a primary controller in a secondary-controlled flyback converter is described. In one embodiment, a method includes storing, by a secondary-side controller of a power converter, calibration information associated with a primary-side controller of the power converter. The power converter is a secondary-controlled alternating current to direct current (AC-DC) flyback converter comprising a galvanic isolation barrier. The method further includes sending, by the secondary-side controller, the calibration information to the primary-side controller across the galvanic isolation barrier in response to power-up of the power converter.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: June 30, 2020
    Assignee: Cypress Semiconductor Corporation
    Inventor: Hariom Rai
  • Patent number: 10673435
    Abstract: A method and apparatus for reducing dynamic switching current in high speed logic. The apparatus may include a CMOS logic circuit, which in turn includes an NMOS FinFET, a first PMOS FinFET, and a second PMOS FinFET. A gate of the NMOS FinFET is connected to a gate of the first PMOS FinFET, a drain of the NMOS FinFET is connected to a drain of the first PMOS FinFET, and the second PMOS FinFET is connected to the first PMOS FinFET to create a capacitor between a source and the drain of the first PMOS FinFET. In one embodiment, the second PMOS FinFET is contained in and positioned at an edge of a cell that also contains the first PMOS FinFET and the NMOS FinFET.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: June 2, 2020
    Assignee: NXP USA, INC.
    Inventors: Emmanuel Chukwuma Onyema, David Russell Tipple
  • Patent number: 10644699
    Abstract: A circuit includes a first transistor comprising a first control input and first and second current terminals, the first control input coupled to receive a first input control signal, and the first current terminal coupled to a first power supply node. The circuit also includes a first resistor coupled to the first control input of the first transistor, a first capacitor coupled between the second current terminal of the first transistor and the first resistor and a second transistor comprising a second control input and third and fourth current terminals, the third current terminal coupled to the first resistor and to the first capacitor.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: May 5, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Steven Ernest Finn
  • Patent number: 10622950
    Abstract: An amplifier arrangement has a first differential stage with a first transistor pair, a second differential stage with a first and a second transistor pair, each pair having a common source connection. The amplifier arrangement further has a first complementary differential stage with a transistor pair having opposite conductivity type, and a second complementary differential stage with a first and a second transistor pair of the complementary conductivity type. The first and the second complementary differential stage are connected symmetrically compared to the first and the second differential stage. The transistors of the second differential stage and the second complementary differential stage are symmetrically connected to form respective first, second, third and fourth current paths. A pair of output terminals is coupled to the first and the fourth current path. Gate terminals of the transistors are coupled to a respective pair of input terminals.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: April 14, 2020
    Assignee: ams AG
    Inventors: Matthias Steiner, Andreas Fitzi
  • Patent number: 10608625
    Abstract: Circuits, methods, and systems are provided for setting a current level to be used by a current-mode gate driver. The current level may be used to source, sink, or both source and sink current to/from the gate terminal of a power device. The current level is based upon a current or voltage level input from an analog current-setting terminal. This input current or voltage level may take a value from a continuous range of current or voltage values.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: March 31, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Giuseppe Bernacchia, Adriano Sambucco
  • Patent number: 10593810
    Abstract: A logic circuit includes a thin film transistor having a channel formation region formed using an oxide semiconductor, and a capacitor having terminals one of which is brought into a floating state by turning off the thin film transistor. The oxide semiconductor has a hydrogen concentration of 5×1019 (atoms/cm3) or less and thus substantially serves as an insulator in a state where an electric field is not generated. Therefore, off-state current of a thin film transistor can be reduced, leadind to suppressing the leakage of electric charge stored in a capacitor, through the thin film transistor. Accordingly, a malfunction of the logic circuit can be prevented. Further, the excessive amount of current which flows in the logic circuit can be reduced through the reduction of off-state current of the thin film transistor, resulting in low power consumption of the logic circuit.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: March 17, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Masashi Tsubuku, Kosei Noda
  • Patent number: 10552562
    Abstract: A method, computer program product, and system for calculating an input timing slack at an input to a latch by subtracting an input arrival time to the latch from an input required arrival time, calculating an output timing slack at an output to the latch by subtracting an output arrival time of the latch from an output required arrival time from the latch, performing cycle stealing to improve the output timing slack by modifying the input required arrival time and the output arrival time, reducing the output timing slack by a pessimism amount, performing optimization in the integrated circuit to improve the input timing slack and the output timing slack, and increasing the output timing slack by the pessimism amount.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: February 4, 2020
    Assignee: International Business Machines Corporation
    Inventors: Nathaniel D. Hieter, Kerim Kalafala, Alexander J. Suess