Abstract: A bi-directional buffer for applications using in an I2C or SMBUS or other bus systems. The bi-directional buffer has an input terminal to receive an input voltage signal and an output terminal for providing an output voltage signal, and the output voltage signal follows the input voltage signal. The output voltage signal is regulated to have a first bias voltage greater than the input voltage signal by a first operational amplifier, or to have a second bias voltage greater than the input voltage signal by a second operational amplifier, the second bias voltage is smaller than the first bias voltage.

Abstract: Circuits integrating OR logic and level shifting functionality and methods of operating the same are configured to accommodate different applications. One such circuit comprises first and second transistors coupled in parallel defining first and second nodes, the first transistor being responsive to a first input signal and the second transistor being responsive to a second input signal; a first resistor coupled between a power supply terminal of the circuit and the first node; and a second resistor coupled between the second node and a ground terminal of the circuit. The circuit generates an output signal having a voltage level that is lower than a voltage level of each of the first and second input signals.

Abstract: An integrated circuit including a first circuit, a second circuit, a third circuit, a first complementary pair of transistors, and a second complementary pair of transistors. The first circuit may be configured to generate a first input signal in response to a first control input signal. The second circuit may be configured to generate a first output signal and a second output signal in response to the first input signal and a bias signal. The third circuit may be configured to generate the bias signal in response to a bias input signal. The first complementary pair of transistors may be configured to drive a first series output of the integrated circuit in response to the first output signal. The second complementary pair of transistors may be configured to drive a first shunt output of the integrated circuit in response to the second output signal.

Abstract: A pipelined processor including a combinational logic of several stages, a voltage regulator, a counter, a comparator, and a plurality of stage registers. Each stage register is disposed between two adjacent stages of the combinational logic. The stage register includes a flip-flop, a latch, an XOR gate, and a MUX module. When the high level of a register clock is coming, the flip-flop latches first data at the rising edge, and the latch receives second data during the high level. The data latched by the flip-flop and the latch respectively are compared by the XOR gate. If they are same, the output Error of the XOR gate is low level, and the output of the flip-flop is delivered to the next stage. Otherwise, the output Error of the XOR gate is high level, and the output of the latch is delivered to the next stage.

Abstract: Described herein is a low-voltage circuit with an inductor tail and a common mode feedback loop for amplitude and current control. A first transistor pair can receive clock inputs, and a second transistor pair can receive data inputs and output the data to a logic gate. A tail inductor can be coupled to the first transistor pair to suppress high frequency common mode bounce induced by clock transitions in independent common emitter branches. A common mode feedback loop can be provided to maintain a constant average current. The common mode feedback loop and the tail inductor can together function in the same way as a tail current source at low frequencies and high frequencies respectively.

Abstract: USB apparatus suitable for interconnection with a USB host having a D? bus coupled to ground via a pull-down resistance, the USB apparatus including a microcontroller having a first port and a second port, the first port being coupled via a resistance to a voltage source and a switch, operated by the microcontroller via the second port, selectably interconnecting the first port and the bus of the USB host.

Abstract: A digital to analog converter including at least one current steering source and a master replica bias network. Each current steering source includes a data current source, two switches, two buffer devices, and two activation current sources. The switches are controlled by a data bit and its inverse for switching the source current between first and second control nodes. The buffer devices buffer the control nodes between corresponding output nodes. The activation current sources ensure that each buffer device remains active regardless of the state of the switches. The master replica bias network includes a replica buffer device coupled to a replica control node and a master buffer amplifier. The master buffer amplifier drives the first, second and replica buffer devices in parallel to maintain the first, second and replica control nodes at a common master control voltage to minimize noise and glitches at the output.

Abstract: Various embodiments are described herein for an asymmetrical bus keeper circuit that provides asymmetrical drive towards one logic level. The asymmetrical bus keeper circuit comprises a first inverter stage having an input node and an output node, an asymmetrical inverter stage having an input node and an output node and a feedback stage with an input node and an output node. The input node of the asymmetrical inverter stage is connected to the output node of the first inverter stage. The input node of the feedback stage connected to the output node of the asymmetrical inverter stage and the output node of the feedback stage connected to the input node of the first inverter stage. The asymmetrical stage provides asymmetrical drive towards one logic level.

Abstract: A communication system having first and second states for use with a shared transmission line composed of at least two conductors and composed of first and second transmission line segments connected to each other at a single connection point. In the first state, a termination is coupled to the single connection point and is operative to at least attenuate a signal propagated between the first and second segments. In the second state, a driver is coupled to the connection point and is operative to conduct a signal over the first and second segments.

Abstract: Various embodiments are described herein for an asymmetrical bus keeper circuit that provides asymmetrical drive towards one logic level. The asymmetrical bus keeper circuit comprises a first inverter stage having an input node and an output node, an asymmetrical inverter stage having an input node and an output node and a feedback stage with an input node and an output node. The input node of the asymmetrical inverter stage is connected to the output node of the first inverter stage. The input node of the feedback stage connected to the output node of the asymmetrical inverter stage and the output node of the feedback stage connected to the input node of the first inverter stage. The asymmetrical stage provides asymmetrical drive towards one logic level.

Abstract: A system and method are shown for generation of at least one reference voltage level in a bus system. A reference voltage generator on a current driver includes at least one reference voltage level, at least one control signal, and an active device. The active device is coupled to the at least one control signal, such as a current control signal, and a selected reference voltage of the at least one reference voltage level. The active device is arranged to shift the at least one reference voltage level based on the at least one current control signal such as an equalization signal, a crosstalk signal, or the combination thereof, employed on the current driver.

Abstract: According to one exemplary embodiment, an active termination circuit includes at least one active termination branch, where the at least one active termination branch includes at least one transistor for providing an active termination output. The at least one active termination branch further includes an amplifier driving the at least one transistor, where the amplifier has a non-inverting input coupled to the active termination output via a feedback network. The amplifier controls a current flowing through the at least one transistor so as to provide the active termination output. The active termination output can be provided at a drain of the at least one transistor, where a source of the at least one transistor is coupled to ground through a degeneration transistor and a tail current sink.

Abstract: A multimode line driver circuit is provided. The multimode line driver circuit has a first driver circuit for receiving a first differential input signal and transmitting a first differential output signal, and a second driver circuit for receiving a second driver circuit for receiving a second differential input signal and transmitting a second differential output signal. The multimode line driver circuit also has a first switch coupling the first driver circuit to a first power supply and a second switch coupling the second driver circuit to a second power supply. The multimode line driver circuit also has a transformer coupled to the output interface for transforming the first differential output and the second differential output and a mode controller configured to close the first switch in the first mode and to close the second switch in the second mode.

Abstract: A bus system that includes a plurality of signal driving devices coupled to a common signal bus, a bus controlled circuit coupled to the common signal bus, and a compare circuit. The plurality of signal driving devices include a first signal driving device and a second signal driving device. The bus controller includes delay compensation circuitry with a configurable delay for each of the signal driving devices. The delay compensation circuitry has a current delay chain configuration associated with the first signal driving device. The compare circuit is configured to compare a first configurable delay associated with a first signal driving device to a second configurable delay associated with a second signal driving device of the plurality of signal driving devices, and for generating an output responsive to the comparing that indicates if the current delay chain configuration can be used by the second signal driving device.

Abstract: A circuit system has a first and a second circuit sub-system, and a bidirectional bus, the first circuit sub-system having a first control circuit that receives a control signal for controlling the direction of the bidirectional bus, and controls the first sub-system to be either of a transmitting or a receiving state based on a state of the control signal, a first sending unit that receives the control signal, and outputs as a first control signal, and a second sending unit that receives the control signal, and outputs as a second control signal, the second circuit sub-system having a first receiving unit that receives the first control signal, a second receiving unit that receives the second control signal, and a second control circuit that controls the second sub-system to assume either the transmitting or the receiving state on the basis of the first and the second control signal.

Abstract: In one embodiment, a receiver circuit is provide that may receive either a differential input or a single-ended input corresponding to an interface. The receiver circuit may include at least two current sources to control a gain of an amplification stage in the receiver. If the receiver circuit is receiving a differential input, one of the current sources may be used. If the receiver circuit is receiving a single-ended input, both of the current sources may be used. A larger gain may thus be provided for the single-ended input as compared to the differential input.

Abstract: A communication system having first and second states for use with a shared transmission line composed of at least two conductors and composed of first and second transmission line segments connected to each other at a single connection point. In the first state, a termination is coupled to the single connection point and is operative to at least attenuate a signal propagated between the first and second segments. In the second state, a driver is coupled to the connection point and is operative to conduct a signal over the first and second segments.

Abstract: A data communication system, comprising at least three signal conductors and a first and a second power supply terminal, for supplying currents of mutually opposite direction to the signal conductors respectively. A driver circuit establishes respective combinations of currents through the signal conductors from a selectable set of combinations, which includes combinations with currents from the first supply terminal and to the second supply terminal, so that a sum of the currents through the signal conductors substantially has a same value for each combination and at least one of the conductors in operation does not merely function in a differential-pair relation with another one of the conductors, the driver circuit determining which of the combinations from the set are established depending on information to be transmitted.

Abstract: A differential transmission line connector with little unwanted radiation noise is provided. A connector connects a differential transmission pattern for multiple transmission of a group of three differential signals and a differential transmission cable. The differential transmission pattern is provided with three signal lines, and the differential transmission cable also is provided with three signal lines. In a plane that is perpendicular to the longitudinal direction of the differential transmission pattern and the differential transmission cable, the signal lines are positioned at the apexes of an equilateral triangle.

Abstract: In one embodiment, a receiver circuit is provide that may receive either a differential input or a single-ended input corresponding to an interface. The receiver circuit may include at least two current sources to control a gain of an amplification stage in the receiver. If the receiver circuit is receiving a differential input, one of the current sources may be used. If the receiver circuit is receiving a single-ended input, both of the current sources may be used. A larger gain may thus be provided for the single-ended input as compared to the differential input.

Abstract: A buffer of a semiconductor memory apparatus includes a buffering section configured to generate an output signal by buffering an input signal. A mismatch compensation section generates a control voltage in correspondence with sizes of a second transistor of the same type as a first transistor constituting the buffering section, wherein the buffering section controls a transition time of the output signal in response to a level of the control voltage.

Abstract: The invention provides a serial link transmitter coupled to a serial link receiver through a pair of transmission lines and having a pair of transmitting terminals respectively coupled to one of the transmission lines. The serial link transmitter comprises a differential amplifier and a voltage clamping circuit. The differential amplifier generates a pair of differential output voltages on the transmitting terminals according to a pair of differential input voltages for transmitting data to the serial link receiver, and the differential output voltages are transmitted with a common mode voltage to the serial link receiver during data transmission. The voltage clamping circuit clamps the pair of differential output voltages of the transmitting terminals to the common mode voltage before the serial link transmitter transmits data to the serial link receiver.

Abstract: A voltage driver circuit includes a first transistor. The first transistor includes a control terminal, a first terminal, and a second terminal. The second transistor includes a control terminal, a first terminal, and a second terminal. A first current source configured to provide a first bias current to the control terminal of the first transistor. A second current source configured to provide a second bias current to the control terminal of the second transistor. The first resistance includes a first terminal connected to the control terminal of the first transistor. The second resistance includes a first terminal connected to the control terminal of the second transistor. A capacitance connects the second terminal of the first transistor with the control terminal of the second transistor. A ratio of the first bias current to the second bias current is approximately equal to a ratio of the second resistance to the first resistance.

Abstract: A voltage sequence output circuit includes a sequence control circuit and a number of voltage output circuits. The sequence control circuit includes a first NOR gate, and the first NOR gate includes a number of the input terminals. The voltage output circuits each includes an input terminal, an output terminal, and a positively enabled tristate buffer connected between the input terminal and the output terminal thereof. The input terminals of the voltage output circuits is connected to the input terminals of the first NOR gate. If all of input terminals of the voltage output circuits are connected with electronic devices, the positively enabled tristate buffer of the voltage output circuits are enabled. The output terminals of the voltage output circuits sequentially output a voltage.

Abstract: A buffer circuit for using one buffer for multiple differential I/O standards is disclosed. The buffer circuit includes a differential input buffer. The first input of the differential input buffer may receive an input and the second input is coupled to a switch. The switch may be a one-time-programmable switch. The switch has a coupling to transmit a signal to the second input of the differential input buffer. The switch may be programmed to selectively transmit different signals to the differential input buffer. The first input terminal of the switch may receive an inverted version of the input signal and the second input terminal of the switch may receive a reference voltage. The buffer may transmit an LVDS signal or an SSTL signal or an HSTL signal. Using one differential buffer for multiple I/O standards may reduce the overall die size and may save space on the die.

Abstract: Provided herein are bi-directional buffers, and methods for providing bi-directional buffering. In an embodiment, a bi-directional buffer includes a differential input/differential output amplifier that includes a first input/output node and a second/input output node. The differential input/differential output amplifier is configurable in a first configuration and a second configuration. When in the first configuration, the second input/output node follows the first input/output node. When in the second configuration, the first input/output node follows the second input/output node.

Abstract: A bus buffer can include a data buffer and a clock signal buffer. The data buffer for can include two symmetrical buffer circuits with an output signal that can follow the input voltage to provide bi-directional buffer action for a data path of the bus buffer. The clock buffer can operate in a forward or reverse direction, where the signal direction for the clock signal path in the bus buffer can be controlled with a direction input. The bus buffer can also include an enable circuit for enabling the data path and the clock signal path.

Abstract: A two-wire transmitter is connected to two transmission lines which transmit an electric signal regarding a physical quantity detected by a sensor. The two-wire transmitter includes a current control section which controls a transmission current of the electric signal, and a starter circuit which starts at a starting time of the two-wire transmitter so that the transmission current flowing through the current control section under steady operation of the two-wire transmitter detours the current control section to flow through the starter circuit. The starter circuit stops when an output voltage of the current control section reaches a predetermined value or more after the two-wire transmitter starts.

Abstract: A circuit with bi-directional signal transmission, including a first signal source, for generating a first signal comprising one bit per clock cycle during a first plurality of clock cycles, a second signal source, for generating a second signal including one bit per clock cycle during a second plurality of clock cycles, a first buffer, coupled with the first signal source, that outputs the first signal when the first buffer is enabled, a second buffer, coupled with the second signal source, that outputs the second signal when the second buffer is enabled, and a plurality of logical gates, coupled with the first signal source, the second signal source, the first buffer and the second buffer, that control enablement of the first buffer and the second buffer, such that (i) at any given clock cycle at least one of the first buffer and the second buffer is disabled, and (ii) when the first buffer and said the buffer are both disabled, subsequent generation of a ‘0’ bit in the first signal or the second signal cau

Abstract: A wireline transmission circuit includes a first circuit that produces a first variable current, a second circuit that produces a first static current, a trans-impedance amplifier that outputs a first analog signal at a first output node in response to the first variable current and the first static current received at a first input node, and a first feedback resistor connected to the first input node and the first output node.

Abstract: A communication system for the connection between timing non-correlated synchronous devices comprising at least one transmitter and one receiver inserted between a first and a second voltage reference and connected to each other through a transmission channel in correspondence with respective transmitting and receiving terminals Advantageously, the receiver comprises at least one asynchronous input stage suitable for receiving on the receiving terminal a datum and associated with a synchronous output stage suitable for transmitting this datum in a synchronized way with a clock signal on a synchronized receiving terminal. A method transmits a datum from a transmitter to a receiver interconnected by a capacitive channel in a communication system for the connection between independently clocked devices.

Abstract: An impedance buffer has a single comparator with a first input and a second input. A first leg has a first pull-up array in series with a reference resistor. The first input of the single comparator is electrically coupled to a node between the first pull up array and the reference resistor. A second leg has a second pull-up array in series with a pull-down array. The second leg is coupled through a switch to the second input of the single comparator.

Abstract: A differential transmission line that has three or more signal lines and with which there is little unwanted radiation noise is provided. The differential transmission line 2 is provided with three signal lines 2a, 2b, and 2c that transmit differential signals from a differential driver IC1 to a differential receiver IC3, and the majority of the signal lines 2a, 2b, and 2c is provided in conductor layers T2 and T3 of a printed circuit board 4.

Abstract: A low amplitude differential output circuit includes a pre-buffer circuit configured to output a main buffer drive signal of a-first drive signal and a second drive signal which are complimentary signals, as a differential signal; and a main buffer circuit connected with the pre-buffer circuit to output a differential output signal in response to the main buffer drive signal. Each of the first drive signal and the second drive signal has an amplitude between a first voltage and a second voltage, and the first drive signal and the second drive signal take a same voltage between the first voltage and a middle voltage between the first voltage and the second voltage.

Abstract: A method and circuit of a biased input buffer is described to maximize the quality in the output signals. The input buffer includes a first stage for receiving differential input signals and generating differential internal signals as biased in response to an averaging of the differential internal signals. The input buffer further includes a second stage coupled to the differential internal signals and configured to generate differential output signals. A memory device includes a memory array with the respective input buffer. Differential input signals are received and differential internal signals are generated as biased in response to an averaging of the differential internal signals. Differential output signals are generated in a second stage from the differential internal signals.

Abstract: Provided herein are bi-directional buffers, and methods for providing bi-directional buffering. In an embodiment, a bi-directional buffer includes a differential input/differential output amplifier that includes a first input/output node and a second/input output node. The differential input/differential output amplifier is configurable in a first configuration and a second configuration. When in the first configuration, the second input/output node follows the first input/output node. When in the second configuration, the first input/output node follows the second input/output node.

Abstract: To provide a transmitting apparatus capable of suppressing the fluctuation of a common mode potential and performing high-speed, long-distance signal transmission. The transmitting apparatus has a main buffer circuit and a pre-emphasis buffer circuit 20. The pre-emphasis buffer circuit 20, which has a switch circuit 21, a first current source 22, and a second current source 23, uses the switch circuit 21 to output a current signal having the same direction as an output current of the main buffer circuit 10 during a certain time interval starting from a time point when the level of data to be transmitted changes, and brings the output terminals 201, 202 to a High-Z state during a time interval when the level is constant after a lapse of the abovementioned certain time interval.

Abstract: A method and apparatus to reduce the degradation in performance of semiconductor-based devices due to process, voltage, and temperature (PVT) and/or other causes of variation. Adaptive feedback mechanisms are employed to sense and correct performance degradation, while simultaneously facilitating configurability within integrated circuits (ICs) such as programmable logic devices (PLDs). A voltage-feedback mechanism is employed to detect PVT variation and mirrored current references are adaptively adjusted to track and substantially eliminate the PVT variation. More than one voltage-feedback mechanism may instead be utilized to detect PVT-based variations within a differential device, whereby a first voltage-feedback mechanism is utilized to detect common-mode voltage variation and a second voltage-feedback mechanism produces mirrored reference currents to substantially remove the common-mode voltage variation and facilitate symmetrical operation of the differential device.

Abstract: A desaturation circuit for an IGBT is disclosed. In one embodiment, flooding of the component with charge carriers is reduced before the IGBT is turned off.

Abstract: Apparatus for configuring input/output signal levels of interfacing logic circuits operating at different voltage levels comprises: a logic circuit for operating at a first voltage level; a bank of input/output gates coupled to the logic circuit for interfacing input/output signals at a second voltage level, different from the first voltage level, to the logic circuit, the bank of gates including a port for setting the operational voltage level thereof; and a control circuit coupled to the port and governed by a control signal to configure the operational voltage level of the bank of gates to render the logic circuit and the interfacing input/output signals voltage level compatible.

Abstract: A communication system having first and second states for use with a shared transmission line composed of at least two conductors and composed of first and second transmission line segments connected to each other at a single connection point. In the first state, a termination is coupled to the single connection point and is operative to at least attenuate a signal propagated between the first and second segments. In the second state, a driver is coupled to the connection point and is operative to conduct a signal over the first and second segments.

Abstract: A transmission system and method may be provided. The transmission system may transmit 2-bit data for each transmission line set and each transmission line set may include first, second and/or third transmission lines arranged in order. The first, second and/or third transmission lines may respectively transmit first, second and/or third signals each having one of first, second and/or third values such that a combination of a first electric field between the first and second transmission lines and a second electric field between the second and third transmission lines may be made depending on a logic state of the 2-bit data. The transmission system may transmit differential signals using a smaller number of transmission lines and the transmission system may transmit a larger number of signals in the same circuit area.

Abstract: A power switching circuit in CMOS technology has a power MOS transistor and a driver stage. The power MOS transistor is operated at a higher supply voltage in excess of its maximum allowable gate-source voltage; and the driver stage of the level shifter is operated at a lower supply voltage substantially lower than the supply voltage for the power MOS transistor. The driver stage includes a pair of driver MOS transistors coupled in series between a higher supply voltage rail and a reference potential rail, and at an interconnection node coupled to the gate of the power MOS transistor. The gates of the driver MOS transistors are AC-coupled to drive signals of mutually opposite phase; and the gates of the driver MOS transistors are each connected to the higher voltage supply rail through a respective parallel connection of a first resistor and a second resistor connected in series with a non-linear component.

Abstract: A rail-to-rail high speed subLVDS receiver demonstrates good jitter and duty cycle performance for high-speed signals at low power supply levels. A sample receiver includes a voltage shifter for shifting the voltage levels of a differential input signal so that a shifted differential input signal is produced. The shifted differential input signal can be applied to a first differential pair, and the differential input signal can be applied to a second differential pair. The outputs of the first and second differential pairs can be summed together to produce a differential output signal. The differential output signal can be output using an output block. A clamp circuit can be used to adjust the gain of the first differential pair responsive to a common mode voltage of the first and second differential input signals.

Abstract: A low power Universal Serial Bus (USB) capable device uses a weak pull-up resistance that is coupled to at least one data line of the USB for detection of when the USB capable device is connected to a USB host or hub. When the USB capable device is not connected to the USB host or hub, USB peripheral, including the USB transceiver, USB voltage regulator, serial interface and/or USB logic circuits required for USB operation may be powered down to conserve power drawn by the USB capable device. When the USB capable device is connected to the USB host or hub, a voltage from the weak pull-up will be significantly reduced, thus signaling that the USB peripheral and associated circuits should be powered up for normal USB operation.

Abstract: A bi-directional buffer includes at least a first and second pair of one-shots and transistors. At least the first pair of one-shots and the first pair of transistors enable a second input/output (I/O) terminal to follow a first I/O terminal. At least the second pair of one-shots and the second pair of transistors enable the first I/O terminal to follow the second I/O terminal. There is a detection of whether the direction of a signal is from the first I/O terminal to second I/O terminal, or vise versa. If the direction is from the first I/O terminal to the second I/O terminal, there is an at least temporarily disabling the second pair of one-shots to thereby reduce feedback that may occur from the second I/O terminal to the first I/O terminal. If the direction is from the second I/O terminal to the first I/O terminal, there is an at least temporarily disabling the first pair of one-shots to thereby reduce feedback that may occur from the first I/O terminal to the second I/O terminal.

Abstract: A differential line compensation apparatus, semiconductor chip and system are disclosed.

Abstract: A wireline transmission circuit includes a first circuit that produces a first variable current, a second circuit that produces a first static current, a trans-impedance amplifier that outputs a first analog signal at a first output node in response to the first variable current and the first static current received at a first input node, and a first feedback resistor connected to the first input node and the first output node.

Abstract: Controlling on-die termination on a bi-directional single-ended data bus carrying data between a controller and a memory device. The controller and the memory device respectively include input termination pull-ups and input termination pull-downs. An enabled state is maintained for the input termination pull-downs of the controller except when data is driven on the bi-directional single ended data bus by the controller. Similarly, an enabled state is maintained for the set of input termination pull-downs of the memory device except when data is driven on the bi-directional single ended data bus by the memory device. In conjunction with this, a disabled state is maintained for the input termination pull-ups of the memory device (or controller) except when data is being received from the bi-directional single-ended data bus by the memory device (or controller).

Abstract: Apparatus for configuring input/output signal levels of interfacing logic circuits operating at different voltage levels comprises: a logic circuit for operating at a first voltage level; a bank of input/output gates coupled to the logic circuit for interfacing input/output signals at a second voltage level, different from the first voltage level, to the logic circuit, the bank of gates including a port for setting the operational voltage level thereof; and a control circuit coupled to the port and governed by a control signal to configure the operational voltage level of the bank of gates to render the logic circuit and the interfacing input/output signals voltage level compatible.