Abstract: A semiconductor device capable of stable operation with low power consumption is provided. A logic circuit having a circuit configuration using a transistor including an oxide semiconductor in a channel formation region is included. The logic circuit is a two-input/two-output two-wire logic circuit. Transistors included in the logic circuit each include a gate and a back gate. An input terminal is electrically connected to one of a gate and a back gate of a transistor electrically connected to a wiring for supplying a high power supply potential. An output terminal is connected to the other of the gate and the back gate of the transistor electrically connected to the wiring for supplying a high power supply potential. An output terminal is electrically connected to one of a source and a drain of a transistor electrically connected to a wiring for supplying a low power supply potential.

Abstract: A resistor-capacitor (RC) sensor circuit includes an integration capacitor configured to integrate a representative copy of a current that drives an electronic circuit line. The integration capacitor is configured to integrate over a first time period to generate a first representative voltage and over a second time period to generate a second representative voltage. The RC sensor circuit includes a sampling circuit coupled to the integration capacitor and configured to sample the first representative voltage and the second representative voltage. A ratio of the first sampled voltage and the second sampled voltage is indicative of an RC time constant of the electronic circuit line.

Abstract: An amplifier circuit for a millimeter wave (mmW) communication system includes an amplifier coupled to a matching network, and a variable gain control circuit in the matching network, the variable gain control circuit having an adjustable gain control resistance, the adjustable gain control resistance having adjustable segments and a center node therebetween, the center node coupled to an alternating current (AC) ground.

Abstract: In accordance with an embodiment, an integrated driver circuit includes: a first connection and a second connection configured to be connected to a control chip; at least one bus connection configured to be connected to a bus line; and a control circuit. The control circuit is configured to operate in a first mode or a second mode; to output a reception signal at the second connection in the second mode, where the reception signal represents a bus signal received at the bus connection; to assume a state of low power consumption in the first mode; to change from the first mode to the second mode when a first command is detected at the first connection or at the second connection; and to change from the second mode to the first mode when the bus signal does not indicate any data for a predefined period of time.

Abstract: A power converter device, includes switching devices and a controller, to realize conversion between power supplies by controlling on and off the switching devices via the controller. The switching devices include: at least one normally-on type switching device and at least one normally-off type switching device both having an operation frequency greater than 1 kHz and connected in series. The controller outputs a first and second control signal to correspondingly control the normally-on type switching device and the normally-off type switching device to control the normally-off type switching device to be turned on after the normally-on type switching device to be turned off. The present disclosure uses the normally-off type switching device originally disposed in the circuit, having a voltage blocking ability, to realize directly usage of the normally-on type switching device to improve efficiency and power density of switching power supply.

Abstract: A signal shaping circuit that shapes a drive signal and includes a main-signal amplifying circuit that amplifies the drive signal; a preemphasis generating circuit that symmetrically emphasizes a rising portion and a falling portion of the drive signal; a current source that is provided in the main-signal amplifying circuit; and a condenser that couples the main-signal amplifying circuit and the preemphasis generating circuit.

Abstract: A gate drive circuit includes a turn-on circuit having an upper limiter for receiving a gate drive signal. The upper limiter has an output terminal. The turn-on circuit also has a transistor having a base connected to the output terminal of the upper limiter. In addition, the terminal has a terminal connected to a gate of a power switching device. The upper limiter limits a voltage input to the base of the transistor to not exceed a first predetermined value.

Abstract: An electronic control apparatus includes a switching element having a control terminal; an ON-drive constant-current circuit for supplying a constant current to the control terminal, thereby charging the control terminal of the switching element with electrical charge; an OFF-drive switching element for discharging electrical charge from the control terminal of the switching element by being turned ON; and a control circuit adapted to control the ON-drive constant-current circuit and the OFF-drive switching element in response to a drive signal being inputted, thereby controlling the voltage of the control terminal of the switching element to drive the switching element. The ON-drive constant-current circuit includes a current control transistor and a current detection element.

Abstract: In accordance with an embodiment, a method of driving switches includes sensing a control node of a first switch, sensing a control node of a second switch, and driving the control node of the first switch to a first active state after the control node of the second switch transitions to a second active state. The method also includes driving the control node of the second switch to a second inactive state after the control node of the first switch transitions to a first inactive state. Driving the control node of the first switch is based on sensing the control node of the second switch, and driving the control node of the second switch is based on based on sensing the control node of the first switch.

Abstract: A DC-coupled two-stage gate driver circuit for driving a junction field effect transistor (JFET) is provided. The JFET can be a wide bandgap junction field effect transistor (JFET) such as a SiC JFET. The driver includes a first turn-on circuit, a second turn-on circuit and a pull-down circuit. The driver is configured to accept an input pulse-width modulation (PWM) control signal and generate an output driver signal for driving the gate of the JFET.

Abstract: Methods and circuits related to a driving circuit with zero current shutdown are disclosed. In one embodiment, a driving circuit with zero current shutdown can include: a linear regulating circuit that receives an input voltage source, and outputs an output voltage; a start-up circuit having a threshold voltage, the start-up circuit receiving an external enable signal; a first power switch receiving both the output voltage of the linear regulating circuit and the external enable signal, and that generates an internal enable signal, the internal enable signal being configured to drive a logic circuit; when the external enable signal is lower than a threshold voltage, the driving circuit is not effective; when the external enable signal is higher than the threshold voltage, the start-up circuit outputs a first current; and where the output voltage at the first output terminal is generated by the linear regulating circuit based on the first current.

Abstract: A receiver and a method for dynamically adjusting sensitivity of the receiver are provided. The receiver includes a detection unit and a receiving unit. The detection unit detects an input signal group, and outputs a detection result. The receiving unit receives the input signal group according to a sensitivity. Wherein, the receiving unit dynamically adjusts the sensitivity used for receiving the input signal group according to the detection result of the detection unit.

Abstract: A level switch circuit receives a digital input signal, and generates a level signal having a voltage level that corresponds to the value of the input signal thus received. A buffer circuit receives a level signal, and outputs the level signal via an output terminal thereof. A bias current generating circuit generates a bias current including a DC component having a constant level and a variable component that changes according to the input signal, and supplies the bias current thus generated to a buffer circuit. The bias current generating circuit detects an edge of the input signal, and raises the bias current by a predetermined amount for a predetermined period of time after the edge thus detected.

Abstract: A desaturation circuit for an IGBT is disclosed. In one embodiment, flooding of the component with charge carriers is reduced before the IGBT is turned off.

Abstract: A bi-directional buffer is connected between a first node and a second node, wherein the first node is connected by a first pull-up resistor to a first voltage supply rail, and the second node is connected by a second pull-up resistor to a second voltage supply rail. In an embodiment, the bi-directional buffer is enabled when a voltage of the first node does not exceed a first threshold voltage, and/or a voltage of the second node does not exceed a second threshold voltage. However, when the voltage of the first node exceeds the first threshold voltage, and the voltage of the second node exceeds the second threshold voltage, the bi-directional buffer is disabled, which disconnects the first and second nodes. This allows the first node to be pulled up to the first voltage supply rail, and the second node to be pulled up to the second voltage supply rail.

Abstract: A CMOS output driver is provided for driving a capacitive load over a circuit trace in high speed applications. The CMOS output driver comprises a signal input and a signal output. The output driver has a first buffer amplifier with an input connected to the signal input and an output connected to the signal output through a resistor. A second buffer amplifier is also provided, which has an input connected to the signal input and an output connected to the signal output through a capacitor.

Abstract: There is provided a switching circuit including, a semiconductor switching circuit comprising, a transistor, a first electrode of the transistor being connected to an electrical source via a load, a second electrode of the transistor being connected to a standard potential, a driving circuit outputting a signal to a control electrode of the transistor on a basis of a potential in the first electrode of the transistor so as to turn on and off the transistor, the driving circuit turning on when an input voltage applied from an input terminal being a first voltage higher than a threshold voltage of the transistor, the driving circuit turning off when the input voltage being a second voltage lower than the threshold voltage of the transistor.

Abstract: A rail-to-rail high speed subLVDS receiver demonstrates good jitter and duty cycle performance for high-speed signals at low power supply levels. A sample receiver includes a voltage shifter for shifting the voltage levels of a differential input signal so that a shifted differential input signal is produced. The shifted differential input signal can be applied to a first differential pair, and the differential input signal can be applied to a second differential pair. The outputs of the first and second differential pairs can be summed together to produce a differential output signal. The differential output signal can be output using an output block. A clamp circuit can be used to adjust the gain of the first differential pair responsive to a common mode voltage of the first and second differential input signals.

Abstract: A driver circuit including an amplifier, which generates a control signal from a reference signal; a driver current mirror; and a control current switch located between the amplifier and the driver current mirror which selectably isolates the driver current mirror from the amplifier or connects the driver current mirror to the amplifier, wherein the driver current mirror, when in a state connected to the amplifier, amplifies the control signal into a driver signal. A compensating circuit is provided that generates a correction signal, as a function of an error current of the driver current mirror and provides the correction signal to an input of the amplifier, wherein a feedback signal input of the amplifier is fed through a feedback path from a feedback signal coupled out of a control branch of the driver current mirror, and the compensating circuit additively provides the correction signal at an input of the amplifier.

Abstract: A pull-up circuit comprises an operational amplifier which forms part of a feedback circuit, acting to bring a pull-up circuit output equal to a reference voltage input. The pull-up circuit may form part of a USB transceiver for incorporation in a USB Device. When the supply voltage of the USB Device is sufficiently high, it is used to provide the required pull-up voltage, with the feedback circuit including the operational amplifier the USB Device is not high enough to provide the required pull-up voltage. In that case, the USB bus voltage is used to generate the reference voltage which is used as an input to the feedback circuit.

Abstract: An integrated circuit includes a current mirror circuit for providing a current at an output end, a power-down switch coupled to the output end of the current mirror circuit for controlling access of the current generated by the current mirror circuit based on signals received at a control end of the power-down switch, and a compensating unit coupled to a bias end of the current mirror circuit and the power-down switch for stabilizing voltages at the bias end of the current mirror circuit.

Abstract: A bi-directional signal transmission system including, a first bi-directional signal path having circuitry adapted to generate a logic high level on said first path, one or more first stations connected to the first bi-directional signal path adapted to monitor a logic level on said first path, and to generate a logic low level on said first path, an interface device operatively coupled to the first bi-directional signal path, said interface device having a first receive input also capable of functioning as an output capable of pulling the first path low; and a second bi-directional signal path coupled to a transmit output and a receive input on the buffered side of the interface device, said interface device includes a first means for generating on the first bi-directional signal path a medium logic level in response to a low level on the receive input on the buffered side, and a second means for generating on the transmit output on the buffered side, a low logic level in response to a low level on the first

Abstract: A drive circuit of a computer system is for driving a mode indicator. The computer system includes a first port and a second port. The mode indicator includes a first receiving end and a second receiving end. The drive circuit includes a first input end connected to the first port, a second input end connected to the second port, a first output end connected to the first receiving end, a second output end connected to the second receiving end. A power supply is connected to the first input end and the second input end via a first resistor and a second resistor respectively. The mode indicator is dichromatic and has two LEDs emitting non-matching colored light.

Abstract: A differential transmission line driver with supplemental current sources that overcome switching anomalies and EMU issues when the logic state of the driver is switching. During a logic transition, a current source, that is directed to the output of the driver, may be prevented from delivering its current. The present invention provides a supplemental current that is active during this transition period to supply the missing current. The present disclosure also details a common mode circuit that maintains a stable common mode output level to help control EMI issues when the power supply for the driver changes.

Abstract: A bi-directional bus buffer for applications using the I2C and SMBus, or other bus systems operating on similar principles, able to extend the bus load limit by buffering both the SCL and SDA (clock and data) lines, allowing capacitive loads of up to the limit of 400 pF on both sides of the buffer. With the use of an enable function, sections of the bus can be isolated, and then, thorough the use of a number of these buffers, different parts of the system are able to be isolated, and brought on-line successively or in a controlled manner, permitting a controlled start-up, and operation at maximum performance speeds while still having a diverse range of components, operating speeds and loads.

Abstract: An apparatus and method for driving an output signal in a high speed integrated circuit. The apparatus and methods enable the output voltage swing from the driver to exceed the breakdown voltage of any individual element in the output driver. A high speed driver can utilize one or more transistors in a stacked configuration, such that the breakdown voltage of the entire stacked configuration is based on the number of transistors in the stack. The driver is configured to distribute the output voltage substantially equally among each of the stacked transistors, such that the driver is able to source an output voltage swing that is greater than the breakdown voltage of any individual transistor in the driver.

Abstract: In accordance with the present invention, the circuit apparatus has a first and a second connection point each for respectively connecting to the first bay and second bay for communicating with them to determine which device in the bays is the master device. The circuit apparatus also has a third and a fourth connection point both of them for connecting to the first bay or second bay for receiving the Boolean algebra to determine which device is the master device. The circuit apparatus further has a fifth connection point for determining whether the circuit apparatus works.

Abstract: A high-side driver circuit for driving a load, including a low-side driver IC having a drive output and a feedback input, a first transistor coupled to the drive output, and a second transistor coupled between a power source and the load. The second transistor is configured to enter an “OFF” state when the first transistor is driven into an “OFF” state by the drive output, and to enter an “ON” state when the first transistor is driven into an “ON” state by the drive output.

Abstract: An output driving circuit has a first and second differential output nodes connected to a first and second external output terminals, respectively. A capacitance connection circuit is connected between the first and second differential output nodes. The capacitance connection circuit connects a capacitance between the first and second differential output nodes. The capacitance connection circuit then adjusts the value of the capacitance in accordance with a control signal.

Abstract: In one embodiment, a differential transistor pair of an ECL differential amplifier is formed on two different semiconductor die.

Abstract: There is provided an amplitude varying driver circuit operable to output an output signal, which is an amplified input signal being supplied. The amplitude varying driver circuit includes: a plurality of differential amplifiers provided in parallel with one another, wherein a signal corresponding to the input signal is input into each base terminal thereof; a resistor section, which is provided in series with the plurality of differential amplifiers, operable to establish potential of the output signal according to total current flowing to the plurality of differential amplifiers; and an amplitude control transistor, which is provided in series with the plurality of differential amplifiers, operable to define total current flowing to the plurality of differential amplifiers.

Abstract: A semiconductor integrated circuit device includes a semiconductor integrated circuit formed in a semiconductor chip, and a switching element that is formed in the semiconductor chip and has a current path whose one end and the other end are both connected to the semiconductor integrated circuit. The switching element receives a control signal produced by a control circuit and causes a current to flow from the one end to the other end of the current path by a bipolar operation. The semiconductor integrated circuit device further includes the control circuit that is formed in the semiconductor chip and configured to control a conductive/non-conductive state of the current path of the switching element.

Abstract: A high voltage circuit driver includes high and low side driver cells to drive a high and a low side power MOSFET, a bootstrap circuit to energize the high side driver cell, a high voltage PMOS transistor (HVPMOS) between a voltage source and the bootstrap circuit, wherein the HVPMOS is embedded in an N-isolation layer and is integrated with the driver cells. A bootstrap control circuit, for controlling the HVPMOS, includes a high voltage level shift stage, which can also be embedded in an N-isolation layer. The circuit driver is operated by switching the high side drive signal from high to low, the low side drive signal from low to high with a first delay, and a bootstrap control signal from high to low with an additional second delay. Also, the bootstrap capacitor is first charged by switching on the HVPMOS, and then it energizes the high side driver cell.

Abstract: A high speed switch. The novel switch includes an input circuit having a transistor Q1 for receiving an input signal, a first mechanism for providing a path from an output of Q1 to an output terminal, and a second mechanism for receiving a control signal and in accordance therewith reducing the conductivity of the path during a mute mode. The first mechanism includes a first circuit for providing a first path from an output of Q1 to a first node, and a second circuit for providing a second path connecting the first node to the output terminal. The second mechanism is adapted to apply a signal to the first node during the mute mode such that the first and second circuits are off or partially conducting. The switch also includes a circuit for clamping the first node to a first predetermined voltage during the mute mode.

Abstract: A multi-threshold complementary metal-oxide semiconductor (MTCMO) bus circuit reduces bus power consumption via a reduced circuit leakage standby and pulsed control of standby mode so that the advantages of MTCMOS repeater design are realized in dynamic operation. A pulse generator pulses the high-threshold voltage power supply rail standby switching devices in response to changes detected at the bus circuit inputs. The delay penalty associated with leaving the standby mode is overcome by reducing cross-talk induced delay via a cross-talk noise minimization encoding and decoding scheme. A subgroup of bus wires is encoded and decoded, simplifying the encoding, decoding and change detection logic and results in the bus subgroup being taken out of standby mode only when changes occur in one or more of the subgroup inputs, further reducing the power consumption of the overall bus circuit.

Abstract: When a potential of a power supply line varies according to a flowing current, the gate-source voltage Vgs of a transistor also varies, leading to variations in the constant current between each source follower. In order to solve this problem, a potential Vb of the gate terminal of a transistor as a constant current source is changed in the same manner as a power supply line Vss which is connected to the source terminal of the transistor. Therefore, variations in the constant current are suppressed and variations in the output of the source followers are thus suppressed. In addition, by connecting the circuit having source followers to the output side of a signal line driver circuit, it can be prevented that luminance unevenness of a striped pattern is recognized in a display portion of a semiconductor device.

Abstract: The invention concerns a switching circuit (20) adapted to generate a pulse when there occurs a rising edge of a signal applied on an input terminal (CTRL), comprising: a first NPN type bipolar transistor (TN2) whereof the transmitter is connected to the input terminal; a second transistor (TP2) whereof a control electrode is connected, through a first resistor (Re2), to the input terminal, the base of the first transistor being connected to a supply potential (VDD) by the second transistor in series with a second resistor (Rp2); and a third transistor (TN3) connecting an output terminal (22) of the switching circuit to a reference potential (GND) and whereof a control electrode is connected to the collector of the first transistor (TN2).

Abstract: A system and method is described for a driver circuit used for high speed data transmission in LVDS and CML transceiver device applications. The transceivers are intended to receive a low voltage differential input signal and interchangeably drive a standard LVDS load with a TIA/EIA-644 compliant LVDS signal, and a standard CML load with a standard CML compatible signal. The driver circuit operates at speeds up to 1.36 Gbps, making it compatible with the OC-24 signaling rate for optical transmission. To accomplish this, the driver uses a mixed combination of voltage and current mode drive sections in the output circuit when coupled to LVDS loads, and when the driver is coupled to CML loads, operates purely in a current mode using only the current mode drive section.

Abstract: An apparatus for interfacing an integrated circuit with external circuitry includes a transistor having an emitter coupled to a node for receiving a control current (IP) from the integrated circuit. A beta compensator disposed within the integrated circuit provides a compensating current (IM) to the node. The compensating current IM is proportional to a base current (IB) of the transistor. A method of interfacing the integrated circuit with external circuitry includes the step of providing the control current (IP) from the integrated circuit to a node coupled to a transistor emitter. A compensating current (IM) is provided to the node in response to the transistor base current (IB). The net node current provided to the emitter is IP+IB so that the transistor collector current is substantially the same as the control current. The transistor collector is coupled to the external circuitry.

Abstract: An electronic structure for passing signals across voltage differences includes a signal bus segment that includes at least one circuit element. Circuitry connected to the signal bus segment is operatively connected to a voltage source. Signal bus segments and the associated circuitry can be stacked and connected to corresponding stacked voltage sources. This allows a signal to be passed to a particular circuit, regardless of the voltage difference between the source circuit and the desired circuit.

Abstract: A logic buffer includes a logic gate having at least two input terminals and two output nodes, a plurality of output terminals, each having a capacitance associated therewith and a pull-up circuit interconnected between each output node and the plurality of output terminals for alternately charging the capacitance of each output terminal. The buffer also includes a differential pull-down circuit including a common pull-down current source, the pull-down device interconnected between the output nodes and the output terminals for inversely alternately discharging the capacitances through the common pull-down current source for accelerating the discharge of the capacitance of the respective output terminal.

Abstract: Interface circuitry for linking an automobile diagnostic scanner to the electronic control unit of an automobile. The disclosed circuitry provides a lower cost, reduced board space solution for an universal scan tool interface circuitry.

Abstract: The circuit configuration for converting logic levels has a bipolar input stage and a CMOS output stage. The bipolar input stage is equipped to process ECL and CML logic levels. The CMOS-logic output stage is equipped to supply trailing CMOS gates having CMOS logic levels. A difference amplifier includes bipolar transistors, which are connected to a common emitter current source and to separate collector current sources. An input-output feedback CMOS inverter is connected to one of the collectors, and the output of the inverter is coupled to an output node.

Abstract: An active termination circuit for clamping a signal on a transmission line in an electronic device is described. The active termination circuit is configured to clamp the signal on the transmission line to one of a first reference voltage level and a second reference voltage level. The active termination circuit includes a bottom clamping transistor having a bottom clamping transistor first node coupled to a transmission line at a transmission line node, a bottom clamping transistor second node coupled to a first potential, and a bottom clamping transistor control node coupled to a first bias voltage supply. The circuit also includes a top clamping transistor having a top clamping transistor first node coupled to the transmission line at the transmission line node, a top clamping transistor second node coupled to a second potential, and a top clamping transistor control node coupled to a second bias voltage supply.

Abstract: An electric current switch circuit in accordance with the present invention is arranged so that an output of an IIL logic circuit is connected with the base of the first transistor of NPN type that switches ON or OFF the electric current. The first constant current source and the second transistor cause the first transistor to switch ON during a period when the output of the IIL logic circuit is in an OFF state, to switch OFF during a period when the output of the IIL logic circuit is in an ON state. Thus, only a voltage of 0.9V to 1.1V (the sum of a drop voltage across the first resistor and the base-emitter voltage) is applied to the base of the first transistor. Accordingly, a voltage less than the withstand voltage of the IIL logic circuit is applied to the base of the first transistor.

Abstract: A decoding apparatus for transmitting a high voltage signal includes a final decoder for switchably transmitting a transmission signal. The final decoder has a switching device that has at least one depletion-mode-type field effect transistor and/or field effect transistor having a low threshold voltage (i.e., 0.1 to 0.4 V), in particular, a low VT field effect transistor. A transmission signal line supplies the transmission signal to the decoder, a driver signal line supplies a driver signal to the decoder, and an output signal line outputs an output signal from the decoder. The driver signal line applies the driver signal to the gate line, the transmission signal line applies the transmission signal to the source line. The field effect transistor is configured to selectively connect the output signal to the output signal line device through the output in response to a reset of the driver signal. The configuration reduces the likelihood of channel degradation and of failure in the field effect transistor.

Abstract: Described is a control circuit for an output stage for suppressing electrical and electromagnetic interference having a signal input (I), a signal output (O), and a ground terminal, two switch stages (1; 2) which are connected to the signal input (I) and the ground and which have one control terminal and one output terminal each, each switch stage (1; 2) switching over from a first state in which the potential at the output terminal follows the potential at the signal input (I) to a second state in which the potential at the output terminal is drawn to ground when a first or second threshold value (Uin1, Uin2) is exceeded at its control terminal, the control terminal (4) of the first switch stage (1) being connected to an intermediary potential, which is between the potential at the signal input (I) and ground, the output terminal (5) of the first switch stage (1) forming the control terminal of the second switch stage (2), the output terminal of the second switch stage forming the signal output (O) of the co

Abstract: An input driver for use with a differential folder in a flash A/D converter having a static ladder that provides an array of reference voltages and a method of operation thereof. The input driver includes a differential signal driver, coupled to an AC input signal, that generates first and second complementary drive signals for a differential folder stage. A tracking circuit, coupled to the differential signal driver, is utilized to maintain a voltage at the center of the static ladder to improve common mode rejection of the input driver without reducing bandwidth. In a related embodiment, the voltage at the center of the static ladder is an average DC voltage of the first and second drive signals.

Abstract: The invention relates to methods and apparatus that efficiently convert a single-ended input signal to a differential output signal at high speeds so that a non-inverted differential output and an inverted differential output maintain a true differential phase relationship even at relatively high frequencies of input data. A single-to-differential input buffer circuit includes multiple paths from the input signal to the differential output signals and transitions relatively quickly from a first state to a second state in response to a change in state of the input signal. An input phase-splitting stage of the single-to-differential input buffer circuit includes cross-coupled positive feedback to dramatically increase the frequency response of the phase-splitting stage.

Abstract: A bipolar drive circuit comprises a differential or single-ended current mirror with signal inputs and outputs connected via resistors to a low voltage supply, e.g. 1.5 volts. A signal output voltage swing is determined and stabilized by a compensation circuit comprising a transistor having a base supplied with a reference voltage, a collector coupled via a resistor to the low voltage supply, and an emitter coupled via a resistor to ground, and a current mirror having an input coupled to the collector of the transistor and a current mirror output coupled to each signal input. A plurality of current mirror circuits can be connected in cascade, and the signal output voltage swing of each current mirror circuit can be similarly determined. The arrangement facilitates providing a drive circuit with high frequency, low supply voltage, and low power operation without transistor saturation.