Abstract: A switching circuit includes: a drive power supply; a first transistor and a second transistor; a drive signal source; and a drive circuit. Each of the first transistor and the second transistor includes: a drain electrode and a source electrode in which a main current flows when a corresponding one of the first transistor and the second transistor is ON; a first source terminal for passing the main current; and a second source terminal. Here, the first source terminal is connected to the source electrode at an impedance lower than an impedance of the second source terminal.

Abstract: A storage control apparatus includes a detection unit that detects a soft error of a memory for setting information included in a programmable logic circuit, when the soft error is detected, a communication control unit that changes a state of a communication path between the communication device and an upper device to a busy state, and a recovery processing unit that performs recovery processing of the memory for setting information of the programmable logic circuit, thereby efficiently resolving a soft error of the programmable logic circuit.

Abstract: The present invention aims to provide a power converter with an arm including switching devices connected in parallel, realizing long lifespans of switching devices. An inverter includes an upper and a lower arm, and gate drive circuits each driving the corresponding arm according to a gate control signal Gup_s indicating ON/OFF periods. Each arm includes switching devices connected in parallel. Each gate drive circuit includes: a switching gate control circuit 230u bringing a switching device 210u into conduction at the beginning of the ON period and bringing the same out of conduction within the ON period; and a conduction gate control circuit 231u bringing switching devices 211u and 212u within a period from when the switching device 210u is brought into conduction until the same is brought out of conduction, wherein the switching device 210u has a lower parasitic capacitance than the switching devices 211u and the 212u.

Abstract: The present invention provides a display device which can achieve the high breakdown voltage proof property, the enhancement of reliability or the expansion of the designing/process tolerance of transistors by the improvement of a circuit. A display device includes a plurality of pixels and a drive circuit which drives the plurality of pixels.

Abstract: A driving strength control circuit and a data output circuit for controlling driving strength of a data driver based on a user's demand are provided to make it possible to control the driving strength through a fuse cutting. The driving strength control circuit includes a fuse signal generating unit for generating a fuse signal based on a fuse cutting, a select signal generating unit for generating select signals in response to the fuse signal, a driving control signal generating unit for receiving set-up signals and generate driving control signals in response to the select signals, and a driving signal generating unit for driving signals by decoding the driving control signals.

Abstract: An impedance buffer has a single comparator with a first input and a second input. A first leg has a first pull-up array in series with a reference resistor. The first input of the single comparator is electrically coupled to a node between the first pull up array and the reference resistor. A second leg has a second pull-up array in series with a pull-down array. The second leg is coupled through a switch to the second input of the single comparator.

Abstract: A power switching circuit in CMOS technology has a power MOS transistor and a driver stage. The power MOS transistor is operated at a higher supply voltage in excess of its maximum allowable gate-source voltage; and the driver stage of the level shifter is operated at a lower supply voltage substantially lower than the supply voltage for the power MOS transistor. The driver stage includes a pair of driver MOS transistors coupled in series between a higher supply voltage rail and a reference potential rail, and at an interconnection node coupled to the gate of the power MOS transistor. The gates of the driver MOS transistors are AC-coupled to drive signals of mutually opposite phase; and the gates of the driver MOS transistors are each connected to the higher voltage supply rail through a respective parallel connection of a first resistor and a second resistor connected in series with a non-linear component.

Abstract: A rail-to-rail high speed subLVDS receiver demonstrates good jitter and duty cycle performance for high-speed signals at low power supply levels. A sample receiver includes a voltage shifter for shifting the voltage levels of a differential input signal so that a shifted differential input signal is produced. The shifted differential input signal can be applied to a first differential pair, and the differential input signal can be applied to a second differential pair. The outputs of the first and second differential pairs can be summed together to produce a differential output signal. The differential output signal can be output using an output block. A clamp circuit can be used to adjust the gain of the first differential pair responsive to a common mode voltage of the first and second differential input signals.

Abstract: Stable testing is performed on an input and output circuit. An output stage outputting output signal to input/output terminal DQ comprises: a differential pair formed from an Nch transistor N1, having as load a Pch transistor P1 and resistance element R1, and an Nch transistor N2, having as load a Pch transistor P2 and resistance element R2; and an Nch transistor N3 supplying operating current to the differential pair. The input/output terminal DQ is connected to the drain of the Nch transistor N1. The output stage is operated as differential pair, in the normal operation mode (TM=L), wherein the Pch transistors P1, P2 are ON, a read-data signal RD is supplied to the differential pair, and a specified voltage CC is supplied to the gate of the Nch transistor N3; and in the test mode (TM=H), a CMOS circuit is established wherein a read-data signal RD is supplied to the gate of the Pch transistor P1 and the gate of the Nch transistor N3, turning the Nch transistor N1 ON.

Abstract: A pull-up circuit comprises an operational amplifier which forms part of a feedback circuit, acting to bring a pull-up circuit output equal to a reference voltage input. The pull-up circuit may form part of a USB transceiver for incorporation in a USB Device. When the supply voltage of the USB Device is sufficiently high, it is used to provide the required pull-up voltage, with the feedback circuit including the operational amplifier the USB Device is not high enough to provide the required pull-up voltage. In that case, the USB bus voltage is used to generate the reference voltage which is used as an input to the feedback circuit.

Abstract: A rapid response push-up pull-down buffer circuit configuration is used as an output buffer of a semiconductor memory device. The buffer circuit includes a pre-driver outputting a driving signal in response to an input data. The buffer circuit also includes an output driver driving an output signal in response to the driving signal which also has a driving strength adjusted in response to a level of the output signal. Accordingly, the driving strength can be automatically controlled in response to a level of the output signal which also results in enhancing the response speed of the buffer circuit.

Abstract: A differential transmission line driver with supplemental current sources that overcome switching anomalies and EMU issues when the logic state of the driver is switching. During a logic transition, a current source, that is directed to the output of the driver, may be prevented from delivering its current. The present invention provides a supplemental current that is active during this transition period to supply the missing current. The present disclosure also details a common mode circuit that maintains a stable common mode output level to help control EMI issues when the power supply for the driver changes.

Abstract: A signaling circuit having reduced parasitic capacitance. The signaling circuit includes a plurality of driver circuits each having an output coupled to a first output node, and a plurality of select circuits each having an output coupled to a control input of a corresponding one of the driver circuits. Each of the select circuits includes a control input to receive a respective select signal and a plurality of data inputs to receive a plurality of data signals. Each of the select circuits is adapted to select, according to the respective select signal, one of the plurality of data signals to be output to the control input of the corresponding one of the driver circuits.

Abstract: A circuit for adaptively adjusting the drive strength of output power transistors in a class D amplifier is provided. The circuit includes a driver circuit and a low-voltage detect circuit. The low-voltage detect circuit is arranged to assert a low-voltage detect signal if a low supply voltage condition is detected. The driver circuit is arranged to increase the drive strength if the low-voltage detect signal is asserted. The driver circuit includes a first driver and a second driver. The second driver is enabled if the low-voltage detect signal is asserted, and disabled if the low-voltage detect signal is unasserted.

Abstract: An electronic circuit includes at least one differential pair of transistors, a control transistor switch, a first current source and a second current source. The second current source is connected to a common emitter node of the pair of transistors in order to accelerate the discharge of parasitic capacitances during a switching operation.

Abstract: An input/output buffer comprises an input/output pad operable to receive an input signal and transmit an output signal, an output driver coupled to the input/output pad, an input path comprising an input transistor coupled to the input/output pad operable to pass an input signal received at the input/output pad to a core circuit coupled to the input/output buffer. The input/output buffer further comprises an output path coupled to the output driver operable to pass an output signal received from the core circuit to the input/output pad, a feedback path coupled to the input transistor in the input path and operable to cut off the output path during input mode, and a biasing circuit coupled to selected transistors in the output path, feedback path and output driver.

Abstract: A method and apparatus for an output buffer with dynamic impedance control have been disclosed.

Abstract: A driver circuit for switching an output voltage (Vout) at an output terminal 3 by using diode bridges 1 and 2 includes a first current mirror circuit 10 for letting flow a first balance current I2e and letting flow a first transition current I2f obtained by adding a first stationary current to a product of the first balance current I2e and a predetermined multiplier when switching from the low level to the high level, and a second current mirror circuit 20 for letting flow a second transition current I2h obtained by adding a second stationary current to a product of the second balance current I2g and a predetermined multiplier when switching from the high level to the low level. As a result, the power dissipation in the stationary state is reduced without lowering the slew rate at the time when switching the output voltage.

Abstract: A system and method is described for a driver circuit used for high speed data transmission in LVDS and CML transceiver device applications. The transceivers are intended to receive a low voltage differential input signal and interchangeably drive a standard LVDS load with a TIA/EIA-644 compliant LVDS signal, and a standard CML load with a standard CML compatible signal. The driver circuit operates at speeds up to 1.36 Gbps, making it compatible with the OC-24 signaling rate for optical transmission. To accomplish this, the driver uses a mixed combination of voltage and current mode drive sections in the output circuit when coupled to LVDS loads, and when the driver is coupled to CML loads, operates purely in a current mode using only the current mode drive section.

Abstract: An apparatus for converting a differential mode signal into a single ended signal with reduced power consumption. A preferred embodiment comprises a single ended converter (for example, a single ended converter 505) and an output transistor (for example, output transistor 524) that when the single ended converter 505 is in standby may pull the output of the single ended converter 505 to a known logic state (such as high logic or low logic). A single ended buffer (inverting or non-inverting) may be used for output signal compatibility conversion.

Abstract: An impedance control circuit includes a reference voltage output circuit for outputting one of a plurality of reference voltages; a variable resistor; a comparator and a control circuit. The comparator includes a first input terminal supplied with a reference voltage from the reference voltage output circuit and a second input terminal connected to the variable resistor, and compares the voltages at the first and second input terminals. The control circuit controls the variable resistor and establishes a plurality of impedances corresponding to the reference voltages in response to the signal output from the comparator. It enables the single impedance control circuit to control the plurality of different impedances on the semiconductor integrated circuit.

Abstract: A symmetric current mode logic with symmetric input loads as well as identical input logic levels at the input terminals so as to prevent phase error due to level adjustment and to further avoid signal surges due to current steering by parallel switching.

Abstract: A driver circuit for switching an output voltage (Vout) at an output terminal 3 by using diode bridges 1 and 2 includes a first current mirror circuit 10 for letting flow a first balance current I2e and letting flow a first transition current I2f obtained by adding a first stationary current to a product of the first balance current I2e and a predetermined multiplier when switching from the low level to the high level, and a second current mirror circuit 20 for letting flow a second transition current I2h obtained by adding a second stationary current to a product of the second balance current I2g and a predetermined multiplier when switching from the high level to the low level. As a result, the power dissipation in the stationary state is reduced without lowering the slew rate at the time when switching the output voltage.

Abstract: A static logic circuit with a pull-up network (155) and a pull-down network (160). The network is fabricated on SOI substrates and the pull-up network comprises at least one NMOS transistor (115) and the pull down network comprises at least one PMOS transistor (120).

Abstract: A current mode data communication system is disclosed. The current mode data communication system has a transmitter to simultaneously transmit two digital data bits. The two digital data bits are combined to form a current mode signal. The current mode signal has a first positive current, a second positive current, a first negative current and a first positive current. The current mode signal will be transmitted on a double bit current mode bus. Further the current mode communication system has a receiver coupled to the double bit current mode bus to receive the current mode signal and convert the current mode signal to a unextracted form of the two digital data bits. The output of the receiver is connected to a data extractor circuit extract the two digital data bits for the unextracted form of the two digital data bits.

Abstract: Method and circuitry for differential output driver with monotonic output transitions. The switching sequence for the output driver transistors of the differential driver changes depending on the direction of the input signal transition. When the input makes a binary transition from high to low, each one of the output driver transistors is switched on or off at a different time based on a first predetermined sequence. When the input makes the opposite binary transition (low to high), each one of the output driver transistors is switched on or off at a different time based on a second predetermined sequence that is different than the first sequence. The predetermined sequences are designed to eliminate any possibility of a glitch or non-monotonic behavior at the output terminals.

Abstract: A radiation-tolerant logic circuit includes three similarly configured SRAM-based PLDs. These PLDs work in parallel to provide identical logic functions. To guard against data corruption that can result from radiation-induced upsets, the logic circuit includes a state-comparison circuit that periodically performs a bitwise comparison of the configuration and user data from each of the PLDs; if a bit from one PLD differs from the corresponding bit from the others, the state-comparison circuit sets a flag that indicates that the differing PLD is in error. The erroneous PLD is then reprogrammed using error-free state data. In one embodiment, the error-free state data is read from an error-free PLD.

Abstract: Briefly, in accordance with one embodiment of the invention, an integrated circuit includes: two transistors coupled together in the integrated circuit so that upon the application of complementary voltage signals, electrical charge is substantially evenly distributed between output nodes. Briefly, in accordance with one more embodiment of the invention, an integrated circuit includes: a charge recycle circuit including two transistors. Briefly, in accordance with another embodiment of the invention, an integrated circuit includes: a charge recycle circuit including a first and second transistor coupled so as to respectively receive complementary voltage signals at the control voltage port of the first and second transistors. The transistors have a threshold voltage level different from the threshold voltage level of other transistors coupled to the charge recycle circuit.

Abstract: Disclosed is an integrated circuit comprising storage circuits, these circuits themselves comprising insulation transistors to which a determined positive bias voltage may be applied. This bias voltage is determined by means of a first bias circuit. The disclosed circuit comprises a second bias circuit whose time constant in response to a voltage step is smaller than the time constant of the first circuit in response to the same step, this second circuit making it possible to reduce the response time of the first bias circuit.

Abstract: An integrated circuit provides for adjustable slew rate control for both rising and falling edges of an output provided to an SCSI bus. Slew rate is controlled by adaptively varying the charge and/or discharge rate of the gate electrode of an output driver's N-channel pull-down transistor. Charge time and, thus, the falling edge slew rate, is adaptively varied by selectively adding the current source P-channel transistors to a current bus coupled to the gate electrode of the pull-down transistor. Similarly, the discharge rate and, thus, the rising edge slew rate, is adaptively adjusted by selectively switching current sink transistors on to the current bus coupled to the pull-down transistor's gate electrode. The amount of currents sourced or sunk is determined by varying the W/L ratios of both the current source and current sink transistors.

Abstract: The present invention is a battery backed output buffer which provides a well-defined signal, even during battery power. The buffer includes a regular output buffer for providing output data during operation with a main power supply and for switching to a tri-state during battery power. The buffer also includes a configurable battery backed output buffer which provides a predetermined output signal during battery operation and produces a signal in the tri-stated during main power operation.

Abstract: A logic circuit comprises an output line, a first switch having an end connected to the output line and another end connected to a power source potential, a second switch having an end connected to the output line and another end connected to a ground potential, and a switching/rectifying circuit, which has an end connected to the output line and another end connected to an intermediate power source potential, for switching/rectifying, in which said intermediate power source potential is higher than the ground potential and lower than the power source potential. With this configuration, said switching/rectifying circuit includes a third switch and a rectifier connected in series.

Abstract: An active pull-down emitter coupled logic circuit includes a high voltage line, a low voltage line, a first constant current circuit coupled to the low voltage line, first and second main current paths extending between the high voltage line and the first constant current circuit, and first and second subordinate current paths extending between the high voltage line and the first constant current circuit. The subordinate current paths are paired with their respective ones of the main current paths.

Abstract: In a driver circuit for a twisted pair cable, a compensator for preventing appreciable common mode current flow into or out of the twisted pair cable in response to the device receiving a wide range of common mode voltage bias levels. A wide range of external bias voltages may be received as a result of variations in the ground node voltages of two coupled devices. The compensator circuit utilizes a feed back loop and monitors the bias voltage received on the twisted pair cable. As the magnitude of the common mode current increases due to external bias voltage variation from a reference bias voltage, the current flow of p-channel transistors, coupled in an arrangement of the present invention, is increased (or decreased, as necessary) so that reduced common mode current flows onto the twisted pair cable. The present invention reduces appreciable common mode current flow through the twisted pair cable from the driver that are due to variations in the external bias voltage between communication devices.

Abstract: An output buffer circuit with edge-rate control capable of maintaining both rising and falling edge-rates within narrow specifications in the face of wide variations in load impedance. In particular, the output buffer of the present invention is intended for coupling to a common bus whereby it may be presented with very low resistive impedance loads and varying capacitive loads. The control schemes for both the pull-up and the pull-down parts of the circuit of the present invention utilize in part fixed currents charging a selected capacitance in order to achieve a metering of the charging or discharging current at the buffer's output. For the pull-down part of the circuit a dual MOS/Bipolar pull-down scheme is used, with the MOS transistors sequentially turning on in a gradual fashion so as to smooth the onset of current sinking. Subsequently, after a measured delay, a bipolar pull-down transistor is turned on.

Abstract: An output buffer circuit is provided which significantly reduces ground/Vcc bounce and glitches of signals provided to an integrated circuit. The circuit includes a plurality of transistors for providing a drive potential at the output of the device. The transistors are coupled such that they increase in size from the input to the output of the output buffer circuit. A control circuit provides control signals for sequentially turning off the transistors from the largest to smallest device thereby substantially reducing the Vcc bounce and glitches of the signals provided to the integrated circuit by the output buffer circuit.

Abstract: A DC-coupled active pull-down ECL circuit ("LS-APD") has a pull-down drive that self-adjusts to load conditions. A current source sinks emitter current from first and second push-pull transistors. The input signal is coupled to the base of the first transistor, whose inverted collector signal is coupled to the base of a pull-up transistor whose emitter is the LS-APD output voltage node. (A non-inverting configuration provides the input signal to the base of the second transistor.) The pull-up transistor is coupled between the upper rail and the second transistor's collector load resistor. A pull-down transistor has its base coupled to the second transistor's collector, its collector coupled to the LS-APD output node, and its emitter coupled to a node receiving a regulated Vreg voltage. As load capacitance increases, the output voltage takes longer to drop sufficiently to nearly turn-off the pull-down transistor.