With Capacitive Or Inductive Bootstrapping Patents (Class 326/92)
-
Patent number: 8493092Abstract: A linear equalizer (LEQ) includes a first transconductance device coupled to an input node of the LEQ and a second transconductance device AC coupled to the input node of the LEQ to increase a gain of the LEQ for data signals above a predetermined frequency. The first transconductance device and the second transconductance device are of complimentary types. A bimodal LEQ includes inputs to control operation of the bimodal LEQ in a current mode or a voltage mode. The bimodal LEQ includes first and second transconductance devices. One of the first and second transconductance devices is AC coupled to an input node to increase the gain for data signals above a predetermined frequency.Type: GrantFiled: April 18, 2012Date of Patent: July 23, 2013Assignee: Rambus, Inc.Inventors: Omid Rajaee, Ting Wu, Kambiz Kaviani, Jason Chia-Jen Wei
-
Patent number: 8310281Abstract: In accordance with an embodiment, a method of driving switches includes sensing a control node of a first switch, sensing a control node of a second switch, and driving the control node of the first switch to a first active state after the control node of the second switch transitions to a second active state. The method also includes driving the control node of the second switch to a second inactive state after the control node of the first switch transitions to a first inactive state. Driving the control node of the first switch is based on sensing the control node of the second switch, and driving the control node of the second switch is based on based on sensing the control node of the first switch.Type: GrantFiled: November 30, 2010Date of Patent: November 13, 2012Assignee: Infineon Technologies AGInventor: Dieter Draxelmayr
-
Patent number: 8269708Abstract: In a driver unit for driving a display panel and a nonvolatile memory, a level shifter circuit receives a driver control signal to generate a level-shifted driver control signal. A display panel driver circuit drives the display panel in accordance with the level-shifted driver control signal. A nonvolatile memory driver circuit drives the nonvolatile memory in accordance with the level-shifted driver control circuit. A selection circuit selects one of the display panel driver circuit and the nonvolatile memory driver circuit.Type: GrantFiled: June 27, 2006Date of Patent: September 18, 2012Assignee: Renesas Electronics CorporationInventor: Takashi Tahata
-
Patent number: 8198918Abstract: An integrated circuit (IC) includes a functional circuit and a capacitor cell. The functional circuit may operate with one of two power supply voltages. The capacitor cell is used to provide power supply decoupling for the functional circuit, and includes multiple capacitors, each designed to withstand a maximum voltage equal to the lower of the two power supply voltages. When the functional circuit is to operate with the higher of the two power supply voltages, the capacitors in the capacitor cell are coupled in a series arrangement between power supply and ground terminals of the IC. When the functional circuit is to operate with the lower of the two power supply voltages, the capacitors in the capacitor cell are coupled in a parallel arrangement between the power supply and ground terminals. In an embodiment, the functional circuit is an input-output (I/O) circuit powered by 1.8V or 3.3V power supplies.Type: GrantFiled: December 28, 2010Date of Patent: June 12, 2012Assignee: Texas Instruments IncorporatedInventor: Karthik Rajagopal
-
Patent number: 7893733Abstract: A voltage driver circuit includes a first transistor. The first transistor includes a control terminal, a first terminal, and a second terminal. The second transistor includes a control terminal, a first terminal, and a second terminal. A first current source configured to provide a first bias current to the control terminal of the first transistor. A second current source configured to provide a second bias current to the control terminal of the second transistor. The first resistance includes a first terminal connected to the control terminal of the first transistor. The second resistance includes a first terminal connected to the control terminal of the second transistor. A capacitance connects the second terminal of the first transistor with the control terminal of the second transistor. A ratio of the first bias current to the second bias current is approximately equal to a ratio of the second resistance to the first resistance.Type: GrantFiled: July 14, 2009Date of Patent: February 22, 2011Assignee: Marvell International Ltd.Inventor: Kien Beng Tan
-
Patent number: 7818704Abstract: The present invention is directed to a capacitive decoupling module and method for an integrated circuit that features providing multiple capacitive elements to decouple the power rails from the integrated circuit. The multiple capacitive elements are spaced-apart, along a first direction, from the integrated circuit. A first set of capacitive elements is closer to the integrated circuit than a second set of capacitive elements. The first set has a smaller capacitance than the second set.Type: GrantFiled: May 16, 2007Date of Patent: October 19, 2010Assignee: Altera CorporationInventors: Andrew E. Oishei, Gregory Moore
-
Patent number: 7688115Abstract: A CMOS output driver is provided for driving a capacitive load over a circuit trace in high speed applications. The CMOS output driver comprises a signal input and a signal output. The output driver has a first buffer amplifier with an input connected to the signal input and an output connected to the signal output through a resistor. A second buffer amplifier is also provided, which has an input connected to the signal input and an output connected to the signal output through a capacitor.Type: GrantFiled: September 4, 2007Date of Patent: March 30, 2010Assignee: Texas Instruments Deutschland GmbHInventor: Horst Jungert
-
Patent number: 7679402Abstract: A circuit incorporating a current starved ring oscillator is coupled to a power gate switch in an integrated circuit. The circuit incorporating the current starved ring oscillator amplifies a voltage difference between a virtual ground associated with the power gate switch and ground, and converts the difference to a frequency. Digital logic monitors the output of the ring oscillator using a counter and a reference clock. Control circuitry controls operation of the integrated circuit in dependence on the monitored conditions associated with the power gate switch. A method monitors a virtual ground voltage across a power gate switch in an integrated circuit; and controls operation of the integrated circuit in dependence on the monitored virtual ground voltage.Type: GrantFiled: April 3, 2008Date of Patent: March 16, 2010Assignee: International Business Machines CorporationInventors: J. Adam Butts, Gary S. Ditlow, Stephen V. Kosonocky, Brian C. Monwai
-
Patent number: 7646220Abstract: A rail-to-rail high speed subLVDS receiver demonstrates good jitter and duty cycle performance for high-speed signals at low power supply levels. A sample receiver includes a voltage shifter for shifting the voltage levels of a differential input signal so that a shifted differential input signal is produced. The shifted differential input signal can be applied to a first differential pair, and the differential input signal can be applied to a second differential pair. The outputs of the first and second differential pairs can be summed together to produce a differential output signal. The differential output signal can be output using an output block. A clamp circuit can be used to adjust the gain of the first differential pair responsive to a common mode voltage of the first and second differential input signals.Type: GrantFiled: September 27, 2007Date of Patent: January 12, 2010Assignee: OmniVision Technologies, Inc.Inventor: Charles Qingle Wu
-
Patent number: 7592831Abstract: A circuit for optimizing charging of a bootstrap capacitor connected to a high side floating supply voltage at a first terminal and to a switched node voltage at a second terminal, the circuit for optimizing being included in a gate driver circuit having high- and low-side driver circuits for driving high- and low-side switches connected at the switched node in a half bridge to provide current to a load, the high-side driver circuit receiving a first control voltage referenced to a first level and the low-side driver circuit receiving a second control voltage referenced to a second level, the bootstrap capacitor providing the high-side floating supply voltage for the high-side driver circuit, the optimizing circuit comprising a bootstrap diode emulator circuit comprising a bootstrap diode emulator driver circuit driving a first switch, the first switch connected between the first terminal of the bootstrap capacitor and a supply voltage for the low side driver circuit; and a phase sense comparator circuit respType: GrantFiled: May 20, 2008Date of Patent: September 22, 2009Assignee: International Rectifier CorporationInventors: Christian Locatelli, Marco Giandalia
-
Patent number: 7560961Abstract: A voltage driver circuit comprises a first transistor having a control terminal and first and second terminals. A second transistor has a control terminal and first and second terminals and generates a drive voltage at the second terminal thereof. First and second current sources bias the control terminals of the first and second transistors with first and second variable current signals, respectively. A capacitance couples the second terminal of the first transistor with the control terminal of the second transistor.Type: GrantFiled: August 11, 2006Date of Patent: July 14, 2009Assignee: Marvell International Ltd.Inventor: Kien Beng Tan
-
Patent number: 7518407Abstract: A bootstrap circuit includes an output transistor, a bootstrap capacitor provided between the gate and source of the output transistor, a power source, and a circuit that performs ON/OFF control of a supply from the power source to the gate electrode of the transistor. An initial voltage before a bootstrap effect can be set to the potential of the power source, which is independent of the threshold voltage of the transistor. Therefore, the source output of the transistor rising or dropping due to the bootstrap effect is not affected by variations that depend on the threshold voltage of the transistor.Type: GrantFiled: November 16, 2005Date of Patent: April 14, 2009Assignee: NEC CorporationInventor: Yoshihiro Nonaka
-
Patent number: 7474117Abstract: A method of transmitting a signal on a bi-directional universal serial bus (“USB”) circuit for boosting a signal on a USB bus disclosed. The circuit includes a first stage inverting buffer coupled to a second stage inverting buffer to form a non-inverting buffer circuit. A high pass filter is coupled in series with the non-inverting buffer circuit to provide AC coupling to the USB bus and to allow fast signal edges through the circuit. The booster circuit is arranged to improve signal quality over a USB bus to allow additional USB devices and longer USB busses to be utilized.Type: GrantFiled: May 27, 2008Date of Patent: January 6, 2009Assignee: International Business Machines CorporationInventors: Justin P. Bandholz, Moises Cases, Bradley D. Herman, Erdem Matoglu, Bhyrav M. Mutnury, Thomas D. Pahel, Pravin S. Patel, Nam H. Pham, Christopher C. West
-
Patent number: 7456658Abstract: A circuit for optimizing charging of a bootstrap capacitor connected to a high side floating supply voltage at a first terminal and to a switched node voltage at a second terminal, the circuit for optimizing being included in a gate driver circuit having a high-and a low-side driver circuits for driving high- and low-side switches connected at a switched node in a half bridge to provide current to a load, the high-side driver circuit receiving a first control voltage referenced to a first level and a low-side driver circuit receiving a second control voltage referenced to a second level, the bootstrap capacitor providing supply voltage for the high-side driver circuit.Type: GrantFiled: April 5, 2007Date of Patent: November 25, 2008Assignee: International Rectifier CorporationInventors: Christian Locatelli, Andrea Francesco Merello
-
Patent number: 7446568Abstract: An integrated circuit includes a current mirror circuit for providing a current at an output end, a power-down switch coupled to the output end of the current mirror circuit for controlling access of the current generated by the current mirror circuit based on signals received at a control end of the power-down switch, and a compensating unit coupled to a bias end of the current mirror circuit and the power-down switch for stabilizing voltages at the bias end of the current mirror circuit.Type: GrantFiled: May 29, 2006Date of Patent: November 4, 2008Assignee: Himax Technologies LimitedInventors: Chin-Tien Chang, Chien-Ru Chen, Ying-Lieh Chen
-
Patent number: 7405595Abstract: A high-side transistor driver including a driver circuit for generating a driving signal to drive a high-side transistor is provided. A floating supply terminal provides a supply voltage to the driver circuit. A floating ground terminal is connected to a source of the high-side transistor. A bootstrap diode is coupled between the floating supply terminal and a voltage source. A capacitor is connected to the bootstrap diode and is coupled between the floating supply terminal and the floating ground terminal. A high-voltage transistor is used for switching off the driving signal and the high-side transistor in response to an input signal. A speed-up capacitor is coupled to the driver circuit for speeding up the driving signal. Furthermore, the positive feedback circuits in the driver circuit further accelerate the driving signal and save power for the driver circuit.Type: GrantFiled: November 16, 2005Date of Patent: July 29, 2008Assignee: System General Corp.Inventors: Ta-yung Yang, Chuh-Ching Li, Yu-Min Chen
-
Patent number: 7397284Abstract: A bootstrapping circuit capable of sampling input signals beyond a supply voltage is disclosed. In one embodiment, the bootstrapped circuit is implemented having a reduced area and/or power consumption requirement.Type: GrantFiled: April 3, 2007Date of Patent: July 8, 2008Assignee: XILINX, Inc.Inventor: Peng Liu
-
Patent number: 7394281Abstract: A bi-directional universal serial bus (“USB”) circuit for boosting a signal on a USB bus disclosed. The circuit includes a first stage inverting buffer coupled to a second stage inverting buffer to form a non-inverting buffer circuit. A high pass filter is coupled in series with the non-inverting buffer circuit to provide AC coupling to the USB bus and to allow fast signal edges through the circuit. The booster circuit is arranged to improve signal quality over a USB bus to allow additional USB devices and longer USB busses to be utilized.Type: GrantFiled: January 31, 2008Date of Patent: July 1, 2008Assignee: International Business Machines CorporationInventors: Justin P. Bandholz, Moises Cases, Bradley D. Herman, Erdem Matoglu, Bhyrav M. Mutnury, Thomas D. Pahel, Pravin S. Patel, Nam H. Pham, Christopher C. West
-
Patent number: 7362146Abstract: A differential transmission line driver with supplemental current sources that overcome switching anomalies and EMU issues when the logic state of the driver is switching. During a logic transition, a current source, that is directed to the output of the driver, may be prevented from delivering its current. The present invention provides a supplemental current that is active during this transition period to supply the missing current. The present disclosure also details a common mode circuit that maintains a stable common mode output level to help control EMI issues when the power supply for the driver changes.Type: GrantFiled: July 25, 2005Date of Patent: April 22, 2008Inventor: Steven Mark Macaluso
-
Patent number: 7282956Abstract: A high-voltage switching circuit comprises: a high-voltage switch configured to transfer a high voltage; a pumping circuit configured to boost signals of first, second, and third nodes by conducting pumping operations in response to a plurality of clock signals; and a drive signal transmission circuit configured to boost the signal of the second node at a constant rate while maintaining a voltage level of the third node regardless of variation of a voltage level at the first node and transfer the boosted signal of the second node to the high-voltage switch, activating the high-voltage switch.Type: GrantFiled: December 9, 2005Date of Patent: October 16, 2007Assignee: Hynix Semiconductor Inc.Inventor: Seok Joo Lee
-
Patent number: 7274223Abstract: As devices are often different in the characteristics from one another, semiconductor chips based on the devices have discrepancies in the performance. A semiconductor device having a semiconductor switching element and a drive controlling means (1) for generating from input signals (A) and (B) drive signals (a) and (b) to control the action of the semiconductor switching element is provided comprising a characteristic compensating means (2) for generating from a characteristic compensation input signal a compensation signal to eliminate variations in the transmission delay time of the drive controlling means (1).Type: GrantFiled: April 17, 2003Date of Patent: September 25, 2007Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Hiroshi Sakata, Toru Araki
-
Patent number: 7271619Abstract: Operation noise and charge error of a charge pump circuit are reduced, thereby the jitter characteristics and the spectrum characteristics of a PLL circuit are improved, and further a time period elapsed until the PLL circuit is locked is shortened. The charge pump circuit 36 receives a control signal depending on an output of a phase comparison circuit 34 from a control circuit 35, and comprises a first P-channel MOS transistor P1, a second P-channel MOS transistor P2 and a third P-channel MOS transistor P3, and a first N-channel MOS transistor N1, a second N-channel MOS transistor N2 and a third N-channel MOS transistor N3, and a first current source 61, a second current source 62, a third current source 63 and a fourth current source 64.Type: GrantFiled: April 18, 2005Date of Patent: September 18, 2007Assignee: Seiko NPC CorporationInventors: Hiroshi Kawago, Haruhiko Otsuka
-
Patent number: 7127597Abstract: A system and method for controlling boot options for a workstation on a computer network includes initiating a boot on a workstation in communication with the network, downloading an application to the workstation from a server in communication with the network, gathering information about the workstation using the bootstrap code and forwarding the information to a policy server in communication with the network. The system and method also include determining, by the policy server, based on the forwarded information and based on a boot policy stored in a policy directory of the network, at least one boot option for booting the workstation, forwarding the boot option to the workstation, requesting, by the workstation, a boot image corresponding to the boot option, forwarding of the boot image to the workstation and completing the boot of the workstation based upon the boot option received by the workstation.Type: GrantFiled: September 24, 2002Date of Patent: October 24, 2006Assignee: Novell, Inc.Inventors: Drake Backman, Matthew Lewis, Stephen Washburn
-
Patent number: 7106105Abstract: A high voltage circuit driver includes high and low side driver cells to drive a high and a low side power MOSFET, a bootstrap circuit to energize the high side driver cell, a high voltage PMOS transistor (HVPMOS) between a voltage source and the bootstrap circuit, wherein the HVPMOS is embedded in an N-isolation layer and is integrated with the driver cells. A bootstrap control circuit, for controlling the HVPMOS, includes a high voltage level shift stage, which can also be embedded in an N-isolation layer. The circuit driver is operated by switching the high side drive signal from high to low, the low side drive signal from low to high with a first delay, and a bootstrap control signal from high to low with an additional second delay. Also, the bootstrap capacitor is first charged by switching on the HVPMOS, and then it energizes the high side driver cell.Type: GrantFiled: July 21, 2004Date of Patent: September 12, 2006Assignee: Fairchild Semiconductor CorporationInventor: Stephen W. Bryson
-
Patent number: 7046040Abstract: A bootstrap driver comprises an output stage having an N-type high-side transistor and a low-side transistor, also of the N-type, which are arranged in series between a positive supply terminal and a negative supply terminal. A control circuit of the high-side transistor and a control circuit of the low-side transistor are respectively supplied by a first voltage regulator and a second voltage regulator, which are mutually independent. A recovery diode is connected by its anode to the output of the first voltage regulator and by its cathode to the positive supply terminal, in order to conduct the reverse current of a bootstrap diode when the output of the circuit switches from a low state to a high state.Type: GrantFiled: July 29, 2004Date of Patent: May 16, 2006Assignee: STMicroelectronics S.A.Inventor: Yannick Guedon
-
Patent number: 6977528Abstract: Methods and circuits are described for reducing power consumption within digital logic circuits by blocking the passage of clock signal transitions to the logic circuits when the clock signal would not produce a desired change of state within the logic circuit, such as at inputs, intermediary nodes, outputs, or combinations. By way of example, the incoming clock is blocked if a given set of logic inputs will not result in an output change of state if a clock signal transition were to be received. By way of further example, the incoming clock is blocked in a data flip-flop if the input signal matches the output signal, such that receipt of a clock transition would not produce a desired change of state in the latched output. The invention may be utilized for creating lower power combinatorial and/or sequential logic circuit stages subject to less unproductive charging and discharging of gate capacitances.Type: GrantFiled: December 20, 2002Date of Patent: December 20, 2005Assignee: The Regents of the University of CaliforniaInventors: Sung-Mo Kang, Seung-Moon Yoo
-
Patent number: 6774667Abstract: A programmable gate array comprising: a plurality of logic modules, each logic module having at least one output coupled to an isolation transistor, each isolation transistor in each of the plurality of logic modules having a gate; and a charge pump having a pump-voltage output line coupled to the gates of each isolation transistor in each of the plurality of logic modules. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims, 37 CFR 1.72(b).Type: GrantFiled: May 9, 2002Date of Patent: August 10, 2004Assignee: Actel CorporationInventor: Richard Chan
-
Patent number: 6710626Abstract: For a minimal electromagnetic radiation during transition between its states, a transmitter for a two-wire, differential databus on which a dominant state can be impressed by means of the transmitter in an active state of the transmitter, and which is in a recessive state when all transmitters connected to the databus are in a passive state, is characterized in that the transmitter is provided with a capacitance (6) and switching means (7, 8, 9, 10) by means of which the capacitance (6) can be alternatively coupled to an electric source (11) or between the two databus lines (1, 2), and in that the switching means (7, 8, 9, 10) charge the capacitance (6) by means of the electric source (11) during periods when the transmitter is in a passive state, and couple the capacitance (6) between the two databus lines (1, 2) during periods when the transmitter is in an active state.Type: GrantFiled: June 29, 2000Date of Patent: March 23, 2004Assignee: Koninklijke Philips Electronics N.V.Inventor: Peter Bühring
-
Patent number: 6577162Abstract: A step-up circuit is equipped with a plurality of serially connected rectification elements Q1, Q2, . . . between a first node and a second node, a plurality of capacitors C1, C2, . . . connected to connection points of the plurality of rectification elements, respectively, and an oscillation loop that is formed by circularly and serially connecting an odd number of inversion devices NAND, INV1, INV2, . . . , each inverting an input signal and outputting the same, and supplies an alternating current signal having a specified phase to the plurality of capacitors.Type: GrantFiled: September 6, 2001Date of Patent: June 10, 2003Assignee: Seiko Epson CorporationInventor: Tetsuo Takagi
-
Patent number: 6300797Abstract: A semiconductor device capable of preventing malfunctions of instantaneous lighting, and comprises a drive circuit, a drive control circuit, and a power supply circuit. The power supply circuit has a boosting circuit which is provided with a first power supply potential VDD being a ground potential from an external power supply and a second power supply potential VSS, being a potential other than the ground potential, and raises the absolute value of the second power supply potential VSS and charges to the capacitor; and a bias generating circuit generating a potential to be supplied to the drive circuit and drive control circuit based on the output potential of the boosting circuit.Type: GrantFiled: March 27, 2000Date of Patent: October 9, 2001Assignee: Seiko Epson CorporationInventor: Norio Koizumi
-
Patent number: 6246296Abstract: A pulse width modulation (PWM) amplifier of the type including power transistors connected in totem-pole fashion and a bootstrap capacitor used to bias at least one of the power transistors into the conductive state. The improvement wherein the bootstrap capacitor is refreshed only to the extent needed to provide a higher effective maximum duty cycle.Type: GrantFiled: July 6, 1998Date of Patent: June 12, 2001Assignee: Kollmorgen CorporationInventor: Robert C. Smith
-
Patent number: 6172528Abstract: A deskew circuit for synchronizing output signals from a fanout buffer. The circuit includes one capacitive element coupled to each of the buffer's output nodes. Each capacitive element is also coupled to a common floating bus. The capacitive element is preferably a capacitor and the common floating bus is electrically isolated from any power rails. The bus may be formed of polysilicon or metal.Type: GrantFiled: January 20, 1999Date of Patent: January 9, 2001Assignee: Fairchild Semiconductor CorporationInventor: Louis J. Malarsie
-
Patent number: 6154063Abstract: Buffers having an output pull-up transistor controlled by the input signal, an output pull-down transistor and a pull-down transistor control circuit. A current source provides a current that is divided between the pull-up transistor and the pull-down transistor control circuit to maintain the desired output voltage. A boost capacitor is coupled between the output and the pull-down transistor control circuit to provide good dynamic response to the circuit even in the presence of substantial capacitive loads on the output. In addition a second capacitor is coupled between the pull-down transistor control circuit and a fixed voltage to provide a low frequency pole internal to the circuit. The connection of the boost capacitor to the pull-down transistor control circuit and the connection of the second capacitor to the pull-down transistor control circuit are separated by a substantial resistance, allowing the effect of each capacitor to be substantially independent of each other.Type: GrantFiled: April 26, 1999Date of Patent: November 28, 2000Assignee: Maxim Integrated Products, Inc.Inventors: Gary G. Fang, David Castaneda, Chowdhury F. Rahim
-
Patent number: 6097220Abstract: Briefly, in accordance with one embodiment of the invention, an integrated circuit includes: two transistors coupled together in the integrated circuit so that upon the application of complementary voltage signals, electrical charge is substantially evenly distributed between output nodes. Briefly, in accordance with one more embodiment of the invention, an integrated circuit includes: a charge recycle circuit including two transistors. Briefly, in accordance with another embodiment of the invention, an integrated circuit includes: a charge recycle circuit including a first and second transistor coupled so as to respectively receive complementary voltage signals at the control voltage port of the first and second transistors. The transistors have a threshold voltage level different from the threshold voltage level of other transistors coupled to the charge recycle circuit.Type: GrantFiled: June 11, 1997Date of Patent: August 1, 2000Assignee: Intel CorporationInventor: Sampson X. Huang
-
Patent number: 6002269Abstract: A bootstrap logic driver circuit operable from a low voltage power supply includes first and second bipolar transistors coupled between positive and negative voltage supplies and having a collector load comprising a first diode structure. A further transistor coupled between the voltage supplies has a collector load comprising a second diode structure. A bootstrap capacitor coupled between the diode structures stores charge when the circuit is in a first condition and is discharged when the circuit is in a second condition to provide an enhanced drive voltage for an output transistor.Type: GrantFiled: December 23, 1997Date of Patent: December 14, 1999Assignee: Northern Telecom LimitedInventors: Peter Dartnell, Joseph Chan
-
Patent number: 5945845Abstract: A voltage elevation circuit supplying additional voltage for gate switching having an elevated power supply connected to a first node of a capacitor using a transistor. The elevated power supply and booting circuit providing additional voltage for gate switching applications. One application is a MOSFET output driver application having a 3 Volt power supply. One configuration using a switch to charge a capacitor using a first voltage supply and then providing additional voltage by a boot device and by switching in an elevated power supply to maintain an elevated voltage at the node.Type: GrantFiled: July 9, 1998Date of Patent: August 31, 1999Assignee: Micron Technology, Inc.Inventors: Mark R. Thomann, Paul M. Fuller
-
Patent number: 5811991Abstract: A logic circuit comprises an output line, a first switch having an end connected to the output line and another end connected to a power source potential, a second switch having an end connected to the output line and another end connected to a ground potential, and a switching/rectifying circuit, which has an end connected to the output line and another end connected to an intermediate power source potential, for switching/rectifying, in which said intermediate power source potential is higher than the ground potential and lower than the power source potential. With this configuration, said switching/rectifying circuit includes a third switch and a rectifier connected in series.Type: GrantFiled: March 8, 1996Date of Patent: September 22, 1998Assignee: Kabushiki Kaisha ToshibaInventor: Daisaburo Takashima
-
Patent number: 5783948Abstract: A voltage elevation circuit supplying additional voltage for gate switching having an elevated power supply connected to a first node of a capacitor using a transistor. The elevated power supply and booting circuit providing additional voltage for gate switching applications. One application is a MOSFET output driver application having a 3 Volt power supply. One configuration using a switch to charge a capacitor using a first voltage supply and then providing additional voltage by a boot device and by switching in an elevated power supply to maintain an elevated voltage at the node.Type: GrantFiled: October 7, 1996Date of Patent: July 21, 1998Assignee: Micron Technology, Inc.Inventors: Mark R. Thomann, Paul M. Fuller
-
Patent number: 5574390Abstract: A voltage elevation circuit supplying additional voltage for gate switching having an elevated power supply connected to a first node of a capacitor using a transistor. The elevated power supply and booting circuit providing additional voltage for gate switching applications. One application is a MOSFET output driver application having a 3 Volt power supply where noise margin demands elevated switching voltages. One configuration using a long channel transistor to limit current sourced by the elevated power supply. An alternate configuration using a switched elevated power supply to minimize loading on the elevated power supply.Type: GrantFiled: June 23, 1995Date of Patent: November 12, 1996Assignee: Micron Technology, Inc.Inventor: Mark R. Thomann
-
Patent number: 5399928Abstract: A circuit is provided for supplying a negative high voltage to an integrated circuit from a high positive voltage source V.sub.PP. The negative voltage is applied to a plurality of FLASH electrically erasable programmable read only memory (EPROM) cells. The circuit includes an oscillator coupled to a voltage converter which provides a periodic signal. The periodic signal is coupled to a charge pump including three P-channel type transistors to produce the negative voltage. The source and drain of the first transistor is coupled to the periodic signal. The second transistor's gate and drain is coupled to a reference ground potential with the source coupled to the first transistor's gate. Finally, the third transistor's drain and gate is coupled to the first transistor's gate and the third transistor's source outputs negative voltage to floating gates of the plurality of FLASH EPROM cells during an erase operation. Further, the negative voltage generated is relatively precise, so no regulation is required.Type: GrantFiled: August 31, 1993Date of Patent: March 21, 1995Assignee: Macronix International Co., Ltd.Inventors: Tien-Ler Lin, Liang Chao