Abstract: Methods and apparatus for tracking delay in signals sent from a first clock domain to a second clock domain are disclosed. For example, at a first time a common timing reference signal (SysRef) may be received at the first clock domain, and a latency marker may be input into a first-in first-out data structure (FIFO) coupling the first clock domain to the second clock domain. At a second time, the SysRef may be received at the second clock domain, and a timer may be started at the second clock domain. At a third time, the latency marker may be received from the FIFO at the second clock domain, and the counter may be stopped at a final count. A FIFO latency may be determined based on the final count and on a difference between the second time and the first time.

Abstract: A phase predictor to accurately detect and predict the phase relationship between two clocks running at different frequencies. The phase relationship can be used to record the transmission and reception times of Ethernet frames transmitted over a transmission medium with very high accuracy.

Abstract: The disclosure relates to a logic circuit. The logic circuit comprises a first thin film transistor, TFT, having a gate connected to an input of the logic circuit, and a drain connected to an output of the logic circuit. The logic circuit further comprises a second TFT having a source connected to the output of the logic circuit. The logic circuit further comprises a third TFT having a gate connected to the input of the logic circuit, a source connected to the source of the second TFT, and a drain connected to a gate of the second TFT. The logic circuit further comprises a fourth TFT having a gate connected to the output of the logic circuit, and a source connected to the gate of the second TFT and the drain of the third TFT.

Abstract: Novel unipolar circuits and vertical structures are described which exhibit low stand-by power, low dynamic power, high speed performance, and have higher density compared to conventional silicon CMOS circuitry. In one embodiment, a design methodology utilizing either a p-channel or n-channel transistor type such that each logic gate is clocked and the clocking mechanism provides the pull up or pull down. Further embodiments include novel designs of vertical unipolar logic gates which provides for high density. Ultra-short transistor channel lengths in vertical unipolar logic gates are fabricated with a deposition process—in lieu of a lithography process—thereby providing for high speed operation and low cost manufacturing.

Abstract: A communication device includes a transmitter, a receiver, a clock signal line, a data signal line, a memory and a controller. The controller is configured to control the transmitter to transmit the clock signal and the confirmation signal where at least one of the clock signal and the confirmation signal are transmitted at a reference waveform condition and determine whether the transmitter receives an acquisition signal. The controller is configured to, if the transmitter does not receive the acquisition signal, control the transmitter to transmit the clock signal and the confirmation signal using a different waveform condition for at least one of the clock signal and the confirmation signal and if the transmitter receives the acquisition signal, update condition change information.

Abstract: Embodiments of the present invention provide a packet processing method and apparatus. After receiving a packet, a first network device processes the packet, and determines a first latency of the processed packet in a FIFO memory, where: the first latency is equal to a difference obtained by subtracting a second latency from a target latency, the second latency includes a third latency, and the third latency includes a time interval for processing the packet.

Abstract: A method and circuit for implementing a hidden security key in Electronic Fuses (eFuses), and a design structure on which the subject circuit resides are provided. The circuit includes a race condition circuit coupled to a latching structure. The race condition circuit is characterized including respective driver strengths of each stage in the race as well as a sampling clock during chip testing. The data is used to store drive strengths for each stage in eFuses and is used to get a logical one or logical zero out of the final latching stage of the race condition circuit.

Abstract: An apparatus includes a latch of a clock gating circuit (CGC). The latch is configured to generate a first signal in response to a clock signal. The apparatus further includes a delay circuit of the CGC. The delay circuit is configured to receive the clock signal and to generate a second signal based on the clock signal and the first signal. The apparatus further includes an output circuit of the CGC. The output circuit is coupled to the delay circuit and to the latch. The output circuit is configured to generate a master clock signal based on the clock signal and the second signal. An edge of the master clock signal is delayed with respect to an edge of the clock signal based on a delay characteristic associated with a slave clock signal.

Abstract: A controller for controlling the illumination state of a light source of solid state lighting devices such as LED or OLED assemblies, is presented. The controller controls the light source according to a plurality of illumination states subject to determine an event of a plurality of events. The controller controls a power converter that converts power derived from an input voltage waveform of line voltage power supply into a drive signal for the light source. The controller determines an event of a plurality of events encoded within the input voltage waveform of the line voltage power supply. A first state processor determines a next illumination state of the plurality of illumination states, based on the determined event and based on the current illumination state. Line voltage Switch event detection is performed while no power is available at the line voltage terminals.

Abstract: A method for increasing performance in a limited switch dynamic logic (LSDL) circuit includes precharging a dynamic node during a precharge phase of a first and second evaluation clock signal. The dynamic node is evaluated to a first logic value in response to one or more first input signals of a first evaluation tree during an evaluation phase of the first evaluation clock signal. The dynamic node is evaluated to a second logic value in response one or more second input signals of a second evaluation tree during an evaluation phase of the second evaluation clock signal. A signal of the LSDL circuit is outputted in response to the dynamic node according to an output latch clock signal.

Abstract: A limited switch dynamic logic (LSDL) circuit includes a dynamic logic circuit and a static logic circuit. The dynamic logic circuit includes a precharge device configured to precharge a dynamic node during a precharge phase of a first evaluation clock signal and a second evaluation clock signal. A first evaluation tree is configured to evaluate the dynamic node to a first logic value in response to one or more first input signals during an evaluation phase of the first evaluation clock signal. A second evaluation tree is configured to evaluate the dynamic node to a second logic value in response to one or more second input signals during an evaluation phase of the second evaluation clock signal. A static logic circuit is configured to provide an output of the LSDL circuit in response to the dynamic node according to an output latch clock signal.

Abstract: A nano-magnetic element array having a conductive line adjacent to a group of nano-magnetic elements and a multi-level current driver connected to an input node on the conductive line. The current driver is controlled by a pair of voltage clock signals and a voltage reference so as to selectively change the current amount at the input node between a first level that erases the state of the elements, a second level that switches the state of the elements and a third level that maintains the state of the elements. The current driver is further configured so that the transition from the second to the third level is gradual. Optionally, a bias generator can selectively adjust the voltage reference and thereby, the current amount at the input node. Also, optionally, the same voltage clock signal and voltage reference lines can be used to control multiple multi-level current drivers within the array.

Abstract: A synchronous clock multiplexer circuit detects the presence of an input clock signal whenever an input select signal changes state to select the input clock signal, and generates an output select signal, which is then used instead of the input select signal for selecting an input clock signal as an output clock signal. The output select signal stays in a logic high state to select a second input clock signal when the input select signal transitions from high to low to select a first input clock signal but the first input clock signal is not present. The output select signal stays in a logic low state to select the first input clock signal when the input select signal transitions from low to high to select the second input clock signal but the second input clock signal is not present.

Abstract: Systems and methods are provided for transferring a signal from a first clock domain to a second clock domain. A system includes a pulse generator configured to receive an input data signal in the first clock domain and to generate a pulse. The system further includes an unclocked flip-flop configured to generate a first output signal. The first output signal is received by a circuit operating in the second clock domain, and the first output signal has one of a first logical value and a second logical value. The unclocked flip-flop is configured to set the first output signal to the first logical value in response to the pulse. The unclocked flip-flop is configured to reset the first output signal to the second logical value in response to a clock signal in the second clock domain and a second output signal generated by the circuit.

Abstract: A multi-valued logic (MVL) circuit includes a MVL clock generator that generates a MVL clock signal having three or more ith MVL levels, a single MVL clock signal distribution network connected to the MVL clock generator, and three or more ith MVL selection circuits connected to the single MVL clock signal distribution network where i=0 to N and N>=3. Each ith MVL selection circuit corresponds to a specified ith MVL level. The ith MVL selection circuit outputs an ith binary clock signal having: (a) a first logic level whenever the MVL clock signal is equal to the ith MVL level and the ith data input receives the first logic level, (b) a second logic level whenever the MVL clock signal is equal to the ith MVL level and the ith data input receives the second logic level, and (c) a previous logic level of the ith binary clock signal whenever the MVL clock signal is not equal to the ith MVL level.

Abstract: A phase splitter includes: a first signal path; and a second signal path, wherein the phase splitter outputs an internal signal of the first signal path as a first phase signal, and mixes an output signal of the first signal path with an output signal of the second signal path, thereby outputting a second phase signal having a predetermined phase difference from the first phase signal.

Abstract: A domino logic circuit includes a plurality of domino logic stages connected in series between a latch and a flip-flop and a clock signal generator generating a clock signal having a first duty cycle and a flip-flop clock signal having a second duty cycle. The latch and the domino logic stages respectively operate in response to a domino clock signals derived from the first clock signal. The flip-flop operates in response to the flip-flop clock signal.

Abstract: Leakage current is reduced in a plurality of gates coupled between source storage elements and destination storage elements by waking the plurality of gates to allow current flow in response to assertion of any source clock enable signals that enable clocking of the source storage elements. The gates are slept to reduce leakage current in the plurality of gates, in response to assertion of a destination clock enable signal and all of the one or more source clock enable signals being deasserted, the destination clock enable signal enabling clocking of the destination storage elements.

Abstract: In one embodiment, a method includes generating a first signal based on a clock signal and generating a second signal based on a programmable delayed clock signal. The method then generates a reset signal based on the first signal and the second signal. The clock signal is delayed using an inverter chain to generate a delayed version of the clock signal. An output signal is generated based on the delayed version of the clock signal and the reset signal. When a pulse width of the output signal is greater than a data duration determined from the clock signal, the pulse width of the output signal is reset to the pulse width of the data duration.

Abstract: A method for increasing performance in a limited switch dynamic logic (LSDL) circuit includes precharging a dynamic node during a precharge phase of a first and second evaluation clock signal. The dynamic node is evaluated to a first logic value in response to one or more first input signals of a first evaluation tree during an evaluation phase of the first evaluation clock signal. The dynamic node is evaluated to a second logic value in response one or more second input signals of a second evaluation tree during an evaluation phase of the second evaluation clock signal. A signal of the LSDL circuit is outputted in response to the dynamic node according to an output latch clock signal.

Abstract: A FIFO device crossing a first and a second power domains is provided. The device comprises: a plurality of input registers belonging to the first power domain for receiving the input signal, and each of the input register having a first output; a first controller belonging to the first power domain for enabling the registers according to specific order and generating an initial signal; a multiplexer receiving the first outputs according to the specific order to generate a second output; a second controller belonging to second power domain, receiving the initial signal through an asynchronous interface and controlling the multiplexer to output second output; and an output register belonging to second power domain receiving the second output. First power domain operates according to a first clock signal. Second power domain operates according to a second clock signal. The first and second clock signals are asynchronous.

Abstract: In accordance with some embodiments, a method for high frequency clock distribution in a VLSI system includes splitting an original master clock signal into one or more pairs of lower-frequency sub-clocks for a destination in the VLSI system, distributing each lower-frequency sub-clock of the one or more pairs of lower-frequency sub-clocks to a corresponding channel coupled to the destination, and reconstructing a reference master clock signal at the destination from the one or more pairs of lower-frequency sub-clocks, wherein the reconstructed reference master clock signal replicates the original master clock signal.

Abstract: A circuit implementing multiplexer, storage, and repeater functions is disclosed. The circuit includes first and second input stages having first and second data inputs, respectively. An output stage is configured to drive an output signal. The first input stage is configured to activate the output stage responsive to a first condition, while the second input stage is configured to activate the output stage responsive to a second condition. An intermediate stage is configured to deactivate the output stage at a first delay time subsequent to one of the first or second input stages activating the output stage. The repeater circuit also includes a storage element configured to store a state of the output signal, and further configured to cause the output node to be held at the state of the output signal subsequent to deactivation of the output stage.

Abstract: A limited switch dynamic logic (LSDL) circuit includes a dynamic logic circuit and a static logic circuit. The dynamic logic circuit includes a precharge device configured to precharge a dynamic node during a precharge phase of a first evaluation clock signal and a second evaluation clock signal. A first evaluation tree is configured to evaluate the dynamic node to a first logic value in response to one or more first input signals during an evaluation phase of the first evaluation clock signal. A second evaluation tree is configured to evaluate the dynamic node to a second logic value in response to one or more second input signals during an evaluation phase of the second evaluation clock signal. A static logic circuit is configured to provide an output of the LSDL circuit in response to the dynamic node according to an output latch clock signal.

Abstract: A semiconductor integrated circuit includes: a plurality of chips configured to receive an external voltage. Each one of the chips detects a signal delay characteristic of the one of the chips to generate an internal voltage having a level corresponding to the signal delay characteristic.

Abstract: An image generating device for an optical, in particular medical tracking system, for determining the position of a recorded image point, includes a light scattering effect generating device, in particular a star and/or cross effect generating device. The invention further provides a tracking system including such an image generating device and to a method for determining the position of a recorded image point using an optical, in particular medical tracking system, in which: an image is generated using an image generating device; a light scattering effect, in particular a star and/or cross effect, is generated on the image for predetermined image points; and in which the position of an image point is ascertained on the basis of the light scattering pattern projected on the image, in particular on the basis of the star and/or cross effect lines and/or their intersection points.

Abstract: A semiconductor memory device using system clock with a high frequency can maintain a constant operation margin even in the change of operation environments including voltage level, temperature, and process. The semiconductor memory device includes an output control signal generator configured to be responsive to a read pulse that is activated in response to a read command, to generate an odd number of first output source signals corresponding to a rising edge of a system clock and a even number of second output source signals corresponding to a falling edge of the system clock, and an output enable signal generator configured to generate a first rising enable signal and a falling enable signal on the basis of the first output source signal and generate a second rising enable signal on the basis of the second output source signal, according to column address strobe (CAS) latencies, the first rising enable signal being activated earlier than the second rising enable signal by a half cycle of the system clock.

Abstract: A programmable logic circuit comprising a plurality of programmable logic elements and a plurality of programmable interconnect means, and memory means for storing the configuration of the logic elements and interconnect means, wherein said memory means is formed and arranged to store a multiplicity of different configurations for each said logic element.

Abstract: A system for protecting an input/output (I/O) pin of an integrated circuit device (IC) from single event transients is disclosed. The system includes a first delay circuit that is configured to delay a clock signal from the clock source by a first predetermined amount of time, and a second delay circuit that is configured to delay the clock signal by a second predetermined amount of time. The system further includes a first register that is clocked by the clock signal, a second register that is clocked by the clock signal delayed by the first predetermined amount of time, and a third register that is clocked by the clock signal delayed by the second predetermined amount of time. The system also includes voter circuits, where each voter circuit is configured to receive a first data signal from an output of the first register, a second data signal from an output of the second register, and a third data signal from an output of the third register.

Abstract: Circuits and methods are provided for estimating a latency through a FIFO buffer. A first detector detects first instances of a pattern in first data values serially written to a write port of the FIFO buffer. A second detector detects second instances of the pattern in second data values serially read from a read port of the FIFO buffer. The second data values are the first data values delayed by the latency through the FIFO buffer. A counter counts a count of active transitions of a sample clock signal. The counter starts on each detected first instance and stops on each detected second instances. The count provides an estimate of the latency of the FIFO buffer.

Abstract: A conversion circuit includes a first inverter having an input node configured to receive a single-ended signal and second and third inverters each having respective inputs coupled to an output of the first inverter. A fourth inverter has an input coupled to an output of the second inverter and has an output coupled to a first node. A fifth inverter has an input coupled to the first node and an output coupled to a second node to which an output of the third inverter is coupled. Sixth and seventh inverters are configured to respectively output a differential signal based on the single-ended signal. The sixth inverter has an input coupled to the first node, and the seventh inverter has an input coupled to the second node.

Abstract: An object of the present invention is to provide a driver circuit including a normally-on thin film transistor, which driver circuit ensures a small malfunction and highly reliable operation. The driver circuit includes a static shift register including an inverter circuit having a first transistor and a second transistor, and a switch including a third transistor. The first to third transistors each include a semiconductor layer of an oxide semiconductor and are depletion-mode transistors. An amplitude voltage of clock signals for driving the third transistor is higher than a power supply voltage for driving the inverter circuit.

Abstract: A device and method to compensate for distortions of amplitude that afflict systems for communicating through capacitive coupling. A circuit includes a first transmitter stage, a first receiver stage, and a first coupling capacitor, coupled between the first transmitter stage and the first receiver stage. The first receiver stage includes a calibration amplifier of a variable-gain type coupled between the first coupling capacitor and an output of the electronic circuit. The electronic circuit includes a reference channel formed by: a transmission calibration stage; a reception calibration stage; and a reference capacitor coupled between the transmission calibration stage and the reception calibration stage.

Abstract: An inductor architecture for resonant clock distribution networks is described. This architecture allows for the adjustment of the natural frequency of a resonant clock distribution network, so that it achieves energy-efficient operation at multiple clock frequencies. The proposed architecture exhibits no inductor overheads. Such an architecture is generally applicable to semiconductor devices with multiple clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs. Moreover, it is applicable to the binning of semiconductor devices according to achievable performance levels.

Abstract: A method for determining flop circuit types includes performing a layout of an IC design including arranging master and slave latches of each of a plurality of flops to receive first and second clock signals, respectively. The initial IC design may then be implemented (e.g., on a silicon substrate). After implementation, the IC may be operated in first and second modes. In the first mode, the master latch of each flop is coupled to receive a first clock signal. In the second mode, the first clock signal is inhibited and the master latch is held transparent. The slave latch of each flop operates according to a second clock signal in both the first and second modes. The method further includes determining, for each flop, whether that flop is to operate as a master-slave flip-flop or as a pulse flop in a subsequent revision of the IC.

Abstract: A disclosed integrated circuit logic cell includes a clock input operative to receive a clock input from a clock tree of the integrated circuit, and clocking circuitry, internal to the logic cell, operative to place a plurality of clock nodes, within the logic cell, in a logical off state in response to a predetermined logic state of the logic cell, thereby preventing the clock nodes from toggling during the predetermined logic state of the logic cell. The integrated circuit logic cell includes primary logic circuitry, internal to the logic cell, operatively coupled to the clocking circuitry which is operatively coupled to an input of the primary logic circuitry. The clocking circuitry provides clock outputs operatively coupled to the clock nodes which are within the primary logic circuitry, and is operative to control the clock outputs in response to the predetermined logic state.

Abstract: An object of the present invention is to provide a driver circuit including a normally-on thin film transistor, which driver circuit ensures a small malfunction and highly reliable operation. The driver circuit includes a static shift register including an inverter circuit having a first transistor and a second transistor, and a switch including a third transistor. The first to third transistors each include a semiconductor layer of an oxide semiconductor and are depletion-mode transistors. An amplitude voltage of clock signals for driving the third transistor is higher than a power supply voltage for driving the inverter circuit.

Abstract: A pulsed latch circuit with conditional shutoff prevents an input node, such as a node receiving data, of the pulsed latch circuit, from latching data based on a delayed input control signal, such as an internal clocking signal, and based on a feedback latch state transition detection signal indicating that a current state of input data is stored in the latch. As such, two control conditions are used to shut down the latch. In one example, a condition generator detects when the latch has captured data correctly and outputs a signal to disable the input node. In addition, a variable delay circuit is used to adjust the width of the allowable input signal to set a worst case shutoff time. If data is latched early, a feedback latch state transition detection signal causes the input node to be disabled. If data is not latched early, the maximum allowable latch time is set by the variable delay circuit.

Abstract: A semiconductor device includes a plurality of CML buffering units configured to buffer, in parallel, a plurality of serially applied data signals to CML levels in a sequence responding to multi-phase source clocks; and a CMOS amplification block configured to amplify a plurality of buffered data signals, sequentially outputted from the plurality of CML buffering units, to CMOS levels in response to the multi-phase source clocks, and output amplified data signals in parallel at the same timing.

Abstract: There is provided a clock signal selection circuit including: a first AND circuit (AND_A1) outputting a logical product signal of a clock selection signal and a first control signal; a second AND circuit (AND_A2) outputting a logical product signal of a logical inversion signal of the clock selection signal and a second control signal; a first flip-flop (FF_A2) inputting either the logical product signal that the first AND circuit outputs or a signal in accordance with the logical product signal, and outputting a logical inversion signal of a first output signal in synchronization with a first clock signal to the second AND circuit as the second control signal; and a second flip-flop (FF_B2) inputting either the logical product signal that the second AND circuit outputs or a signal in accordance with the logical product signal, and outputting a logical inversion signal of a second output signal in synchronization with a second clock signal to the first AND circuit as the first control signal.

Abstract: A flip-flop circuit having a scan function includes an internal clock generator to receive a clock signal, a scan enable signal, and a first input signal, and to output an internal timing signal based on each of the clock signal, the scan enable signal, and the first input signal. The circuit includes a dynamic input unit to receive a second input signal, the scan enable signal, a first timing signal, and the internal timing signal, and to output a first output signal. The circuit also includes a static output unit to receive the first timing signal and the first output signal and to output a static output signal, and the dynamic input unit outputs the first output signal corresponding to one of the first input signal and the second input signal, respectively, based on a status of the scan enable signal.

Abstract: A clock gater includes a first circuit configured to receive a clock signal. The first circuit includes a first subcircuit and a second subcircuit. A latch is configured to receive the clock signal. The latch is connected to the first circuit at each of a first node and a second node. The latch includes a third subcircuit and a fourth subcircuit. The first subcircuit and the third subcircuit are configured to pull the first node and the second node, respectively, to a common precharge voltage in response to a first state of the clock signal in order to pass the clock signal. The second subcircuit and the fourth subcircuit are configured to pull the first node and the second node, respectively, to complementary voltages in response to a second state of the clock signal in order to pass the clock signal, the second state of the clock signal being different from the first state of the clock signal.

Abstract: A synchronizer circuit for transferring data from a source clock domain to a target clock domain. A first latch in the target clock domain may capture a data value corresponding to current data received from the source clock domain. Under certain conditions, the first latch may enter into a metastable, or undefined logic state. A second latch may remain stable, and store a previous value corresponding to data that has most recently been transferred from the source clock domain to the target clock domain. The respective values output by the two latches may be compared by a detection circuit, and a value derived from the output value of the first latch and corresponding to the current data may be written to an output latch if the current data differs from the stored previous value. The detection circuit may also provide a defined logical value to the output latch even if the first latch is in a metastable state.

Abstract: A semiconductor device includes a plurality of CML buffering units configured to buffer, in parallel, a plurality of serially applied data signals to CML levels in a sequence responding to multi-phase source clocks; and a CMOS amplification block configured to amplify a plurality of buffered data signals, sequentially outputted from the plurality of CML buffering units, to CMOS levels in response to the multi-phase source clocks, and output amplified data signals in parallel at the same timing.

Abstract: The semiconductor device with the power down mode includes a power down detecting block for generating a power down mode signal by detecting if the power down mode is activated, a power source control block for producing a power control signal whose ratio of an enable period to a disable period is determined by the power down mode signal, a current saving block whose driving current requirement is reduced in the power down mode, a power switching block for controlling the power supply to the current saving block in response to the power control signal, and a current non-saving block whose driving current requirement in the power down mode is identical to that in a normal operation mode. The semiconductor device can prevent the current consumption due to off-leakage components and static current components generated at internal analog circuits in the power down mode.

Abstract: De-skew is performed on a nibble-by-nibble basis where a nibble is not limited to four bits.

Abstract: Methods and apparatus are provided for time-balanced switching of multiplexer circuits. An embodiment of the invention includes a transistor chain coupled to the output of the multiplexer circuit. The transistor chain preferably delays transitions that would otherwise occur relatively quickly, to match the timing of transitions that occur relatively slowly. The timing of relatively slow transitions is left unaltered. The invention advantageously allows all selector input transitions to yield a data output transition with a substantially constant delay.

Abstract: I/O blocks include input, output, and output enable circuits for interfacing with memory devices. The input circuit includes registers for capturing a double data rate signal, converting it into single data rate signals, and resynchronizing the single data rate signals. Multiple devices may be accessible with each device potentially having a different clock signal for resynchronizing. Another clock signal may be used to align/synchronize resulting signals from multiple devices. The resynchronized single rate signals can be converted into half-rate data signals, and the four half-rate data signals can be provided to resources in the programmable device core. The input circuit also may provide a half-rate clock signal synchronized with the half-rate data signals to the programmable device core. The half rate clock signal can be derived from the full-rate clock signal using a data strobe signal, a full-rate clock signal, or a half-rate clock signal as an input.

Abstract: A method, an apparatus, and a computer program are provided to measure and/or correct duty cycles. Duty cycles of various signals, specifically clocking signals, are important. However, measurement of very high frequency signals, off-chip, and in a laboratory environment can be very difficult and present numerous problems. To combat problems associated with making off-chip measurements and adjustments of signal duty cycles, comparisons are made between input signals and divided input signals that allow for easy measurement and adjustment of on-chip signals, including clocking signals.

Abstract: An exemplary aspect of the invention is to conduct delay tests under actual operating conditions for a semiconductor integrated circuit including multiple logic circuits operating based on clocks of different frequencies, without causing any inconveniences when a test clock is set to a high-frequency side or a low-frequency side. The semiconductor integrated circuit includes: a first logic block that operates based on a first clock; a second logic block that operates based on a second clock having a frequency different from that of the first clock; and a test circuit connected between the first logic block and the second logic block. The test circuit outputs an output of the first logic block set as a test target, without passing through the second logic block, and transmits an input value received without being passed through the first logic circuit, to the second logic circuit set as a test target.