Field-effect Transistor Patents (Class 326/95)
  • Patent number: 10454455
    Abstract: Described herein are reduced-power electronic circuits with wide-band energy recovery using non-interfering topologies. A resonant clock distribution network comprises a plurality of resonant clock drivers that receive at least one of a plurality of reference clock signals. An energy saving component is coupled with the plurality of resonant clock drivers. The energy saving component provides for lower energy consumption by resonating with unwanted parasitic capacitance of a load capacitance. The energy saving component and the load capacitance (LC) form a series resonant frequency that is significantly greater than a clock frequency of the plurality of resonant clock drivers, so that output clock signal paths are not interfered with and so that effects on skew are minimized.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: October 22, 2019
    Assignee: Rezonent Corporation
    Inventor: Ignatius Bezzam
  • Patent number: 10447267
    Abstract: Systems, methods, and devices are provided for increasing uniformity of wear in semiconductor devices due to, for example, negative-bias temperature instability (NBTI). The method may include receiving a first NBTI control signal. The method may involve receiving a second NBTI control signal based at least in part on the first NBTI control signal. The method may also involve asserting the first NBTI control signal at a clock input pin of a latch. Further, the method may include asserting the second NBTI control signal at a data input pin of the latch. The method may additionally involve toggling electrical elements downstream of the latch based at least in part on an output of the latch based on the first and second NBTI control signals to increase uniformity of wear on the electrical elements in a default low-power state during NBTI toggling mode.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: October 15, 2019
    Assignee: Micron Technology, Inc.
    Inventor: William C. Waldrop
  • Patent number: 10230374
    Abstract: Aspects of various embodiments of the present disclosure are directed to methods and circuits preventing hold violations in clock synchronized circuits. In an example implementation, a circuit includes a logic circuit having a set of inputs. Signal propagation time on a signal path to at least one of the set of inputs presents a hold violation. The circuit includes first and second level-sensitive latches. The first level-sensitive latch has an output connected to the one of the plurality of inputs. The second level-sensitive latch has an input connected to an output of the logic circuit. A latch control circuit is configured to remove the hold violation on the input by providing a pulsed clock signal to a clock input of the second level-sensitive latch and an inversion of the pulsed clock signal to a clock input of the first level-sensitive latch.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: March 12, 2019
    Assignee: XILINX, INC.
    Inventors: Ilya K. Ganusov, Benjamin S. Devlin
  • Patent number: 10224933
    Abstract: A dynamic decode circuit for decoding a plurality of input signals comprises a decoder that decodes the plurality of input signals to produce a result at a first node, the result is propagated to a second node while an evaluation clock is active by a pair of serially connected transistors consisting of a transistor receiving an evaluation clock at its gate and a transistor receiving the first node at its gate, the interconnection of the pair of serially connected transistors is precharged when the evaluation clock is inactive to provide a delay between the end of the active evaluation clock and the beginning of the precharge.
    Type: Grant
    Filed: October 29, 2017
    Date of Patent: March 5, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Paul Alan Bunce, Yuen Hung Chan, John D Davis, Antonio Raffaele Pelella
  • Patent number: 10199334
    Abstract: According to one embodiment, a method for manufacturing a digital circuit is described comprising forming a modified RS master latch with an output for outputting an output signal comprising forming two field effect transistors which are virtually identical wherein the two formed field effect transistors are connected to each other in an RS latch type configuration and the respective threshold voltages of the two field effect transistors are set to be different from each other so that the output signal of the modified RS master latch in response to an RS latch forbidden input transition has a predetermined defined logic state, forming an RS slave latch having a set input and a reset input and connecting the set input or the reset input of the RS-slave latch to the output of the modified RS master latch.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: February 5, 2019
    Assignee: Infineon Technologies AG
    Inventors: Thomas Kuenemund, Berndt Gammel
  • Patent number: 10164612
    Abstract: The storage circuit includes first and second logic circuits, first and second transistors whose channel formation regions include an oxide semiconductor, and a capacitor. The first and second transistors are connected to each other in series, and the capacitor is connected to a connection node of the first and second transistors. The first transistor functions as a switch that controls connection between an output terminal of the first logic circuit and the capacitor. The second transistor functions as a switch that controls connection between the capacitor and an input terminal of the second logic circuit. Clock signals whose phases are inverted from each other are input to gates of the first and second transistors. Since the storage circuit has a small number of transistors and a small number of transistors controlled by the clock signals, the storage circuit is a low-power circuit.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: December 25, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yukio Maehashi, Seiichi Yoneda, Wataru Uesugi
  • Patent number: 10135425
    Abstract: Aspects of the disclosure provide a circuit having a pulse latch circuit and an enable circuit. The latch circuit is configured to receive a first signal at an input lead and drive the first signal to an output lead in response to an enable signal. The enable circuit is configured to be active to generate the enable signal to enable the latch circuit to receive the first signal when the first signal is different from a second signal on the output lead and is configured to default the enable signal to suppress the first signal so as not to be received at the latch circuit when the first signal is the same as the second signal.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: November 20, 2018
    Assignee: MARVELL ISRAEL (M.I.S.L.) LTD.
    Inventor: Gideon Paul
  • Patent number: 10037048
    Abstract: An integrated circuits with sequential logic circuitry is provided. The sequential logic circuitry may including latching circuits that receive clock signals from on-chip or off-chip clock sources. The clock signals may exhibit clock skew that is native to the integrated circuit. The natively existing clock skew can be leverage to perform time borrowing to help optimize circuit performance. The desired clock skew can be achieved by intelligent placement of the clock sources and deliberate routing of the clock signals from the clock sources to respective types of clock distribution networks on the integrated circuit.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: July 31, 2018
    Assignee: ALTERA CORPORATION
    Inventor: Mark Bourgeault
  • Patent number: 10001801
    Abstract: A voltage providing circuit includes a first circuit configured to receive a first input signal and a second input signal and to generate an output signal. The first circuit includes a first transistor configured to switchably couple the second input signal to a first node responsive to the first input signal, a second transistor having a gate terminal coupled with the first node, and a third transistor having a source terminal coupled with a source terminal of the second transistor. The third transistor is configured to set a reference voltage value at the source terminal of the second transistor if the first input signal indicates that the second input signal is pulled from a first voltage value toward a second voltage value and if the second input signal reaches a predetermined voltage value. A second circuit is configured to receive the output signal and to generate an output voltage.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: June 19, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: I-Han Huang, Chia-En Huang, Chih-Chieh Chiu, Fu-An Wu, Chun-Jiun Dai, Hong-Chen Cheng, Jung-Ping Yang, Cheng Hung Lee
  • Patent number: 9948282
    Abstract: A retention flip-flop is provided. The flip-flop includes a clock generation circuit, a master latch circuit, and a salve latch circuit. The clock generation circuit generates first and second clock signals in a first mode. The master latch circuit performs a first latch operation on an input signal from the input terminal according to the first and second clock signals to generate a first latched signal at a first node in the first mode. The salve latch circuit performs a second latch operation on the first latched signal according to the first and second clock signals to generate a second latched signal at a second node in the first mode. In a sleep or power-down mode, the total number of transistors in the clock generation circuit and the salve latch circuit is equal to or less than eight.
    Type: Grant
    Filed: October 26, 2015
    Date of Patent: April 17, 2018
    Assignee: MEDIATEK INC.
    Inventor: Rei-Fu Huang
  • Patent number: 9876500
    Abstract: A semiconductor circuit includes a first circuit, a second circuit, a third circuit, and a fourth circuit. The first circuit determines a value of a first node based on a voltage level of a clock signal, and a voltage level of an enable signal or a voltage level of a scan enable signal. The second circuit determines a value of a second node based on the voltage levels of the first node and the clock signal. The third circuit determines a value of a third node based on a voltage level of the second node. The fourth circuit determines a value of a fourth node based on the voltage levels of the second node and the clock signal. The third circuit includes a first transistor and a second transistor connected in series with each other and gated to the voltage level of the second node to determine the value of the third node. The fourth circuit includes a third transistor that is gated to the voltage level of the clock signal to electrically connect the third node and the fourth node.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: January 23, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ah Reum Kim, Min Su Kim, Chung Hee Kim, Hyun Chul Hwang
  • Patent number: 9711231
    Abstract: Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of a memory cell can shift depending on when the read operation occurs. In one aspect, read voltages are set and optimized based on a time period since a last sensing operation. A timing device such as an n-bit digital counter may be provided for each block of memory cells to track the time. The counter is set to all 1's when the device is powered on. When a sensing operation occurs, the counter is periodically incremented based on a clock. When a next read operation occurs, the value of the counter is cross-referenced to an optimal set of read voltage shifts. Each block of cells may have its own counter, where the counters are incremented using a local or global clock.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: July 18, 2017
    Assignee: SanDisk Technologies LLC
    Inventors: Chris Yip, Philip Reusswig, Nian Niles Yang, Grishma Shah, Abuzer Azo Dogan, Biswajit Ray, Mohan Dunga, Joanna Lai, Changyuan Chen
  • Patent number: 9680470
    Abstract: Digital circuits are disclosed that may include multiple transistors having controllable current paths coupled between first and second logic nodes. One or more of the transistors may have a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a relatively highly doped screen layer formed over a doped body region. Resulting reductions in threshold voltage variation may improve digital circuit performance. Logic circuit, static random access memory (SRAM) cell, and passgate embodiments are disclosed.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: June 13, 2017
    Assignee: Mie Fujitsu Semiconductor Limited
    Inventors: Scott E. Thompson, Lawrence T. Clark
  • Patent number: 9627012
    Abstract: Aspects include a computer-implemented method for scanning data into a shift register. The method includes receiving, by a circuit, a data signal, wherein the data signal propagates in a first direction; and receiving, by the circuit, a clock signal, wherein the clock signal propagates in a second direction, wherein the second direction is in a reverse direction of the first direction.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: April 18, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: William V. Huott, Norman K. James, Pradip Patel, Daniel Rodko
  • Patent number: 9537485
    Abstract: Aspects disclosed herein describe a keeper circuit that adapts to variations in the fabrication process used to manufacture a dynamic circuit. The different characteristics of the circuit elements may cause a keeper circuit to behave in an unintended manner. In one example, a logical state of the dynamic circuit may be erroneously changed because of a strong (i.e., leaky) NMOS transistor in a pull down or discharge path. An adaptive keeper circuit, however, is designed to prevent such unintended behavior regardless of any change in the characteristics of the circuit elements in the dynamic circuit. The adaptive keeper circuit matches the behavior of the pull down path and prevents the pull down path from erroneously changing the logical state stored by the dynamic circuit.
    Type: Grant
    Filed: February 24, 2015
    Date of Patent: January 3, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Joshua Lance Puckett, Anthony Dale Klein, Kaushik Viswanathan
  • Patent number: 9490779
    Abstract: Synchronisation circuitry 2 comprises a first dynamic circuit stage 4 generating a first stage state signal which is pulse amplified by pulse amplifying circuitry 8 to generate a pulse amplified signal. The pulse amplified signal is supplied to a second dynamic circuit stage 6 where it is used to control generation of a second stage state signal. The pulse amplifying circuitry 8 comprises a chain of serially connected skewed inverters 20, 22. The action of the pulse amplifying circuitry 8 is to reduce the probability of metastability in the output of the second dynamic stage 6.
    Type: Grant
    Filed: July 12, 2013
    Date of Patent: November 8, 2016
    Assignee: The Regents of the University of Michigan
    Inventors: Bharan Giridhar, Matthew Rudolph Fojtik, David Alan Fick, Dennis Michael Sylvester, David Theodore Blaauw
  • Patent number: 9473148
    Abstract: An oscillator circuit includes a voltage-controlled oscillator configured to output an AC output signal having a predetermined frequency, which changes due to temperature and fabrication process variations and a control voltage generating circuit configured to provide a voltage signal to the voltage-controlled oscillator to maintain the predetermined frequency by compensating for the temperature and fabrication process variations.
    Type: Grant
    Filed: March 9, 2015
    Date of Patent: October 18, 2016
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Hua Tang, Fei Liu, Benpeng Xun
  • Patent number: 9460250
    Abstract: The present disclosure relates to a computer-implemented method for transient simulation of an input/output buffer model. The method may include generating an input/output buffer data file associated with a first model of an electrical circuit. The method may also include determining at least one of a node voltage and a branch current associated with the electrical circuit using, at least in part, a latency insertion method, the method may further include performing one or more simulations on a second model of an electrical circuit, the one or more simulations incorporating, at least in part, the input/output buffer data file and the latency insertion method.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: October 4, 2016
    Assignee: Cadence Design Systems, Inc.
    Inventors: Jose Emmanuel Schutt-Aine, Dennis Nagle, Feras Al-Hawari, Ambrish Kant Varma, Jilin Tan, Ping Liu, Shangli Wu, Yubao Meng, Qi Zhao, Zhongyong Zhou
  • Patent number: 9438206
    Abstract: The storage circuit includes first and second logic circuits, first and second transistors whose channel formation regions include an oxide semiconductor, and a capacitor. The first and second transistors are connected to each other in series, and the capacitor is connected to a connection node of the first and second transistors. The first transistor functions as a switch that controls connection between an output terminal of the first logic circuit and the capacitor. The second transistor functions as a switch that controls connection between the capacitor and an input terminal of the second logic circuit. Clock signals whose phases are inverted from each other are input to gates of the first and second transistors. Since the storage circuit has a small number of transistors and a small number of transistors controlled by the clock signals, the storage circuit is a low-power circuit.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: September 6, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yukio Maehashi, Seiichi Yoneda, Wataru Uesugi
  • Patent number: 9351369
    Abstract: A leakage current detection circuit detects a switch current flowing in a switch which is targeted for leakage monitoring, and generates a detection signal to prohibit operation of a control target circuit which is targeted for control when the switch current does not reach a predetermined threshold value.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: May 24, 2016
    Assignees: Rohm Co., Ltd., Honda Motor Co., Ltd.
    Inventors: Kouji Miyamoto, Masaaki Nakayama, Akira Aoki, Koji Okamoto, Masaharu Ando, Yosuke Tsuchiya
  • Patent number: 9276578
    Abstract: A dynamic logic gate includes a nano-electro-mechanical-switch, preferably a four-terminal-nano-electro-mechanical-switch. The invention further refers to dynamic logic cascade circuits comprising such a dynamic logic gate. In particular, embodiments of the invention concern dynamic logic cascade circuits comprising single or dual rail dynamic logic gates.
    Type: Grant
    Filed: August 26, 2013
    Date of Patent: March 1, 2016
    Assignee: International Business Machines Corporation
    Inventors: Michel Despont, Daniel Grogg, Christoph Hagleitner, Yu Pu
  • Patent number: 9276579
    Abstract: A dynamic logic gate includes a nano-electro-mechanical-switch, preferably a four-terminal-nano-electro-mechanical-switch. The invention further refers to dynamic logic cascade circuits comprising such a dynamic logic gate. In particular, embodiments of the invention concern dynamic logic cascade circuits comprising single or dual rail dynamic logic gates.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: March 1, 2016
    Assignee: International Business Machines Corporation
    Inventors: Michel Despont, Daniel Grogg, Christoph Hagleitner, Yu Pu
  • Patent number: 9252754
    Abstract: A scan flip-flop, which performs a normal operation latching a data input and a scan operation latching a scan input, includes a first circuit, a second circuit and a latch. The first circuit determines a voltage of an intermediate node based on a clock signal, one of the data input and the scan input, and data of a latch input node. The second circuit determines the data based on the clock signal, the voltage of the intermediate node and the data input during the normal operation, and determines the data based on the clock signal and the voltage of the intermediate node during the scan operation. The latch latches the data based on the clock signal.
    Type: Grant
    Filed: September 21, 2012
    Date of Patent: February 2, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Min Su Kim
  • Patent number: 9182782
    Abstract: An integrated circuit includes a first pipeline with multiple stages of asynchronous circuits. Note that a stage in the first pipeline communicates with a stage in a corresponding second pipeline with multiple stages of asynchronous circuits on another integrated circuit via connectors. Furthermore, a first state wire preceding the stage in the first pipeline provides advanced notice to a first state wire preceding the stage in the second pipeline of subsequent communication between the stage in the first pipeline and the stage in the second pipeline so that the stage in the second pipeline has time to amplify a signal received from the stage in the first pipeline, thereby facilitating approximately synchronous operation of the stages in the first and second pipelines.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: November 10, 2015
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventor: Ivan E. Sutherland
  • Patent number: 9088277
    Abstract: An output driver circuit may include a electrically conductive medium, an output logic inverter having a first switch adapted to couple a first positive supply voltage to the electrically conductive medium and a second switch adapted to couple a ground supply voltage to the conductive medium. A first biasing network includes a first input that is coupled to the conductive medium, a second input that receives a clock signal, and a first output that is adapted to couple a second positive supply voltage to each input of the first and the second switch. Based on the second switch coupling the conductive medium to the ground supply voltage and the received clock signal generating a logic low, the biasing network reverse biases the first switch by coupling the second positive supply voltage to the respective input of the first switch causing a leakage current reduction in the first switch.
    Type: Grant
    Filed: November 8, 2013
    Date of Patent: July 21, 2015
    Assignee: International Business Machines Corporation
    Inventors: Igor Arsovski, Travis R. Hebig
  • Patent number: 9082465
    Abstract: A memory circuit is provided comprising a plurality of bit cells coupled to a bit line that permits accessing information from each of the plurality of bit cells. A sense inverter is coupled to an output of the bit line. A keeper circuit has an output coupled to the bit line to compensate for current leakage from the plurality of bit cells. The keeper circuit may comprise an n-channel metal-oxide-silicon (NMOS) transistor in series with a p-channel metal-oxide-silicon (PMOS) transistor.
    Type: Grant
    Filed: February 12, 2013
    Date of Patent: July 14, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Balachander Ganesan, Ritu Chaba, Sei Seung Yoon
  • Patent number: 9018981
    Abstract: A latch circuit includes a latch unit and a clock propagation suppressing unit. The latch circuit holds and outputs input data of 0 or 1. The clock propagation suppressing unit compares the input data input to the latch unit with output data output from the latch unit. When it is detected that the input data matches the output data at 0, or that the input data matches the output data at 1, an externally input clock signal is prevented from propagating to the latch unit.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: April 28, 2015
    Assignee: Fujitsu Limited
    Inventor: Katsunao Kanari
  • Publication number: 20150097595
    Abstract: To reduce a leakage current of a transistor so that malfunction of a logic circuit can be suppressed. The logic circuit includes a transistor which includes an oxide semiconductor layer having a function of a channel formation layer and in which an off current is 1×10?13 A or less per micrometer in channel width. A first signal, a second signal, and a third signal that is a clock signal are input as input signals. A fourth signal and a fifth signal whose voltage states are set in accordance with the first to third signals which have been input are output as output signals.
    Type: Application
    Filed: December 15, 2014
    Publication date: April 9, 2015
    Inventors: Shunpei YAMAZAKI, Jun KOYAMA, Masashi TSUBUKU, Kosei NODA
  • Publication number: 20150084673
    Abstract: A timing margin circuit of a local clock buffer circuit may include an inverter logic gate having an inverter input and an inverter output, whereby the inverter input receives an input clock signal. A NAND logic gate includes a first NAND input coupled to the inverter output, a second NAND input, and a NAND output. The circuit also includes a logic device having a first logic device input that is coupled to the inverter output, a second logic device input that receives a mode selection signal, and a logic device output that couples to the second NAND input, whereby the NAND logic gate generates a first time delayed input clock signal and a second time delayed input clock signal, such that the first and the second time delayed input clock signal control a falling edge transition of a local clock signal derived from the input clock signal.
    Type: Application
    Filed: September 24, 2013
    Publication date: March 26, 2015
    Applicant: International Business Machines Corporation
    Inventors: Bruce M. Fleischer, James D. Warnock
  • Patent number: 8988107
    Abstract: An integrated circuit with a pulse clock unit having shared gating control includes one or more logic blocks, each including a clock distribution network configured to distribute a clock signal. The integrated circuit also includes a clock unit coupled to the one or more logic blocks and configured to generate a pulse clock signal formed using a chain of inverting logic gates. The clock unit may be further configured to provide the pulse clock signal to the clock distribution network. The clock unit may also include an enable input that is coupled to one input of one of the inverting logic gates. In addition, the clock unit may be configured to selectively enable and disable the pulse clock signal in response to an enable signal on the enable input.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: March 24, 2015
    Assignee: Apple Inc.
    Inventor: Edward M. McCombs
  • Patent number: 8981815
    Abstract: A clock gating circuit for generating a clock enable signal with respect to a clock input signal and a logic enable signal includes: a first plurality of transistors for receiving at least the logic enable signal and generating a first output; a second plurality of transistor for receiving at least the first output and generating a second output; a third plurality of transistors for receiving at least the second output and an inverted second output; and an AND gate circuit, for receiving the second output and generating the clock enable signal when the logic enable signal is at logic 1. One transistor of the first plurality of transistors, the second plurality of transistors and the third plurality of transistors, respectively, receives the clock input signal at its gate.
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: March 17, 2015
    Assignee: MediaTek Singapore Pte. Ltd.
    Inventor: Sumanth Katte Gururajarao
  • Patent number: 8957718
    Abstract: A flip-flop circuit has a master latch circuit and a slave latch circuit. In the flip-flop circuit, the master latch circuit and the slave latch circuit share at least a pair of transistors. In response to the clock signal, the signal held in the master latch circuit can be output at higher speed as the output signal via the intermediate node, the slave latch circuit and the output circuit. The flip-flop circuit can be reduced in cell size and improved in processing speed.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: February 17, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Muneaki Maeno
  • Publication number: 20150008968
    Abstract: Apparatuses and methods for phase interpolating clock signals and for providing duty cycle corrected clock signals are described. An example apparatus includes a first inverter configured to receive first and second clock signals and further includes a second inverter configured to receive the first and second clock signals. The first inverter is configured to provide to an output node an inverted first clock signal as controlled by the second clock signal. The second inverter is configured to provide to the output node an inverted second clock signal as controlled by the first clock signal. Another example apparatus includes a clock generator circuit to provide first and second clock signals responsive to an input clock signal, and further includes a duty phase interpolator circuit, a duty cycle adjuster and a duty cycle detector.
    Type: Application
    Filed: July 8, 2013
    Publication date: January 8, 2015
    Inventor: Yantao Ma
  • Patent number: 8928354
    Abstract: A clock-delayed domino logic circuit includes a precharge circuit configured to control connection between a first node and a dynamic node in response to a clock signal, an evaluation circuit configured to control connection between a second node and an evaluation node in response to the clock signal, a logic network connected between the dynamic node and the evaluation node, the logic network configured to determine a logic level of the dynamic node based on a plurality of input signals, and a phase control circuit configured to output a logic level of the evaluation node or a logic level of the first node according to a level of the clock signal.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: January 6, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Min Su Kim
  • Patent number: 8907700
    Abstract: A clock-delayed domino logic circuit includes a first pre-charge circuit configured to pre-charge a first dynamic node with a pre-charge voltage in response to a first clock signal received via a first control terminal during a pre-charge operation; a first logic network configured to determine a logic level of the first dynamic node in response to first input data signals during an evaluation operation; and a first storage circuit which is connected between the first control terminal and the first dynamic node.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: December 9, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Rahul Singh, Hyoung Wook Lee
  • Patent number: 8907701
    Abstract: The present invention discloses a CMOS differential logic circuit. The CMOS differential logic circuit includes a precharge differential logic unit, which is precharged to a source voltage in response to a clock signal and is configured to output voltage having an increased load-driving ability using a boosting voltage; a voltage-boosting unit, which is pulled down by a ground voltage in response to the clock signal and is configured to boost the pulled-down voltage using capacitive coupling and output the boosting voltage; and a switching unit, which is configured to couple the precharge differential logic unit and the voltage-boosting unit in response to the clock signal. The propagation delay of a signal from the input terminal to the output terminal of a circuit in a low-source-voltage environment can be reduced, and the operating speed of the circuit and energy efficiency of the operation thereof can be improved.
    Type: Grant
    Filed: February 19, 2013
    Date of Patent: December 9, 2014
    Assignee: Research & Business Foundation Sungkyunkwan University
    Inventors: Bai Sun Kong, Jong Woo Kim, Joo Seong Kim
  • Patent number: 8901965
    Abstract: A dual-mode logic gate, for selectable operation in either of static and dynamic modes, includes: a static gate which includes at least one logic input and a logic output; a mode selector, configured for outputting a turn-off signal to select static mode operation and for outputting a dynamic clock signal to select dynamic mode operation; and a switching element associated with the mode selector static gate, comprising a first input connected to a constant voltage, a second input for inputting the mode selection signal from the mode selector, and an output connected to a logic output of the static gate. The switching elements switches the logic gate operation from static to dynamic mode, by applying the appropriate signal to the switching element.
    Type: Grant
    Filed: August 2, 2012
    Date of Patent: December 2, 2014
    Assignee: Ben-Gurion University of the Negev Research and Development Authority
    Inventors: Alexander Fish, Asaf Kaizerman, Sagi Fisher, Itamar Levy
  • Patent number: 8890572
    Abstract: Embodiments of the present disclosure enable low swing dynamic circuits with reduced dynamic power and leakage power. In an embodiment, a level detector circuit monitors the pre-charge voltage level of the dynamic node of a dynamic circuit and discontinues the charging of the dynamic node when the pre-charge voltage exceeds a logic high reference voltage. The logic high reference voltage is selected below a supply voltage of the dynamic circuit, resulting in a low swing dynamic circuit. In another embodiment, the pull-down logic circuitry is disconnected from the dynamic node when the dynamic node voltage falls below a logic low reference voltage, above a ground voltage. In another embodiment, a DC keeper circuit of the dynamic circuit is configured based on the pre-charge level of the dynamic node.
    Type: Grant
    Filed: September 19, 2012
    Date of Patent: November 18, 2014
    Assignee: Broadcom Corporation
    Inventor: Sachin Joshi
  • Patent number: 8866510
    Abstract: When a semiconductor device is provided with an inverter comprising a transistor having a first gate and a second gate, the semiconductor device does not require a circuit for generating a potential to be input to the second gate of the transistor and has a small number of wirings. Moreover, a semiconductor device having high reliability is provided. The semiconductor device includes a plurality of stages of circuits each provided with two inverter circuits in parallel. Two inverter circuits in a given stage output respective signals of opposite polarities, which is utilized for interchanging signals output from inverter circuits in the previous stage. Thus, an inverted signal is input to the second gate of the transistor included in each of two inverter circuits in the subsequent stage.
    Type: Grant
    Filed: April 26, 2013
    Date of Patent: October 21, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toru Tanabe, Hiroyuki Miyake
  • Patent number: 8860464
    Abstract: A zero keeper circuit includes a dynamic input PFET connected to a source, an output, and a dynamic input. The circuit also includes a clock input NFET connected to the output, a pull-down node, and a clock input. The circuit also includes a dynamic input NFET connected to the pull-down node, a reference voltage, and the dynamic input. The circuit also includes a feedback PFET and a clock input PFET connected in series between the source and the output. The feedback PFET receives a feedback signal and the clock input PFET receives the clock input. The circuit also includes a feedback NFET connected to the output and the node. The feedback NFET is configured to couple the output to the node based on the feedback signal. The circuit also includes a NOR gate configured to provide the feedback signal based on the output and a bypass input.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: October 14, 2014
    Assignee: Apple Inc.
    Inventors: Hitesh K Gupta, Greg M Hess, Naveen Javarappa
  • Publication number: 20140292372
    Abstract: A clock gating circuit for generating a clock enable signal with respect to a clock input signal and a logic enable signal includes: a first plurality of transistors for receiving at least the logic enable signal and generating a first output; a second plurality of transistor for receiving at least the first output and generating a second output; a third plurality of transistors for receiving at least the second output and an inverted second output; and an AND gate circuit, for receiving the second output and generating the clock enable signal when the logic enable signal is at logic 1. One transistor of the first plurality of transistors, the second plurality of transistors and the third plurality of transistors, respectively, receives the clock input signal at its gate.
    Type: Application
    Filed: March 19, 2014
    Publication date: October 2, 2014
    Applicant: MediaTek Singapore Pte. Ltd.
    Inventor: Sumanth Katte Gururajarao
  • Publication number: 20140292371
    Abstract: A Multi-Threshold Dual-spacer Dual-rail Delay-insensitive Logic (MTD3L) circuit architecture. The architecture includes a first th22 circuit, a second th22 circuit, and an XNOR gate. The first th22 circuit is configured to receive a first rail input, a completion detection signal, and a reset signal, and to produce a first rail output. The second th22 circuit is configured to receive a second rail input, the completion detection signal, and the reset signal, and to produce a first rail output. The XNOR gate is configured to receive the first rail input and the second rail input and to produce a completion detection signal output.
    Type: Application
    Filed: April 10, 2013
    Publication date: October 2, 2014
    Inventor: THE BOARD OF TRUSTEES OF THE UNIVERSITY OF ARKANSAS
  • Patent number: 8847627
    Abstract: A semiconductor device includes a first transistor, a second transistor, a first transistor group, and a second transistor group. The first transistor group includes a third transistor, a fourth transistor, and four terminals. The second transistor group includes fifth to eighth transistors and four terminals. The first transistor, the third transistor, the sixth transistor, and the eighth transistor are n-channel transistors, and the second transistor, the fourth transistor, the fifth transistor, and the seventh transistor are p-channel transistors.
    Type: Grant
    Filed: May 16, 2012
    Date of Patent: September 30, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Tatsuya Ohnuki
  • Patent number: 8836371
    Abstract: Methods and systems are disclosed for reduced coupling between digital signal lines. For disclosed embodiments, return-to-zero signaling is dynamically blocked so that high logic levels remain high through entire clock cycles where the next data to be output is also at high logic levels. The dynamically blocked return-to-zero signaling reduces capacitive coupling between digital signal lines, such as clock and data signal lines, that are in close proximity to each other by reducing current flow that would otherwise occur with return-to-zero signaling. The dynamically blocked return-to-zero signaling can be used in a wide variety of environments and implementations.
    Type: Grant
    Filed: January 22, 2013
    Date of Patent: September 16, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Perry H. Pelley, James D. Burnett
  • Patent number: 8836402
    Abstract: A phase splitter includes: a first signal path; and a second signal path, wherein the phase splitter outputs an internal signal of the first signal path as a first phase signal, and mixes an output signal of the first signal path with an output signal of the second signal path, thereby outputting a second phase signal having a predetermined phase difference from the first phase signal.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: September 16, 2014
    Assignee: SK Hynix Inc.
    Inventor: Min Sik Han
  • Patent number: 8797065
    Abstract: A selector circuit includes a plurality of first selection circuits each configured to select one of plural input signals on the basis of a first selection control signal and to output a first output signal and a second selection circuit configured to select one of the first output signals on the basis of a second selection control signal. Each of the first selection circuits includes a charging circuit configured to charge a first node by electrically connecting the first node to a first voltage in a first period, and a discharge control circuit configured to control, on the basis of the first selection control signal, the input signals and the second selection control signal, whether to discharge the charged first node by electrically connecting the first node to a second voltage source having a potential lower than the first voltage source in a second period following the first period.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: August 5, 2014
    Assignee: Fujitsu Limited
    Inventor: Tomohiro Tanaka
  • Patent number: 8786309
    Abstract: A multi-path power switch scheme for functional block wakeup is disclosed. The scheme may be applied to functional blocks of an integrated circuit. When a power on procedure is initiated within a given functional block, a first group of power switches in a functional block may be powered on, while a second group of power switches is inhibited from powering on. After a predetermined time has elapsed, activation of the second group of power switches is initiated. After initiation of a power up procedure for a given functional block, the powering up of a second functional block to be powered on may initially be inhibited. After a predetermined time has elapsed, the powering on of the second functional block may be initiated. Overlap between times when the first and second groups of switches are active may depend on process, voltage, and temperature variations.
    Type: Grant
    Filed: October 31, 2011
    Date of Patent: July 22, 2014
    Assignee: Apple Inc.
    Inventors: Toshinari Takayanagi, Shingo Suzuki
  • Patent number: 8786345
    Abstract: One embodiment of the present invention sets forth a technique for capturing and storing a level of an input signal using a single-trigger low-energy flip-flop circuit that is fully-static and insensitive to fabrication process variations, The single-trigger low-energy flip-flop circuit presents only three transistor gate loads to the clock signal and none of the internal nodes toggle when the input signal remains constant, The output signal Q is set or reset at the rising clock edge using a single- trigger sub-circuit. A set or reset may be armed while the clock signal is low, and the set or reset is triggered at the rising edge of the clock.
    Type: Grant
    Filed: March 28, 2013
    Date of Patent: July 22, 2014
    Assignee: NVIDIA Corporation
    Inventors: Jonah M. Alben, William J. Dally
  • Patent number: 8779798
    Abstract: In order to reduce power consumption, an arithmetic circuit having a function of performing a logic operation processing based on an input signal, storing a potential set in accordance with the result of the logic operation processing as stored data, and outputting a signal with a value corresponding to the stored data as an output signal. The arithmetic circuit includes an arithmetic portion performing the logic operation processing, a first field-effect transistor controlling whether a first potential, which is the potential corresponding to the result of the logic operation processing is set, and a second field-effect transistor controlling whether the potential of the output signal data is set at a second potential which is a reference potential.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: July 15, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Kiyoshi Kato
  • Patent number: 8760208
    Abstract: An apparatus may include a storage circuit that may have a first terminal and a second terminal and may have two cross-coupled inverters. The apparatus may include a feedback circuit coupled to the first terminal. The feedback circuit may include electronic logic elements to determine if the storage circuit is in a metastable state. The feedback circuit may couple at least one of the first and second terminals to one of a voltage reference and a voltage source if determined that the storage circuit is in a metastable state.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: June 24, 2014
    Assignee: Intel Corporation
    Inventors: Charles E. Dike, Mark E. Schuelein