Mosfet Patents (Class 326/98)
  • Patent number: 10515670
    Abstract: A memory apparatus and a voltage control method of the memory apparatus are provided. The memory apparatus of the invention includes a synchronous circuit, a clock tree and a memory controller. The synchronous circuit receives a reference clock and generating a clock signal. The clock tree is coupled to an output end of the multiplexer and assigns the clock signal to a plurality of signal paths. The memory controller is coupled to the synchronous circuit and controls the synchronous circuit to adjust a frequency of the clock signal according to an operating mode of the memory apparatus.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: December 24, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Wen-Ming Lee, Chuan-Jen Chang
  • Patent number: 10466968
    Abstract: A system including a series of partial product select encoders and partial product muxes, each of the partial product select encoders receiving a multiplier, receiving a carry input from a multiplier tree, and outputting a select signal to an associated partial product mux based on the multiplier and carry input, and each of the partial product muxes outputting a partial product based on the select signal and a multiplicand received.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: November 5, 2019
    Assignee: NVIDIA Corp.
    Inventor: Ilyas Elkin
  • Patent number: 10438937
    Abstract: A system and method for creating layout for non-planar cells with redundancy in one or more of output contacts and power contacts are described. In various implementations, cell layout is created for a first cell with non-planar devices. An available local path in the first cell is identified for redundant output signal routing, which includes a free available metal zero layer track. Redundant metal zero layer is placed in an available metal zero track of the available local path. Redundant contacts and redundant metal one layer are placed in a free track in the available local path to connect an original output contact to a redundant output contact. An available external path is identified between the first cell and a second cell for redundant power or ground routing. One or more metal zero extension layers and/or metal one extension layers are placed in the identified external path.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: October 8, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Richard T. Schultz
  • Patent number: 10324721
    Abstract: By shutting off keeper transistors during pre-charge, the aging on these devices may be reduced. This means that a relatively weaker keeper may be used for noise compared to an overdesigned stronger keeper. Using a relatively weaker keeper circuit results in a faster evaluation stage and improved minimum read voltage in some embodiments.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: June 18, 2019
    Assignee: Intel Corporation
    Inventors: Anupama A. Thaploo, Bhushan M. Borole, Bee Ngo, Iqbal R. Rajwani, Altug Koker, Abhishek R. Appu, Kamal Sinha, Wenyin Fu
  • Patent number: 10269419
    Abstract: Described is an apparatus which comprises: a memory bit-cell; a local bit-line (LBL) coupled to the memory bit-cell via a read port device; a NAND gate circuitry coupled to the LBL; and a stack of keepers coupled to the LBL, wherein at least one transistor of the stack of keepers is controllable according to an output of the NAND gate circuitry, wherein the stack of keepers includes transistors with variable strength which are to be turned on overtime.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: April 23, 2019
    Assignee: Intel Corporation
    Inventors: Jaydeep P. Kulkarni, Vivek K. De, Muhammad M. Khellah
  • Patent number: 10164773
    Abstract: Described is an apparatus comprising precharge paths including first clocked transistors having gates coupled to a clock signal path, first terminals coupled to a first power rail, and second terminals coupled to one or more first junction nodes. The precharge paths lack a keeper circuitry, have a configurable keeper circuitry, and/or have cross-coupled keeper circuitry to eliminate/reduce keeper contention during domino logic evaluation. The apparatus may comprise second clocked transistors having gates coupled to the clock signal path, first terminals coupled to one or more second junction nodes, and second terminals coupled to a second power rail. The apparatus may comprise sets of evaluation transistors having conducting channels coupled in series, coupled to the one or more first junction nodes, and coupled to one of the one or more second junction nodes. A NAND or inverter circuitry with inputs is coupled to the one or more first junction nodes.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: December 25, 2018
    Assignee: Intel Corporation
    Inventors: Vikram B. Suresh, Sanu K. Mathew, Sudhir K. Satpathy
  • Patent number: 10090333
    Abstract: In order to reduce power consumption, an arithmetic circuit having a function of performing a logic operation processing based on an input signal, storing a potential set in accordance with the result of the logic operation processing as stored data, and outputting a signal with a value corresponding to the stored data as an output signal. The arithmetic circuit includes an arithmetic portion performing the logic operation processing, a first field-effect transistor controlling whether a first potential, which is the potential corresponding to the result of the logic operation processing is set, and a second field-effect transistor controlling whether the potential of the output signal data is set at a second potential which is a reference potential.
    Type: Grant
    Filed: June 6, 2014
    Date of Patent: October 2, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Kiyoshi Kato
  • Patent number: 10056882
    Abstract: At least some embodiments are directed to a flip-flop that comprises a tri-state inverter and a master latch coupled to the tri-state inverter and comprising a first transistor, a first inverter, and a first logic gate. The master latch receives a clock signal. The flop also comprises a slave latch coupled to the master latch and comprising a second transistor and a second inverter. The slave latch receives the clock signal. The flop further comprises an enablement logic coupled to the master latch and comprising multiple, additional logic gates. The tri-state inverter, the master and slave latches, and the enablement logic are configured so that when a flip-flop input signal D and a flip-flop output signal Q are identical and the clock signal is toggled, a state of the master latch and a state of the slave latch remain static.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: August 21, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Suvam Nandi, Badarish Mohan Subbannavar
  • Patent number: 10027325
    Abstract: A circuit coupled to receive an input voltage that can span a wide voltage supply range and a voltage translator that includes the circuit are disclosed. The circuit includes a first metal oxide silicon (MOS) transistor having a first conductivity type and a first threshold voltage and a second MOS transistor having the first conductivity type and a second threshold voltage that is lower than the first threshold voltage. The first MOS transistor is coupled in parallel with the second MOS transistor between a first rail and a first signal line; the first MOS transistor and the second MOS transistor each receive a first signal on a respective gate.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: July 17, 2018
    Assignee: Texas Instruments Incorporated
    Inventor: Christopher Michael Graves
  • Patent number: 9940992
    Abstract: Leakage-aware activation control of a delayed keeper circuit for a dynamic read operation in a memory bit cell is disclosed. In one aspect, a leakage-aware activation control circuit is provided for a dynamic read circuit configured to perform read operations on a memory bit cell. To prevent or mitigate contention between the delayed keeper circuit and a read port circuit in the dynamic read circuit pulling a dynamic node to opposite voltage levels when a read operation is initiated, the leakage-aware activation control circuit is configured to adaptively control activation timing of the delayed keeper circuit based on a comparison of N-type Field-Effect Transistor (NFET) leakage current to P-type FET (PFET) leakage current. In this manner, the leakage-aware activation control circuit can adaptively adjust the activation timing of the delayed keeper circuit based on the actual relative strengths of NFETs and PFETs.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: April 10, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Francois Ibrahim Atallah, Hoan Huu Nguyen, Keith Alan Bowman
  • Patent number: 9437555
    Abstract: It is desirable to design and manufacture electronic chips that are resistant to modern reverse engineering techniques. Disclosed is a method and device that allows for the design of chips that are difficult to reverse engineer using modern teardown techniques. The disclosed device uses devices having the same geometry but different voltage levels to create different logic devices. Alternatively, the disclosed uses devices having different geometries and the same operating characteristics. Also disclosed is a method of designing a chip using these devices.
    Type: Grant
    Filed: October 2, 2014
    Date of Patent: September 6, 2016
    Assignee: Verisiti, Inc.
    Inventor: William Eli Thacker, III
  • Patent number: 9374075
    Abstract: An input apparatus may include a pulse width control circuit, a reception circuit, and a latch circuit. The pulse width control circuit may be configured to generate a pulse width control signal by performing a logical operation on a pulse width detection signal and a clock signal. The reception circuit may be configured to selectively provide a received input signal as a period signal on the basis of the clock signal and the pulse width control signal. The latch circuit may be configured to provide an output signal by inverting the period signal, and provide the output signal as the pulse width detection signal in response to the clock signal.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: June 21, 2016
    Assignee: SK hynix Inc.
    Inventor: Nohhyup Kwak
  • Patent number: 9349849
    Abstract: In a semiconductor device including a transistor, an oxygen release type oxide insulating film is formed in contact with a channel formation region of the transistor. The channel formation region is formed in an oxide semiconductor film. Oxygen is supplied from the oxide insulating film to the oxide semiconductor film. Further, an oxygen bather film which penetrates the oxide insulating film is formed around the channel formation region, whereby a diffusion of oxygen to the wiring, the electrode, and the like connected to the transistor can be suppressed.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 24, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Tetsuhiro Tanaka
  • Patent number: 9324384
    Abstract: In a sense amplifier, a switching transistor is configured to apply a ground voltage to a ground node in response to a sense enable signal. A first detection circuit is configured to output a first detection signal to the first detection node based on a mode signal and a voltage of a bit-line. A second detection circuit is configured to output a second detection signal to the second detection node based on a voltage of a complementary bit-line. A latch circuit is connected to a supply voltage, the first detection node and the second detection node, and configured to output a first amplified signal and a second amplified signal through a latch node and a complementary latch node, respectively, based on the first detection signal and the second detection signal.
    Type: Grant
    Filed: October 2, 2014
    Date of Patent: April 26, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tae-Joong Song, Sung-Hyun Park, Woo-Jin Rim, Gi-Young Yang
  • Patent number: 9286555
    Abstract: An information processing device includes a computing unit and a display unit. The computing unit computes a power consumption per a predetermined time during a power saving mode that reduces power consumption, on the basis of a count per type of an interrupt signal produced during the power saving mode, and a power consumption pre-estimated per type of the interrupt signal. The display unit displays a power consumption computed by the computing unit using generated or stored electric power.
    Type: Grant
    Filed: May 7, 2014
    Date of Patent: March 15, 2016
    Assignee: FUJI XEROX CO., LTD
    Inventors: Kenji Kuroishi, Tsutomu Nakaminato, Masafumi Ono, Motofumi Baba, Keiko Shiraishi, Yuri Takeuchi, Koichi Azuma, Kazuhiko Narushima, Hidenori Horie
  • Patent number: 9281820
    Abstract: An asynchronous pipeline structure includes a plurality of functional blocks comprising dynamic logic, each block precharged to an idle state responsive to a precharge control signal applied thereto, with each block, upon being precharged, receiving input data thereto for processing, and holding output data generated thereby during an evaluate phase, independent of a reset of the input data; for each block, a completion detector circuit coupled to the output of the functional block, the completion detector circuit generating an acknowledgement signal that indicates validity or absence of data at the output of the block; and for each block, a precharge control circuit generating a precharge signal, wherein for a given block, a first input to the precharge control circuit comprises the acknowledgment signal from a downstream completion detector, and second input to the precharge control circuit comprises the precharge signal from an upstream precharge control circuit.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: March 8, 2016
    Assignee: RAYTHEON COMPANY
    Inventors: Harry Marr, Kenneth E. Prager, Julia Karl, Lloyd J. Lewins
  • Patent number: 9274751
    Abstract: A multiplier circuit comprises a fused Booth encoder multiplexer which produces partial product bits, a tree which uses the partial product bits to generate partial products, and an adder which uses the partial products to generate intermediate sum and carry results for a multiplication operation. The fused Booth encoder multiplexer utilizes encoder-selector cells having a logic tree which carries out a Boolean function according to a Booth encoding and selection algorithm to produce one of the partial product bits at a dynamic node, and a latch connected to the dynamic node which maintains the value at an output node. The encoder-selector cells operate in parallel to produce the partial product bits generally simultaneously. A given one of the encoder-selector cells has a unique set of both multiplier operand inputs and multiplicand operand inputs, and produces a single partial product bit.
    Type: Grant
    Filed: July 11, 2007
    Date of Patent: March 1, 2016
    Assignee: International Business Machines Corporation
    Inventors: Wendy Ann Belluomini, Hung Cai Ngo, Jun Sawada
  • Patent number: 9236114
    Abstract: In at least one embodiment, a sense amplifier circuit includes a bit line, a sense amplifier output, a keeper circuit, and a noise threshold control circuit. The keeper circuit is coupled to the bit line and includes an NMOS transistor coupled between a power node and the bit line. The keeper circuit is sized to supply sufficient current to compensate a leakage current of the bit line and configured to maintain a voltage level of the bit line. The noise threshold control circuit is connected to the sense amplifier output and the bit line. The noise threshold control circuit comprises an inverter.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: January 12, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Bharath Upputuri
  • Patent number: 9129685
    Abstract: A word-line driver includes first, second and third transistors. The first transistor includes a gate terminal driven by a first group selection signal, a first conduction terminal driven by a second sub-group selection signal and a second conduction terminal coupled to the word-line. The second transistor includes a gate terminal driven by a second group selection signal, a second conduction terminal driven by the second sub-group selection signal, and a first conduction terminal coupled to the word-line. The third transistor includes a gate terminal driven by a third the group selection signal, a first conduction terminal driven by a first sub-group selection signal, and a second conduction terminal coupled to the word-line.
    Type: Grant
    Filed: April 30, 2014
    Date of Patent: September 8, 2015
    Assignee: STMICROELECTRONICS INTERNATIONAL N.V.
    Inventor: Vikas Rana
  • Patent number: 9018981
    Abstract: A latch circuit includes a latch unit and a clock propagation suppressing unit. The latch circuit holds and outputs input data of 0 or 1. The clock propagation suppressing unit compares the input data input to the latch unit with output data output from the latch unit. When it is detected that the input data matches the output data at 0, or that the input data matches the output data at 1, an externally input clock signal is prevented from propagating to the latch unit.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: April 28, 2015
    Assignee: Fujitsu Limited
    Inventor: Katsunao Kanari
  • Patent number: 9000806
    Abstract: A device may include a latch activated during a second phase of a clock cycle; a clock gating component to control when a clock signal is to reach the latch; a destination storage element activated during a first phase of the clock cycle, where a logical path exists from the latch to the destination storage element; and a blocking element located in the logical path from the latch to the destination storage element, where the blocking element includes, as a first input, an output of the latch and, as a second input, an output of the clock gating component, and where the blocking element prevents an output value of the latch from changing when the clock gating component is not enabled and does not prevent the output value of the latch from changing when the clock gating element is enabled.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: April 7, 2015
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Dwight K. Elvey, Someshwar Gatty
  • Patent number: 8994405
    Abstract: A semiconductor integrated circuit device includes a first flip-flop circuit receiving data in synchronization with a first clock signal, a logic circuit performing a predetermined process on data output from the first flip-flop circuit, a hold buffer delaying transmission of an output of the logic circuit, a second flip-flop circuit receiving an output of the hold buffer in synchronization with a second clock signal, and a power supply circuit capable of selecting a supply of a power supply voltage to the first flip-flop circuit, the logic circuit, and the second flip-flop circuit between a first power supply voltage and a second power supply voltage higher than the first power supply voltage. A power supply voltage supplied to the hold buffer remains the same when the power supply voltage supplied to the first flip-flop circuit, the logic circuit, and the second flip-flop circuit changes between first and second power supply voltages.
    Type: Grant
    Filed: February 26, 2014
    Date of Patent: March 31, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Azuma Suzuki, Hiroyuki Hara
  • Patent number: 8994404
    Abstract: A 3D device, including: a first layer including first transistors, the first transistors interconnected by a first layer of interconnection; a second layer including second transistors, the second transistors overlaying the first layer of interconnection; the first layer includes a first clock distribution structure, the first clock distribution structure includes a first clock origin, the second layer includes a second clock distribution structure, the second clock distribution structure includes a second clock origin, and the second clock origin is feeding the first clock origin.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: March 31, 2015
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Zeev Wurman
  • Publication number: 20150070050
    Abstract: A semiconductor integrated circuit device includes a first flip-flop circuit receiving data in synchronization with a first clock signal, a logic circuit performing a predetermined process on data output from the first flip-flop circuit, a hold buffer delaying transmission of an output of the logic circuit, a second flip-flop circuit receiving an output of the hold buffer in synchronization with a second clock signal, and a power supply circuit capable of selecting a supply of a power supply voltage to the first flip-flop circuit, the logic circuit, and the second flip-flop circuit between a first power supply voltage and a second power supply voltage higher than the first power supply voltage. A power supply voltage supplied to the hold buffer remains the same when the power supply voltage supplied to the first flip-flop circuit, the logic circuit, and the second flip-flop circuit changes between first and second power supply voltages.
    Type: Application
    Filed: February 26, 2014
    Publication date: March 12, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Azuma SUZUKI, Hiroyuki HARA
  • Patent number: 8957718
    Abstract: A flip-flop circuit has a master latch circuit and a slave latch circuit. In the flip-flop circuit, the master latch circuit and the slave latch circuit share at least a pair of transistors. In response to the clock signal, the signal held in the master latch circuit can be output at higher speed as the output signal via the intermediate node, the slave latch circuit and the output circuit. The flip-flop circuit can be reduced in cell size and improved in processing speed.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: February 17, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Muneaki Maeno
  • Patent number: 8928377
    Abstract: A scannable fast dynamic register including a data and scan enable circuit, a precharge circuit, a select circuit, a store circuit, and a scan input enable circuit. The data and scan enable circuit pulls a first precharge node to a discharge node in response to the clock upon evaluation in normal mode. The precharge circuit precharges first and second precharge nodes high, in which one of the precharged nodes discharges depending upon whether a data block evaluates. The store circuit and an output gate are responsive to the second precharge node to provide the output. The select circuit is interposed before the store circuit to allow injection of scan data in a scan mode. In scan mode, the scan input enable circuit provides scan data to the select and store circuits. The scan input enable circuit also includes a store circuit which operates with the first store circuit in a master-slave configuration.
    Type: Grant
    Filed: July 25, 2013
    Date of Patent: January 6, 2015
    Assignee: VIA Technologies, Inc.
    Inventor: Imran Qureshi
  • Patent number: 8928354
    Abstract: A clock-delayed domino logic circuit includes a precharge circuit configured to control connection between a first node and a dynamic node in response to a clock signal, an evaluation circuit configured to control connection between a second node and an evaluation node in response to the clock signal, a logic network connected between the dynamic node and the evaluation node, the logic network configured to determine a logic level of the dynamic node based on a plurality of input signals, and a phase control circuit configured to output a logic level of the evaluation node or a logic level of the first node according to a level of the clock signal.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: January 6, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Min Su Kim
  • Patent number: 8907701
    Abstract: The present invention discloses a CMOS differential logic circuit. The CMOS differential logic circuit includes a precharge differential logic unit, which is precharged to a source voltage in response to a clock signal and is configured to output voltage having an increased load-driving ability using a boosting voltage; a voltage-boosting unit, which is pulled down by a ground voltage in response to the clock signal and is configured to boost the pulled-down voltage using capacitive coupling and output the boosting voltage; and a switching unit, which is configured to couple the precharge differential logic unit and the voltage-boosting unit in response to the clock signal. The propagation delay of a signal from the input terminal to the output terminal of a circuit in a low-source-voltage environment can be reduced, and the operating speed of the circuit and energy efficiency of the operation thereof can be improved.
    Type: Grant
    Filed: February 19, 2013
    Date of Patent: December 9, 2014
    Assignee: Research & Business Foundation Sungkyunkwan University
    Inventors: Bai Sun Kong, Jong Woo Kim, Joo Seong Kim
  • Patent number: 8907700
    Abstract: A clock-delayed domino logic circuit includes a first pre-charge circuit configured to pre-charge a first dynamic node with a pre-charge voltage in response to a first clock signal received via a first control terminal during a pre-charge operation; a first logic network configured to determine a logic level of the first dynamic node in response to first input data signals during an evaluation operation; and a first storage circuit which is connected between the first control terminal and the first dynamic node.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: December 9, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Rahul Singh, Hyoung Wook Lee
  • Patent number: 8890573
    Abstract: A clock gating latch, a method of gating a clock signal and an integrating circuit incorporating the clock gating latch or the method. In one embodiment, the clock gating latch includes: (1) a propagation circuit having a single, first switch configured to be driven by an input clock signal, (2) a keeper circuit coupled to the propagation circuit and having a single, first switch configured to be driven by the input clock signal and (3) an AND gate coupled to the propagation circuit and the keeper circuit and having an internal node coupled to a second switch in the propagation circuit and a second switch in the keeper circuit.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: November 18, 2014
    Assignee: Nvidia Corporation
    Inventors: Ilyas Elkin, Ge Yang, Jonah Alben
  • Publication number: 20140292374
    Abstract: A method for controlling an IC having logic cells and a clock-tree cell. Each logic cell has first and second FETs, which are pMOS and nMOS respectively. The clock-tree cell includes third and fourth FETs, which are pMOS and nMOS respectively. The clock-tree cell provides a clock signal to the logic cells. A back gate potential difference (“BGPD”) of a pMOS-FET is a difference between its source potential less its back-gate potential, and vice versa for an nMOS-FET. The method includes applying first and second back gate potential difference (BGPD) to a logic cell's first and second FETs and either applying a third BGPD to a third FET, wherein the third BGPD is positive and greater than the first BGPD applied, which is applied concurrently, or applying a fourth BGEPD to a fourth FET, wherein the fourth BGPD is positive and greater than the second BGPD that is applied concurrently.
    Type: Application
    Filed: March 26, 2014
    Publication date: October 2, 2014
    Inventors: Bastien Giraud, Fady Abouzeid, Sylvain Clerc, Jean-Philippe Noel, Philippe Roche, Yvain Thonnart
  • Patent number: 8836369
    Abstract: A latch circuit switches a differential operation performed by a differential operation circuit including a first logic circuit, a second logic circuit, a third logic circuit, and a fourth logic circuit and a single end operation performed by a single end operation circuit according to a logic level of an inputted selection signal. The latch circuit performs an operation to output an input signal and an inverted input signal without change from a first output terminal and a second output terminal of the latch circuit, respectively, and an operation to set the input signal and the inverted input signal in a hold state in the differential operation and performs an operation to output the input signal from the first output terminal without change and an operation to set the input signal in a hold state in the single end operation, according to a clock signal and an inverted clock signal.
    Type: Grant
    Filed: October 3, 2012
    Date of Patent: September 16, 2014
    Assignee: Fujitsu Limited
    Inventors: Yuuki Ogata, Yoichi Koyanagi
  • Publication number: 20140225645
    Abstract: A tuneable buffer circuit for use in a clock tree has multiple buffers in parallel, each buffer having a grounding function, and also a bypass switch in parallel with the buffers. The circuit has a normal mode of one buffer connected into circuit, a first low voltage mode of multiple buffers connected into circuit in parallel without grounding function, a second low voltage mode of the buffers connected into circuit in parallel with grounding function and a bypass mode.
    Type: Application
    Filed: January 30, 2014
    Publication date: August 14, 2014
    Applicant: NXP B.V.
    Inventors: Vibhu SHARMA, Rinze Ida Mechtildis Pete MEIJER, Jose Pineda de Gyvez
  • Patent number: 8791720
    Abstract: A control circuit comprises a first NOR gate, a first NMOS transistor, and a first PMOS transistor. The control circuit also comprises an output node. The control circuit further comprises a half latch keeper circuit coupled to a gate of the first NMOS transistor and to a gate of the first PMOS transistor. The half latch keeper circuit is configured to keep the output node at a logical 1 during a standby mode. The control circuit additionally comprises an operational PMOS transistor coupled to the output node. An output of the first NOR gate is coupled to a gate of the operational PMOS transistor. The control circuit is configured to turn off the operational PMOS transistor during the standby mode.
    Type: Grant
    Filed: October 3, 2013
    Date of Patent: July 29, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chan-Hong Chern, Fu-Lung Hsueh, Ming-Chieh Huang, Bryan Sheffield, Chih-Chang Lin
  • Patent number: 8786345
    Abstract: One embodiment of the present invention sets forth a technique for capturing and storing a level of an input signal using a single-trigger low-energy flip-flop circuit that is fully-static and insensitive to fabrication process variations, The single-trigger low-energy flip-flop circuit presents only three transistor gate loads to the clock signal and none of the internal nodes toggle when the input signal remains constant, The output signal Q is set or reset at the rising clock edge using a single- trigger sub-circuit. A set or reset may be armed while the clock signal is low, and the set or reset is triggered at the rising edge of the clock.
    Type: Grant
    Filed: March 28, 2013
    Date of Patent: July 22, 2014
    Assignee: NVIDIA Corporation
    Inventors: Jonah M. Alben, William J. Dally
  • Patent number: 8779798
    Abstract: In order to reduce power consumption, an arithmetic circuit having a function of performing a logic operation processing based on an input signal, storing a potential set in accordance with the result of the logic operation processing as stored data, and outputting a signal with a value corresponding to the stored data as an output signal. The arithmetic circuit includes an arithmetic portion performing the logic operation processing, a first field-effect transistor controlling whether a first potential, which is the potential corresponding to the result of the logic operation processing is set, and a second field-effect transistor controlling whether the potential of the output signal data is set at a second potential which is a reference potential.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: July 15, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Kiyoshi Kato
  • Patent number: 8730215
    Abstract: The present invention provides a data latch circuit which can operate stably with a low-amplitude signal, which consumes less electric power, and which is resistant against the variation in TFTs. When an analog switch is turned on, a data signal is inputted to a gate electrode of an n-channel TFT and, at this time, VDD is supplied to an input terminal of an inverter. When the analog switch in turned off, the n-channel TFT is turned on or off depending on a level of the data signal. When the data signal is at an H level, the n-channel TFT is turned on and VSS is supplied to the input terminal of the inverter. When the data signal is at an L level, VDD is supplied to an input terminal of the inverter. Therefore, only VDD and VSS levels are applied to the input terminal of the inverter.
    Type: Grant
    Filed: March 23, 2011
    Date of Patent: May 20, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Mitsuaki Osame, Tatsuo Ueno
  • Patent number: 8692579
    Abstract: In order to reduce power consumption, an arithmetic circuit having a function of performing a logic operation processing based on an input signal, storing a potential set in accordance with the result of the logic operation processing as stored data, and outputting a signal with a value corresponding to the stored data as an output signal. The arithmetic circuit includes an arithmetic portion performing the logic operation processing, a first field-effect transistor controlling whether a first potential, which is the potential corresponding to the result of the logic operation processing is set, and a second field-effect transistor controlling whether the potential of the output signal data is set at a second potential which is a reference potential.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: April 8, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Kiyoshi Kato
  • Publication number: 20140070847
    Abstract: A clock gating latch, a method of gating a clock signal and an integrating circuit incorporating the clock gating latch or the method. In one embodiment, the clock gating latch includes: (1) a propagation circuit having a single, first switch configured to be driven by an input clock signal, (2) a keeper circuit coupled to the propagation circuit and having a single, first switch configured to be driven by the input clock signal and (3) an AND gate coupled to the propagation circuit and the keeper circuit and having an internal node coupled to a second switch in the propagation circuit and a second switch in the keeper circuit.
    Type: Application
    Filed: September 7, 2012
    Publication date: March 13, 2014
    Applicant: Nvidia Corporation
    Inventors: Ilyas Elkin, Ge Yang, Jonah Alben
  • Patent number: 8659320
    Abstract: A digital logic gate suitable for a high-speed operation of a central processing unit. The digital logic gate comprises the first dynamic logic gate configured to logically gate a plurality of first input data in response to the first clock signal, a second dynamic logic gate configured to logically gate a gating output of the first dynamic logic gate and a plurality of second input data, and a latching device configured to latch a gating output of the second dynamic logic gate. The digital logic circuit need not adopt a keeper circuit, and thus a gate delay is reduced and the digital logic circuit performs a high-speed gating operation with robust characteristic against a current leakage or an input noise.
    Type: Grant
    Filed: October 21, 2011
    Date of Patent: February 25, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Hyoungwook Lee
  • Patent number: 8610461
    Abstract: An apparatus having a first circuit and a second circuit. The first circuit may be configured to generate an output signal in response to (i) an intermediate signal, and (ii) a clock signal. The second circuit may be configured to generate the intermediate signal and a digital complement of the output signal in response to (i) an input signal and (ii) the clock signal. The intermediate signal may form a feedback to ensure the output signal and the digital complement of the output signal are in complementary states during a power up.
    Type: Grant
    Filed: September 28, 2011
    Date of Patent: December 17, 2013
    Assignee: LSI Corporation
    Inventors: Richard J. Stephani, Amy R. Rittenhouse, Donald A. Evans
  • Patent number: 8604855
    Abstract: One embodiment of the present invention sets forth a technique for technique for capturing and storing a level of an input signal using a dual-trigger low-energy flip-flop circuit that is fully-static and insensitive to fabrication process variations. The dual-trigger low-energy flip-flop circuit presents only three transistor gate loads to the clock signal and none of the internal nodes toggle when the input signal remains constant. One of the clock signals may be a low-frequency “keeper clock” that toggles less frequently than the other two clock signal that is input to two transistor gates. The output signal Q is set or reset at the rising clock edge using separate trigger sub-circuits. Either the set or reset may be armed while the clock signal is low, and the set or reset is triggered at the rising edge of the clock.
    Type: Grant
    Filed: June 18, 2013
    Date of Patent: December 10, 2013
    Assignee: NVIDIA Corporation
    Inventors: William J. Dally, Jonah M. Alben, John W. Poulton, Ge Yang
  • Patent number: 8575965
    Abstract: An internal clock gating apparatus comprises a static logic block and a domino logic block. The static logic block is configured to receive a clock signal and a clock enable signal. The domino logic block is configured to receive the clock signal and a control signal from an output of the static logic block. The static logic block and the domino logic block are further configured such that an output of the domino logic block generates a signal similar to the clock signal in phase when the clock enable signal has a logic high state. On the other hand, the output of the domino logic block generates a logic low signal when the clock enable signal has a logic low state. Furthermore, the static logic block and the domino logic block can reduce the setup time and delay time of the internal clock gating apparatus respectively.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: November 5, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Lin Liu, Chung-Cheng Chou, Yangsyu Lin, Hsiao Wen Lu
  • Patent number: 8570068
    Abstract: A circuit includes an operational PMOS transistor of a logic gate driver. A control circuit is configured to turn off the operational PMOS transistor during a standby mode. The circuit also includes a sacrificial PMOS transistor coupled to an output node. The operational PMOS transistor is coupled to the output node. The sacrificial PMOS transistor is configured to keep the output node at a logical 1 during the standby mode.
    Type: Grant
    Filed: April 28, 2010
    Date of Patent: October 29, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chan-Hong Chern, Fu-Lung Hsueh, Ming-Chieh Huang, Bryan Sheffield, Chih-Chang Lin
  • Patent number: 8564331
    Abstract: A semiconductor device in which an input terminal is electrically connected to a first terminal of a first transmission gate; a second terminal of the first transmission gate is electrically connected to a first terminal of a first inverter and a second terminal of a functional circuit; a second terminal of the first inverter and a first terminal of the functional circuit are electrically connected to a first terminal of a second transmission gate; a second terminal of the second transmission gate is electrically connected to a first terminal of a second inverter and a second terminal of a clocked inverter; a second terminal of the second inverter and a first terminal of the clocked inverter are electrically connected to an output terminal; and the functional circuit includes a data holding portion between a transistor with small off-state current and a capacitor.
    Type: Grant
    Filed: May 2, 2012
    Date of Patent: October 22, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Seiichi Yoneda
  • Patent number: 8552761
    Abstract: A flip-flop includes a transmission circuit configured to transmit data to a transmission line in response to a clock signal and a complementary clock signal. The flip-flop further includes a keeper circuit configured to latch data of the transmission line in response to the clock signal and the complementary clock signal to maintain the data of the transmission line constant.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: October 8, 2013
    Assignee: SAMSUNG Electronics Co., Ltd.
    Inventor: Min Su Kim
  • Publication number: 20130257480
    Abstract: A clock-delayed domino logic circuit includes a precharge circuit configured to control connection between a first node and a dynamic node in response to a clock signal, an evaluation circuit configured to control connection between a second node and an evaluation node in response to the clock signal, a logic network connected between the dynamic node and the evaluation node, the logic network configured to determine a logic level of the dynamic node based on a plurality of input signals, and a phase control circuit configured to output a logic level of the evaluation node or a logic level of the first node according to a level of the clock signal.
    Type: Application
    Filed: December 21, 2012
    Publication date: October 3, 2013
    Applicant: Samsung Electronics Co., Ltd.
    Inventor: Min Su KIM
  • Patent number: 8542033
    Abstract: A domino logic circuit includes a first evaluation unit, a second evaluation unit and an output unit. The first evaluation unit precharges a first dynamic node, discharges a footer node in a first phase of a clock signal, and evaluates a plurality of input signals to determine a logic level of the first dynamic node in a second phase of the clock signal. The second evaluation unit precharges a second dynamic node in the first phase of the clock signal, and determines a logic level of the second dynamic node in response to a logic level of the footer node in the second phase of the clock signal. The output unit provides an output signal having a logic level according to levels of a first voltage of the first dynamic node and a second voltage of the second dynamic node.
    Type: Grant
    Filed: September 16, 2011
    Date of Patent: September 24, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyoung-Wook Lee, Gun-Ok Jung, Suhwan Kim, Ah-Reum Kim, Rahul Singh
  • Publication number: 20130246819
    Abstract: A domino logic circuit includes a pre-charge circuit pre-charging a first dynamic node in response to a clock signal, a first logic network determining a logic level of the first dynamic node in response to first data signals, an inverter receiving the clock signal, a discharge circuit discharging a second dynamic node in response to an output signal of the inverter, and a second logic network determining a logic level of the second dynamic node in response to at least one second data signal and an output signal of the first dynamic node.
    Type: Application
    Filed: March 12, 2013
    Publication date: September 19, 2013
    Inventors: Ken Keon Shin, Hoi Jin Lee, Gun Ok Jung, Min Su Kim
  • Publication number: 20130246834
    Abstract: A domino logic circuit includes a plurality of domino logic stages connected in series between a latch and a flip-flop and a clock signal generator generating a clock signal having a first duty cycle and a flip-flop clock signal having a second duty cycle. The latch and the domino logic stages respectively operate in response to a domino clock signals derived from the first clock signal. The flip-flop operates in response to the flip-flop clock signal.
    Type: Application
    Filed: December 28, 2012
    Publication date: September 19, 2013
    Inventors: Ken Keon Shim, Hoi Jin Lee, Gun Ok Jung