Mosfet Patents (Class 326/98)
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Patent number: 12021522Abstract: Apparatus and associated methods relate to quasi-adiabatic logic gates in which at least one supply terminal receives a periodic power signal. The quasi-adiabatic logic gate is configured to perform a specific logic function operative upon one or more input signals. When the quasi-adiabatic logic gate switches the output from one logic state to another logic state, the transient switching portion of the output signal substantially tracks the periodic supply signal. Such a periodic supply signal can be one that transitions gradually between low and high voltage levels. Such periodic supply signals results in a transient switching portion of the logic signal having lower frequency components than have traditional CMOS logic gate transients. The quasi-adiabatic logic gate has a periodic clock signal that is not in phase with the periodic power signal.Type: GrantFiled: December 20, 2021Date of Patent: June 25, 2024Assignee: TACHO HOLDINGS, LLCInventors: Tommy Allen Agan, James John Lupino
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Patent number: 11876517Abstract: An electrical circuit includes a driver circuit, a receiver circuit, and a keeper circuit. The receiver circuit receives an input pulse from the driver circuit during a pre-charge phase. The receiver circuit generates an output pulse based on the input pulse during an evaluation phase. The keeper circuit maintains a charge of the output pulse until another evaluation phase, wherein the keeper circuit is adapted to the driver circuit by gating a first voltage supply of the driver circuit with a second voltage supply of the keeper circuit.Type: GrantFiled: February 11, 2022Date of Patent: January 16, 2024Assignee: International Business Machines CorporationInventors: Israel A. Wagner, Elazar (Eli) Kachir
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Patent number: 11822705Abstract: An apparatus for masking power consumption associated with one or more operations of a logic circuitry of a processor. The apparatus comprises power-complementing circuitry configured to provide a second power consumption to directly power-complementing the power consumption associated with the one or more operations of the logic circuitry. The second power consumption complements the power consumption associated with the one or more operations of the logic circuitry. The apparatus further comprises header circuitry configured to enable a common node to vary in voltage corresponding to the one or more operations of the logic circuitry. The power-complementing circuitry and the header circuitry are each coupled to the logic circuitry at the common node.Type: GrantFiled: November 29, 2021Date of Patent: November 21, 2023Assignee: Arm LimitedInventors: Bal S. Sandhu, George McNeil Lattimore, Carl Wayne Vineyard
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Patent number: 11705167Abstract: A memory circuit includes a pre-charging circuit and a control circuit. The pre-charging circuit includes a first pre-charging unit, a second pre-charging unit, a first power supply terminal, a second power supply terminal, a first control terminal, a second control terminal and a data terminal; the first pre-charging unit is connected with the first power supply terminal, the first control terminal and the data terminal; the second pre-charging unit is connected with the second power supply terminal, the second control terminal and the data terminal. The control circuit is configured to in response to a memory being in a row active state and not performing a reading-writing operation, control, through the second pre-charging unit, the data terminal and the second power supply terminal to be disconnected, and control, through the first pre-charging unit, the data terminal and the first power supply terminal to be disconnected.Type: GrantFiled: September 9, 2021Date of Patent: July 18, 2023Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Liang Zhang
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Patent number: 11700000Abstract: A CAN bus transmitter has an input to receive a transmit data signal, and CANH and CANL outputs coupled to a CAN bus. The CAN bus transmitter comprises a plurality of CAN driver circuits having inputs coupled through delay circuits with their CANH and CANL outputs in common and connected to the CAN bus. Matching of Cgs capacitances between devices of the CANH and CANL legs provides substantially synchronized changes in the CANH and CANL output logic levels upon a change in the input logic level. Variable delaying of the input logic level changes to each of the plurality of CAN driver circuits reduces emission of unwanted signals from the CAN bus.Type: GrantFiled: January 11, 2022Date of Patent: July 11, 2023Assignee: Microchip Technology IncorporatedInventor: Wolfgang Roeper
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Patent number: 11637552Abstract: A speed-up circuit is configured to be provided between a power supply terminal and a gate of a semiconductor switching element. An impedance element is configured to be provided between a signal input terminal and a node, the node being between the speed-up circuit and the gate of the semiconductor switching element. In the speed-up circuit, a second field effect transistor is connected in series to a first field effect transistor and is configured to be connected to the gate of the semiconductor switching element. The impedance element has an impedance higher than an impedance of the speed-up circuit when both the first field effect transistor and the second field effect transistor are in an ON state.Type: GrantFiled: April 28, 2020Date of Patent: April 25, 2023Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Yusuke Kinoshita, Takashi Ichiryu, Ryusuke Kanomata, Hidetoshi Ishida
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Patent number: 11590860Abstract: An automotive control module includes a microcontroller having an access port, and that permits reprogramming of its functions responsive to a voltage at the access port being greater than a first predefined threshold upon power-up or reset thereof. The automotive control module also includes a boot assist control circuit lacking logical elements and including a pair of input ports, an output port directly electrically connected to the access port, and a plurality of capacitors, resistors, and transistors electrically connected between the pair and output port. The plurality outputs a voltage to the output port at least equal to the first predefined threshold responsive to voltages at both the input ports being greater than a second predefined threshold, and outputs a voltage to the output port less than the first predefined threshold responsive to the voltage at either one of the input ports being less than the second predefined threshold.Type: GrantFiled: May 18, 2020Date of Patent: February 28, 2023Assignee: FORD GLOBAL TECHNOLOGIES, LLCInventor: Thomas Joseph Wand
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Patent number: 11533052Abstract: According to a certain embodiment, the semiconductor device includes a circuit block and a clock circuit configured to supply a clock signal to the circuit block at a specific timing. The clock circuit includes an output circuit configured to provide the clock signal to the circuit block, and a control circuit configured to control the timing at which the output circuit provides the clock signal. A threshold voltage of at least a transistor in the output circuit using the clock signal as input/output signals is a first threshold voltage, and a threshold voltage of a transistor configuring the control circuit is a second threshold voltage higher than the first threshold voltage.Type: GrantFiled: March 2, 2021Date of Patent: December 20, 2022Assignee: Kioxia CorporationInventor: Koji Kohara
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Patent number: 11509295Abstract: A flip flop includes a master latch and a slave latch. The master latch includes a delay circuit configured to receive a clock signal and generate a first internal signal, and is configured to generate an internal output signal by latching a data signal based on the first internal signal. The slave latch is configured to generate a final signal by latching the internal output signal. The delay circuit is further configured to generate the first internal signal by delaying the clock signal by a delay time when the clock signal has a first logic level and generate the first internal signal based on the data signal when the clock signal has a second logic level.Type: GrantFiled: June 7, 2021Date of Patent: November 22, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Byounggon Kang, Changbeom Kim, Dalhee Lee, Wookyu Kim
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Patent number: 11296118Abstract: Reduction in power consumption of a semiconductor device is achieved. The semiconductor device includes: a first circuit operating at a first power supply voltage and a second circuit operating at a second power supply voltage and including a level shift unit and a switch unit, the first circuit is configured of a low-breakdown-voltage n-type transistor that is an SOTB transistor, and the switch unit is configured of an n-type transistor that is an SOTB transistor. A second power supply voltage is higher than a first power supply voltage, and an impurity concentration of a channel formation region of the n-type transistor is higher than an impurity concentration of a channel formation region of the low-breakdown-voltage n-type transistor.Type: GrantFiled: December 22, 2020Date of Patent: April 5, 2022Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Kazuya Uejima, Kazuhiro Koudate
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Patent number: 11196421Abstract: Provided is a logic circuit comprising: a switch portion that includes one or more switching devices configured to be turned on and off in accordance with an input signal and is configured to generate an output signal with a logical value according to an operating state of the switching devices; and a clamp portion configured to clamp a voltage of the output signal, of a case where the logical value of the output signal is logic H. The switch portion may be arranged between an output line and a reference potential line, and the clamp portion may be arranged in parallel with the switch portion, between the output line and the reference potential line. The logic circuit may include a current suppression portion configured to suppress a current flowing through the clamp portion, when the logical value of the output signal is logic H.Type: GrantFiled: September 27, 2020Date of Patent: December 7, 2021Assignee: FUJI ELECTRIC CO., LTD.Inventor: Motomitsu Iwamoto
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Patent number: 10879271Abstract: Reduction in power consumption of a semiconductor device is achieved. The semiconductor device includes: a first circuit operating at a first power supply voltage and a second circuit operating at a second power supply voltage and including a level shift unit and a switch unit, the first circuit is configured of a low-breakdown-voltage n-type transistor that is an SOTB transistor, and the switch unit is configured of an n-type transistor that is an SOTB transistor. A second power supply voltage is higher than a first power supply voltage, and an impurity concentration of a channel formation region of the n-type transistor is higher than an impurity concentration of a channel formation region of the low-breakdown-voltage n-type transistor.Type: GrantFiled: March 22, 2019Date of Patent: December 29, 2020Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Kazuya Uejima, Kazuhiro Koudate
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Patent number: 10848153Abstract: Methods, systems, and devices for leakage current reduction in electronic devices are described. Electronic devices may be susceptible to leakage currents when operating in a first mode, such as an inactive (e.g., a standby) mode. To mitigate leakage current, an electronic device may include transistors coupled in cascode configuration where a gate of a drain-side transistor in the cascode configuration is configured to be biased by an adjustable (e.g., a dynamic) control signal. When the transistors are inactive (e.g., “off”), the control signal may be adjusted to prevent leakage associated with the inactive transistors. Further, a source-side transistor in the cascode configuration may be configured to have a high threshold voltage (e.g., relative to the drain-side transistor).Type: GrantFiled: November 30, 2018Date of Patent: November 24, 2020Assignee: Micron Technology, Inc.Inventors: Hiroshi Akamatsu, Ki-Jun Nam, John David Porter
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Patent number: 10754809Abstract: By shutting off keeper transistors during pre-charge, the aging on these devices may be reduced. This means that a relatively weaker keeper may be used for noise compared to an overdesigned stronger keeper. Using a relatively weaker keeper circuit results in a faster evaluation stage and improved minimum read voltage in some embodiments.Type: GrantFiled: March 15, 2019Date of Patent: August 25, 2020Assignee: Intel CorporationInventors: Anupama A. Thaploo, Bhushan M. Borole, Bee Ngo, Iqbal R. Rajwani, Altug Koker, Abhishek R. Appu, Kamal Sinha, Wenyin Fu
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Patent number: 10651164Abstract: A system and method for creating layout for non-planar cells with redundancy in one or more of output contacts and power contacts are described. In various implementations, cell layout is created for a first cell with non-planar devices. An available local path in the first cell is identified for redundant output signal routing, which includes a free available metal zero layer track. Redundant metal zero layer is placed in an available metal zero track of the available local path. Redundant contacts and redundant metal one layer are placed in a free track in the available local path to connect an original output contact to a redundant output contact. An available external path is identified between the first cell and a second cell for redundant power or ground routing. One or more metal zero extension layers and/or metal one extension layers are placed in the identified external path.Type: GrantFiled: October 2, 2019Date of Patent: May 12, 2020Assignee: Advanced Micro Devices, Inc.Inventor: Richard T. Schultz
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Patent number: 10515670Abstract: A memory apparatus and a voltage control method of the memory apparatus are provided. The memory apparatus of the invention includes a synchronous circuit, a clock tree and a memory controller. The synchronous circuit receives a reference clock and generating a clock signal. The clock tree is coupled to an output end of the multiplexer and assigns the clock signal to a plurality of signal paths. The memory controller is coupled to the synchronous circuit and controls the synchronous circuit to adjust a frequency of the clock signal according to an operating mode of the memory apparatus.Type: GrantFiled: June 13, 2018Date of Patent: December 24, 2019Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Wen-Ming Lee, Chuan-Jen Chang
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Patent number: 10466968Abstract: A system including a series of partial product select encoders and partial product muxes, each of the partial product select encoders receiving a multiplier, receiving a carry input from a multiplier tree, and outputting a select signal to an associated partial product mux based on the multiplier and carry input, and each of the partial product muxes outputting a partial product based on the select signal and a multiplicand received.Type: GrantFiled: July 12, 2018Date of Patent: November 5, 2019Assignee: NVIDIA Corp.Inventor: Ilyas Elkin
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Patent number: 10438937Abstract: A system and method for creating layout for non-planar cells with redundancy in one or more of output contacts and power contacts are described. In various implementations, cell layout is created for a first cell with non-planar devices. An available local path in the first cell is identified for redundant output signal routing, which includes a free available metal zero layer track. Redundant metal zero layer is placed in an available metal zero track of the available local path. Redundant contacts and redundant metal one layer are placed in a free track in the available local path to connect an original output contact to a redundant output contact. An available external path is identified between the first cell and a second cell for redundant power or ground routing. One or more metal zero extension layers and/or metal one extension layers are placed in the identified external path.Type: GrantFiled: April 27, 2018Date of Patent: October 8, 2019Assignee: Advanced Micro Devices, Inc.Inventor: Richard T. Schultz
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Patent number: 10324721Abstract: By shutting off keeper transistors during pre-charge, the aging on these devices may be reduced. This means that a relatively weaker keeper may be used for noise compared to an overdesigned stronger keeper. Using a relatively weaker keeper circuit results in a faster evaluation stage and improved minimum read voltage in some embodiments.Type: GrantFiled: April 17, 2017Date of Patent: June 18, 2019Assignee: Intel CorporationInventors: Anupama A. Thaploo, Bhushan M. Borole, Bee Ngo, Iqbal R. Rajwani, Altug Koker, Abhishek R. Appu, Kamal Sinha, Wenyin Fu
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Patent number: 10269419Abstract: Described is an apparatus which comprises: a memory bit-cell; a local bit-line (LBL) coupled to the memory bit-cell via a read port device; a NAND gate circuitry coupled to the LBL; and a stack of keepers coupled to the LBL, wherein at least one transistor of the stack of keepers is controllable according to an output of the NAND gate circuitry, wherein the stack of keepers includes transistors with variable strength which are to be turned on overtime.Type: GrantFiled: May 24, 2017Date of Patent: April 23, 2019Assignee: Intel CorporationInventors: Jaydeep P. Kulkarni, Vivek K. De, Muhammad M. Khellah
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Patent number: 10164773Abstract: Described is an apparatus comprising precharge paths including first clocked transistors having gates coupled to a clock signal path, first terminals coupled to a first power rail, and second terminals coupled to one or more first junction nodes. The precharge paths lack a keeper circuitry, have a configurable keeper circuitry, and/or have cross-coupled keeper circuitry to eliminate/reduce keeper contention during domino logic evaluation. The apparatus may comprise second clocked transistors having gates coupled to the clock signal path, first terminals coupled to one or more second junction nodes, and second terminals coupled to a second power rail. The apparatus may comprise sets of evaluation transistors having conducting channels coupled in series, coupled to the one or more first junction nodes, and coupled to one of the one or more second junction nodes. A NAND or inverter circuitry with inputs is coupled to the one or more first junction nodes.Type: GrantFiled: September 30, 2016Date of Patent: December 25, 2018Assignee: Intel CorporationInventors: Vikram B. Suresh, Sanu K. Mathew, Sudhir K. Satpathy
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Patent number: 10090333Abstract: In order to reduce power consumption, an arithmetic circuit having a function of performing a logic operation processing based on an input signal, storing a potential set in accordance with the result of the logic operation processing as stored data, and outputting a signal with a value corresponding to the stored data as an output signal. The arithmetic circuit includes an arithmetic portion performing the logic operation processing, a first field-effect transistor controlling whether a first potential, which is the potential corresponding to the result of the logic operation processing is set, and a second field-effect transistor controlling whether the potential of the output signal data is set at a second potential which is a reference potential.Type: GrantFiled: June 6, 2014Date of Patent: October 2, 2018Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Kiyoshi Kato
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Patent number: 10056882Abstract: At least some embodiments are directed to a flip-flop that comprises a tri-state inverter and a master latch coupled to the tri-state inverter and comprising a first transistor, a first inverter, and a first logic gate. The master latch receives a clock signal. The flop also comprises a slave latch coupled to the master latch and comprising a second transistor and a second inverter. The slave latch receives the clock signal. The flop further comprises an enablement logic coupled to the master latch and comprising multiple, additional logic gates. The tri-state inverter, the master and slave latches, and the enablement logic are configured so that when a flip-flop input signal D and a flip-flop output signal Q are identical and the clock signal is toggled, a state of the master latch and a state of the slave latch remain static.Type: GrantFiled: December 27, 2016Date of Patent: August 21, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Suvam Nandi, Badarish Mohan Subbannavar
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Patent number: 10027325Abstract: A circuit coupled to receive an input voltage that can span a wide voltage supply range and a voltage translator that includes the circuit are disclosed. The circuit includes a first metal oxide silicon (MOS) transistor having a first conductivity type and a first threshold voltage and a second MOS transistor having the first conductivity type and a second threshold voltage that is lower than the first threshold voltage. The first MOS transistor is coupled in parallel with the second MOS transistor between a first rail and a first signal line; the first MOS transistor and the second MOS transistor each receive a first signal on a respective gate.Type: GrantFiled: June 28, 2017Date of Patent: July 17, 2018Assignee: Texas Instruments IncorporatedInventor: Christopher Michael Graves
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Patent number: 9940992Abstract: Leakage-aware activation control of a delayed keeper circuit for a dynamic read operation in a memory bit cell is disclosed. In one aspect, a leakage-aware activation control circuit is provided for a dynamic read circuit configured to perform read operations on a memory bit cell. To prevent or mitigate contention between the delayed keeper circuit and a read port circuit in the dynamic read circuit pulling a dynamic node to opposite voltage levels when a read operation is initiated, the leakage-aware activation control circuit is configured to adaptively control activation timing of the delayed keeper circuit based on a comparison of N-type Field-Effect Transistor (NFET) leakage current to P-type FET (PFET) leakage current. In this manner, the leakage-aware activation control circuit can adaptively adjust the activation timing of the delayed keeper circuit based on the actual relative strengths of NFETs and PFETs.Type: GrantFiled: March 30, 2016Date of Patent: April 10, 2018Assignee: QUALCOMM IncorporatedInventors: Francois Ibrahim Atallah, Hoan Huu Nguyen, Keith Alan Bowman
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Patent number: 9437555Abstract: It is desirable to design and manufacture electronic chips that are resistant to modern reverse engineering techniques. Disclosed is a method and device that allows for the design of chips that are difficult to reverse engineer using modern teardown techniques. The disclosed device uses devices having the same geometry but different voltage levels to create different logic devices. Alternatively, the disclosed uses devices having different geometries and the same operating characteristics. Also disclosed is a method of designing a chip using these devices.Type: GrantFiled: October 2, 2014Date of Patent: September 6, 2016Assignee: Verisiti, Inc.Inventor: William Eli Thacker, III
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Patent number: 9374075Abstract: An input apparatus may include a pulse width control circuit, a reception circuit, and a latch circuit. The pulse width control circuit may be configured to generate a pulse width control signal by performing a logical operation on a pulse width detection signal and a clock signal. The reception circuit may be configured to selectively provide a received input signal as a period signal on the basis of the clock signal and the pulse width control signal. The latch circuit may be configured to provide an output signal by inverting the period signal, and provide the output signal as the pulse width detection signal in response to the clock signal.Type: GrantFiled: December 30, 2014Date of Patent: June 21, 2016Assignee: SK hynix Inc.Inventor: Nohhyup Kwak
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Patent number: 9349849Abstract: In a semiconductor device including a transistor, an oxygen release type oxide insulating film is formed in contact with a channel formation region of the transistor. The channel formation region is formed in an oxide semiconductor film. Oxygen is supplied from the oxide insulating film to the oxide semiconductor film. Further, an oxygen bather film which penetrates the oxide insulating film is formed around the channel formation region, whereby a diffusion of oxygen to the wiring, the electrode, and the like connected to the transistor can be suppressed.Type: GrantFiled: March 15, 2013Date of Patent: May 24, 2016Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Tetsuhiro Tanaka
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Patent number: 9324384Abstract: In a sense amplifier, a switching transistor is configured to apply a ground voltage to a ground node in response to a sense enable signal. A first detection circuit is configured to output a first detection signal to the first detection node based on a mode signal and a voltage of a bit-line. A second detection circuit is configured to output a second detection signal to the second detection node based on a voltage of a complementary bit-line. A latch circuit is connected to a supply voltage, the first detection node and the second detection node, and configured to output a first amplified signal and a second amplified signal through a latch node and a complementary latch node, respectively, based on the first detection signal and the second detection signal.Type: GrantFiled: October 2, 2014Date of Patent: April 26, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Tae-Joong Song, Sung-Hyun Park, Woo-Jin Rim, Gi-Young Yang
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Patent number: 9286555Abstract: An information processing device includes a computing unit and a display unit. The computing unit computes a power consumption per a predetermined time during a power saving mode that reduces power consumption, on the basis of a count per type of an interrupt signal produced during the power saving mode, and a power consumption pre-estimated per type of the interrupt signal. The display unit displays a power consumption computed by the computing unit using generated or stored electric power.Type: GrantFiled: May 7, 2014Date of Patent: March 15, 2016Assignee: FUJI XEROX CO., LTDInventors: Kenji Kuroishi, Tsutomu Nakaminato, Masafumi Ono, Motofumi Baba, Keiko Shiraishi, Yuri Takeuchi, Koichi Azuma, Kazuhiko Narushima, Hidenori Horie
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Patent number: 9281820Abstract: An asynchronous pipeline structure includes a plurality of functional blocks comprising dynamic logic, each block precharged to an idle state responsive to a precharge control signal applied thereto, with each block, upon being precharged, receiving input data thereto for processing, and holding output data generated thereby during an evaluate phase, independent of a reset of the input data; for each block, a completion detector circuit coupled to the output of the functional block, the completion detector circuit generating an acknowledgement signal that indicates validity or absence of data at the output of the block; and for each block, a precharge control circuit generating a precharge signal, wherein for a given block, a first input to the precharge control circuit comprises the acknowledgment signal from a downstream completion detector, and second input to the precharge control circuit comprises the precharge signal from an upstream precharge control circuit.Type: GrantFiled: March 1, 2013Date of Patent: March 8, 2016Assignee: RAYTHEON COMPANYInventors: Harry Marr, Kenneth E. Prager, Julia Karl, Lloyd J. Lewins
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Patent number: 9274751Abstract: A multiplier circuit comprises a fused Booth encoder multiplexer which produces partial product bits, a tree which uses the partial product bits to generate partial products, and an adder which uses the partial products to generate intermediate sum and carry results for a multiplication operation. The fused Booth encoder multiplexer utilizes encoder-selector cells having a logic tree which carries out a Boolean function according to a Booth encoding and selection algorithm to produce one of the partial product bits at a dynamic node, and a latch connected to the dynamic node which maintains the value at an output node. The encoder-selector cells operate in parallel to produce the partial product bits generally simultaneously. A given one of the encoder-selector cells has a unique set of both multiplier operand inputs and multiplicand operand inputs, and produces a single partial product bit.Type: GrantFiled: July 11, 2007Date of Patent: March 1, 2016Assignee: International Business Machines CorporationInventors: Wendy Ann Belluomini, Hung Cai Ngo, Jun Sawada
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Patent number: 9236114Abstract: In at least one embodiment, a sense amplifier circuit includes a bit line, a sense amplifier output, a keeper circuit, and a noise threshold control circuit. The keeper circuit is coupled to the bit line and includes an NMOS transistor coupled between a power node and the bit line. The keeper circuit is sized to supply sufficient current to compensate a leakage current of the bit line and configured to maintain a voltage level of the bit line. The noise threshold control circuit is connected to the sense amplifier output and the bit line. The noise threshold control circuit comprises an inverter.Type: GrantFiled: March 7, 2014Date of Patent: January 12, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventor: Bharath Upputuri
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Patent number: 9129685Abstract: A word-line driver includes first, second and third transistors. The first transistor includes a gate terminal driven by a first group selection signal, a first conduction terminal driven by a second sub-group selection signal and a second conduction terminal coupled to the word-line. The second transistor includes a gate terminal driven by a second group selection signal, a second conduction terminal driven by the second sub-group selection signal, and a first conduction terminal coupled to the word-line. The third transistor includes a gate terminal driven by a third the group selection signal, a first conduction terminal driven by a first sub-group selection signal, and a second conduction terminal coupled to the word-line.Type: GrantFiled: April 30, 2014Date of Patent: September 8, 2015Assignee: STMICROELECTRONICS INTERNATIONAL N.V.Inventor: Vikas Rana
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Patent number: 9018981Abstract: A latch circuit includes a latch unit and a clock propagation suppressing unit. The latch circuit holds and outputs input data of 0 or 1. The clock propagation suppressing unit compares the input data input to the latch unit with output data output from the latch unit. When it is detected that the input data matches the output data at 0, or that the input data matches the output data at 1, an externally input clock signal is prevented from propagating to the latch unit.Type: GrantFiled: June 12, 2012Date of Patent: April 28, 2015Assignee: Fujitsu LimitedInventor: Katsunao Kanari
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Patent number: 9000806Abstract: A device may include a latch activated during a second phase of a clock cycle; a clock gating component to control when a clock signal is to reach the latch; a destination storage element activated during a first phase of the clock cycle, where a logical path exists from the latch to the destination storage element; and a blocking element located in the logical path from the latch to the destination storage element, where the blocking element includes, as a first input, an output of the latch and, as a second input, an output of the clock gating component, and where the blocking element prevents an output value of the latch from changing when the clock gating component is not enabled and does not prevent the output value of the latch from changing when the clock gating element is enabled.Type: GrantFiled: May 31, 2013Date of Patent: April 7, 2015Assignee: Advanced Micro Devices, Inc.Inventors: Dwight K. Elvey, Someshwar Gatty
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Patent number: 8994405Abstract: A semiconductor integrated circuit device includes a first flip-flop circuit receiving data in synchronization with a first clock signal, a logic circuit performing a predetermined process on data output from the first flip-flop circuit, a hold buffer delaying transmission of an output of the logic circuit, a second flip-flop circuit receiving an output of the hold buffer in synchronization with a second clock signal, and a power supply circuit capable of selecting a supply of a power supply voltage to the first flip-flop circuit, the logic circuit, and the second flip-flop circuit between a first power supply voltage and a second power supply voltage higher than the first power supply voltage. A power supply voltage supplied to the hold buffer remains the same when the power supply voltage supplied to the first flip-flop circuit, the logic circuit, and the second flip-flop circuit changes between first and second power supply voltages.Type: GrantFiled: February 26, 2014Date of Patent: March 31, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Azuma Suzuki, Hiroyuki Hara
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Patent number: 8994404Abstract: A 3D device, including: a first layer including first transistors, the first transistors interconnected by a first layer of interconnection; a second layer including second transistors, the second transistors overlaying the first layer of interconnection; the first layer includes a first clock distribution structure, the first clock distribution structure includes a first clock origin, the second layer includes a second clock distribution structure, the second clock distribution structure includes a second clock origin, and the second clock origin is feeding the first clock origin.Type: GrantFiled: March 12, 2013Date of Patent: March 31, 2015Assignee: Monolithic 3D Inc.Inventors: Zvi Or-Bach, Zeev Wurman
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Publication number: 20150070050Abstract: A semiconductor integrated circuit device includes a first flip-flop circuit receiving data in synchronization with a first clock signal, a logic circuit performing a predetermined process on data output from the first flip-flop circuit, a hold buffer delaying transmission of an output of the logic circuit, a second flip-flop circuit receiving an output of the hold buffer in synchronization with a second clock signal, and a power supply circuit capable of selecting a supply of a power supply voltage to the first flip-flop circuit, the logic circuit, and the second flip-flop circuit between a first power supply voltage and a second power supply voltage higher than the first power supply voltage. A power supply voltage supplied to the hold buffer remains the same when the power supply voltage supplied to the first flip-flop circuit, the logic circuit, and the second flip-flop circuit changes between first and second power supply voltages.Type: ApplicationFiled: February 26, 2014Publication date: March 12, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Azuma SUZUKI, Hiroyuki HARA
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Patent number: 8957718Abstract: A flip-flop circuit has a master latch circuit and a slave latch circuit. In the flip-flop circuit, the master latch circuit and the slave latch circuit share at least a pair of transistors. In response to the clock signal, the signal held in the master latch circuit can be output at higher speed as the output signal via the intermediate node, the slave latch circuit and the output circuit. The flip-flop circuit can be reduced in cell size and improved in processing speed.Type: GrantFiled: July 29, 2013Date of Patent: February 17, 2015Assignee: Kabushiki Kaisha ToshibaInventor: Muneaki Maeno
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Patent number: 8928377Abstract: A scannable fast dynamic register including a data and scan enable circuit, a precharge circuit, a select circuit, a store circuit, and a scan input enable circuit. The data and scan enable circuit pulls a first precharge node to a discharge node in response to the clock upon evaluation in normal mode. The precharge circuit precharges first and second precharge nodes high, in which one of the precharged nodes discharges depending upon whether a data block evaluates. The store circuit and an output gate are responsive to the second precharge node to provide the output. The select circuit is interposed before the store circuit to allow injection of scan data in a scan mode. In scan mode, the scan input enable circuit provides scan data to the select and store circuits. The scan input enable circuit also includes a store circuit which operates with the first store circuit in a master-slave configuration.Type: GrantFiled: July 25, 2013Date of Patent: January 6, 2015Assignee: VIA Technologies, Inc.Inventor: Imran Qureshi
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Patent number: 8928354Abstract: A clock-delayed domino logic circuit includes a precharge circuit configured to control connection between a first node and a dynamic node in response to a clock signal, an evaluation circuit configured to control connection between a second node and an evaluation node in response to the clock signal, a logic network connected between the dynamic node and the evaluation node, the logic network configured to determine a logic level of the dynamic node based on a plurality of input signals, and a phase control circuit configured to output a logic level of the evaluation node or a logic level of the first node according to a level of the clock signal.Type: GrantFiled: December 21, 2012Date of Patent: January 6, 2015Assignee: Samsung Electronics Co., Ltd.Inventor: Min Su Kim
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Patent number: 8907700Abstract: A clock-delayed domino logic circuit includes a first pre-charge circuit configured to pre-charge a first dynamic node with a pre-charge voltage in response to a first clock signal received via a first control terminal during a pre-charge operation; a first logic network configured to determine a logic level of the first dynamic node in response to first input data signals during an evaluation operation; and a first storage circuit which is connected between the first control terminal and the first dynamic node.Type: GrantFiled: November 30, 2012Date of Patent: December 9, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Rahul Singh, Hyoung Wook Lee
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Patent number: 8907701Abstract: The present invention discloses a CMOS differential logic circuit. The CMOS differential logic circuit includes a precharge differential logic unit, which is precharged to a source voltage in response to a clock signal and is configured to output voltage having an increased load-driving ability using a boosting voltage; a voltage-boosting unit, which is pulled down by a ground voltage in response to the clock signal and is configured to boost the pulled-down voltage using capacitive coupling and output the boosting voltage; and a switching unit, which is configured to couple the precharge differential logic unit and the voltage-boosting unit in response to the clock signal. The propagation delay of a signal from the input terminal to the output terminal of a circuit in a low-source-voltage environment can be reduced, and the operating speed of the circuit and energy efficiency of the operation thereof can be improved.Type: GrantFiled: February 19, 2013Date of Patent: December 9, 2014Assignee: Research & Business Foundation Sungkyunkwan UniversityInventors: Bai Sun Kong, Jong Woo Kim, Joo Seong Kim
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Patent number: 8890573Abstract: A clock gating latch, a method of gating a clock signal and an integrating circuit incorporating the clock gating latch or the method. In one embodiment, the clock gating latch includes: (1) a propagation circuit having a single, first switch configured to be driven by an input clock signal, (2) a keeper circuit coupled to the propagation circuit and having a single, first switch configured to be driven by the input clock signal and (3) an AND gate coupled to the propagation circuit and the keeper circuit and having an internal node coupled to a second switch in the propagation circuit and a second switch in the keeper circuit.Type: GrantFiled: September 7, 2012Date of Patent: November 18, 2014Assignee: Nvidia CorporationInventors: Ilyas Elkin, Ge Yang, Jonah Alben
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Publication number: 20140292374Abstract: A method for controlling an IC having logic cells and a clock-tree cell. Each logic cell has first and second FETs, which are pMOS and nMOS respectively. The clock-tree cell includes third and fourth FETs, which are pMOS and nMOS respectively. The clock-tree cell provides a clock signal to the logic cells. A back gate potential difference (“BGPD”) of a pMOS-FET is a difference between its source potential less its back-gate potential, and vice versa for an nMOS-FET. The method includes applying first and second back gate potential difference (BGPD) to a logic cell's first and second FETs and either applying a third BGPD to a third FET, wherein the third BGPD is positive and greater than the first BGPD applied, which is applied concurrently, or applying a fourth BGEPD to a fourth FET, wherein the fourth BGPD is positive and greater than the second BGPD that is applied concurrently.Type: ApplicationFiled: March 26, 2014Publication date: October 2, 2014Inventors: Bastien Giraud, Fady Abouzeid, Sylvain Clerc, Jean-Philippe Noel, Philippe Roche, Yvain Thonnart
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Patent number: 8836369Abstract: A latch circuit switches a differential operation performed by a differential operation circuit including a first logic circuit, a second logic circuit, a third logic circuit, and a fourth logic circuit and a single end operation performed by a single end operation circuit according to a logic level of an inputted selection signal. The latch circuit performs an operation to output an input signal and an inverted input signal without change from a first output terminal and a second output terminal of the latch circuit, respectively, and an operation to set the input signal and the inverted input signal in a hold state in the differential operation and performs an operation to output the input signal from the first output terminal without change and an operation to set the input signal in a hold state in the single end operation, according to a clock signal and an inverted clock signal.Type: GrantFiled: October 3, 2012Date of Patent: September 16, 2014Assignee: Fujitsu LimitedInventors: Yuuki Ogata, Yoichi Koyanagi
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Publication number: 20140225645Abstract: A tuneable buffer circuit for use in a clock tree has multiple buffers in parallel, each buffer having a grounding function, and also a bypass switch in parallel with the buffers. The circuit has a normal mode of one buffer connected into circuit, a first low voltage mode of multiple buffers connected into circuit in parallel without grounding function, a second low voltage mode of the buffers connected into circuit in parallel with grounding function and a bypass mode.Type: ApplicationFiled: January 30, 2014Publication date: August 14, 2014Applicant: NXP B.V.Inventors: Vibhu SHARMA, Rinze Ida Mechtildis Pete MEIJER, Jose Pineda de Gyvez
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Patent number: 8791720Abstract: A control circuit comprises a first NOR gate, a first NMOS transistor, and a first PMOS transistor. The control circuit also comprises an output node. The control circuit further comprises a half latch keeper circuit coupled to a gate of the first NMOS transistor and to a gate of the first PMOS transistor. The half latch keeper circuit is configured to keep the output node at a logical 1 during a standby mode. The control circuit additionally comprises an operational PMOS transistor coupled to the output node. An output of the first NOR gate is coupled to a gate of the operational PMOS transistor. The control circuit is configured to turn off the operational PMOS transistor during the standby mode.Type: GrantFiled: October 3, 2013Date of Patent: July 29, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chan-Hong Chern, Fu-Lung Hsueh, Ming-Chieh Huang, Bryan Sheffield, Chih-Chang Lin
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Patent number: RE49986Abstract: A semiconductor integrated circuit includes: a main-interconnect to which supply voltage or reference voltage is applied; a plurality of sub-interconnects; a plurality of circuit cells configured to be connected to the plurality of sub-interconnects; a power supply switch cell configured to control, in accordance with an input control signal, connection and dis-connection between the main-interconnect and the sub-interconnect to which a predetermined one of the circuit cells is connected, of the plurality of sub-interconnects; and an auxiliary interconnect configured to connect the plurality of sub-interconnects to each other.Type: GrantFiled: December 13, 2021Date of Patent: May 28, 2024Assignee: Sony Group CorporationInventor: Hiromi Ogata