Abstract: A clock generating device includes: a DDS circuit that generates a periodic signal; and a comparator that compares an input signal and a reference signal and outputs a binary signal. The clock generating device includes a rate-of-change correcting unit that applies correction for increasing a rate of change at a crossing point with the reference signal to the periodic signal generated by the DDS circuit.

Abstract: A method and system for managing Digital to Time Conversion (DTC) is provided. The method comprises receiving a first Radio Frequency (RF) signal and a second RF signal. The second RF signal is a phase-shifted first RF signal. The method further comprises converting the first RF signal to a first Intermediate Frequency (IF) signal and the second RF signal to a second IF signal. Further, a time delay between the first IF signal and the second IF signal is estimated based on a time difference measurement technique. The second RF signal is processed based on the estimated time delay to compensate for a delay error associated with the second RF signal.

Abstract: In a transmission device for differential communication, a first cathode-side element part is coupled between a first communication line and a cathode-side power supply line, a second cathode-side element part is coupled between a second communication line and the cathode-side power supply line, a first anode-side element part is coupled between the first communication line and an anode-side power supply line, and a second anode-side element part is coupled between the second communication line and the anode-side power supply line. A driving portion drives the element parts based on transmission data input from an outside. A target potential generating portion generates target potentials of the element parts based on potentials of the first communication line and the second communication line.

Abstract: A method for compensating NCO jitter by changing a step value used to increment an accumulator in the NCO to make up for inaccuracies, or jitters. In one approach, a remainder in the accumulator may be monitored and a compensated clock close to the current edge of an ideal clock may be generated. In another approach, a compensated clock close to the next edge of the ideal clock may be generated after the current edge of the ideal clock is missed. The step value may be stored in a memory, which may be a register. A jitter compensator may include a comparator for monitoring the remainder in the accumulator or a detector for detecting whether an ideal clock has been missed. The jitter compensator may also change the step value to a step value for a faster clock to compensate jitter.

Abstract: A digital phase-locked loop (DPLL), a supporting digital frequency integrator, and a method are provided for deriving a digital phase error signal in a DPLL. A digital frequency integrator periodically accepts a digital tdcOUT message from a Time-to-Digital Converter (TDC) representing a measured ratio of a reference clock (Tref) period to a synthesizer clock (Tdco) period. Also accepted is a digital message selecting a first ratio (Nf). In response, a digital phase error (pherr) message is periodically supplied that is proportional to an error in phase between the reference clock and the (synthesizer clock*Nf).

Abstract: Methods and apparatus are provided in the present invention to adjust the frequency of an output clock close to within a required accuracy of an oscillation frequency. In another embodiment, a method comprises: entering a calibration mode; generating a first control word to control a timing of a clock synthesizer; adjusting the first control word until the timing of the clock synthesizer is sufficiently accurate with respect to a timing of a reference clock; sensing a temperature using a temperature sensor; storing a present value of an output of the temperature sensor and the first control word into a non-volatile memory; exiting the calibration mode; entering a normal operation mode; sensing the temperature using the temperature sensor; generating a second control word to control the timing of the clock synthesizer in accordance with an output of the non-volatile memory and the output of the temperature sensor.

Abstract: A low power frequency synthesiser circuit (30) for a radio transceiver, the synthesiser circuit comprising: a digital controlled oscillator (33) configured to generate an output signal (F0) having a frequency controlled by an input digital control word (DCW); a feedback loop (35-38) connected between an output and an input of the digital controlled oscillator, the feedback loop configured to provide the digital control word to the input of the digital controlled oscillator from an error derived from an input frequency control word (FCW) and the output signal; and a duty cycle module (32) connected to the digital controlled oscillator and the feedback loop, the duty cycle module configured to generate a plurality of control signals to periodically enable and disable the digital controlled oscillator for a set fraction of clock cycles of an input reference clock signal (RefClock).

Abstract: Transmitter device which includes at least: a) one delay line designed to output M signals which are delayed in relation to each other, where M is an integer greater than 1; b) a memory, designed to store at least M digital samples of a waveform, where each digital sample contains N bits, and to output each of the M digital samples successively on N output lines respectively under the control of one of the M delayed signals; and c) a digital-analog converter which includes N inputs linked to N output lines, designed to convert the M digital samples received as input from the N output lines of the memory and to successively output, on an output of the digital-analog converter, each of the M analog converted digital samples which together form an analog signal which is representative of the waveform.

Abstract: A method and system for managing power consumption of a component that employs a clock processing circuit to produce a processed clock signal used by the component from a clock signal supplied to the clock processing circuit. A frequency of a clock signal supplied to the clock processing circuit is changed based on operating characteristics of a voltage regulator module (VRM) or power supply unit so as to maintain acceptable operating parameters of the power supply unit during a change in frequency of a clock signal. Data pertaining to operating characteristics of the VRM or power supply may be one or both of two forms. In one form, this data is determined a priori from simulations or experiments made on a particular VRM or power supply unit and used to generate and store parameters that are known to optimally (quickly and without degradation of VRM or power supply performance) change the frequency of the clock processing circuit.

Abstract: Described is an apparatus that includes a frequency source and a plurality of time domain direct digital synthesizers each having an input connected to an output of the frequency source and an output providing an output frequency signal. A particular time domain direct digital synthesizer includes a sigma-delta modulator that functions as a second order multi-stage noise shaping sigma-delta modulator. In one exemplary embodiment sigma-delta modulator outputs provide a unitary-weighted word used to switch certain unit capacitors that comprise part of a delay modulator to produce a time-varying delay having a time-averaged value that directly corresponds to a binary value appearing on a plurality of phase accumulator outputs.

Abstract: A realtime display compression for a waveform image uses a priority basis for combining groups of pixels when producing a compressed waveform image in order to preserve intensity information. As an example successive lines of data for the waveform image are demultiplexed into line buffers in a circulating manner, the number of line buffers being a function of the maximum desired integer compression ratio. The outputs from the line buffers are aligned and the corresponding pixels are combined according to a desired compression ratio, one output line for each integer compression ratio. The appropriate compressed line is selected as the output line according to the desired compression ratio, with the totality of the output lines forming the compressed waveform image.

Abstract: A signal generator including a DDS-signal source that is configured to operate according to the principle of direct digital synthesis (DDS), and a PLL signal synthesizer that is configured to operate according to the principle of phase locked loop (PLL) using an output signal from the DDS-signal source as a reference signal. The DDS-signal source can be connected via a direct connection, without further frequency division or mixing, directly to an output of the signal generator or directly to a level-adjustment device of the signal generator in order to generate a portion of an overall frequency range of an output signal of the signal generator.

Abstract: An electrical waveform generating circuit has a programmable current source-driver. A digital switched current source is coupled to the programmable current source-driver and controlled by waveforms stored in the programmable current source-driver. A plurality of MOSFETs is coupled to the programmable current source driver. A center-tapped RF transformer is provided and has a primary coupled to the plurality of high voltage MOSFETs. A transducer is coupled to a secondary of the RF transformer.

Abstract: A DDS system is disclosed that is configured to provide a variable clock delay that allows timing of data coming out of the ROM to be adjusted. In one example case, a DDS system is provided that includes a ROM for storing phase-to-amplitude conversion data and generating digital amplitude values corresponding to respective digital phase values, and delay circuitry for adjusting timing of data output by the ROM to compensate for propagation delay of the DDS system. The delay circuitry may include, for instance, delay elements that can be selected alone or in combination to adjust the timing. The timing can be adjusted, for example, by adjusting delay of a clock signal that clocks one or more ROM pipeline registers. The system may include a phase accumulator and DAC, and adjusting the timing may include adjusting delay of a clock signal that clocks one or more DAC pipeline registers.

Abstract: Provided is a waveform generating apparatus that generates a signal having an arbitrary waveform, comprising a waveform memory that stores a plurality of pieces of waveform data that each include a sequence of signal values; a filtering section that (i) reads from the waveform memory a piece of waveform data serving as a basis for a waveform to be generated, from among the plurality of pieces of waveform data, (ii) performs a conversion by filtering the read piece of waveform data to obtain a piece of converted waveform data, and (iii) writes to the waveform memory the piece of converted waveform data; and a waveform output section that reads the piece of converted waveform data from the waveform memory and outputs a signal having a waveform corresponding to the sequence of signal values of the read piece of converted waveform data.

Abstract: A circuit for signal conditioning including a first stage with a digital/analog converter, a second stage with an I/Q-modulator, and at least one third stage with a mixer. Instead of a multiplicity of independent oscillators, a shared oscillator is provided for the first, second, and third stages, from an output signal of which a respective oscillator signal and clock-pulse signal for each stage of the first, second, and third stages is derived. The oscillator signal and respective clock-pulse signal of the oscillator are supplied via a frequency divider to at least one stage of the first, second, and third stages, or the oscillator signal of the oscillator is supplied via a frequency multiplier to at least one stage. Also, the oscillator signal of the oscillator is supplied as a reference signal to a frequency synthesizer of at least one stage of the first, second, and third stages.

Abstract: A digital frequency generator is described.

Abstract: An AWG includes a waveform memory providing a digital waveform signal at a sample rate and an arbitrary factor interpolator (AFI) coupled to receive the digital waveform signal or a processed digital waveform signal. A complex mixer for carrier modulation is coupled to the AFI which outputs a complex band pass signal. A DAC is coupled to an output of the complex mixer for receiving the complex band pass signal to provide an analog output signal. A fixed frequency sample clock clocks the DAC to provide a fixed DAC sample rate. The DAC provides a data clock signal to a sample request controller that generates a sample request signal that is coupled to the waveform memory for requesting the digital waveform signal from the waveform memory. The interpolated digital signal is sampled at the fixed DAC sample rate independent of the sample rate of digital waveform signal.

Abstract: Memory design techniques are disclosed that provide a high compression ratio at no loss in speed. The techniques can be embodied, for instance, in heterojunction bipolar transistor (HBT) based ROMs. By embedding compression logic (e.g., XOR) functionality directly into the address decoders and sense amplifiers of the memory device, a high compression ratio is achieved at no loss in speed. For example, the logic-based compression functionality can be directly implemented into the buffers that form the address decoder as well as the sense amplifiers.

Abstract: A method includes generating a plurality of reference phases of a reference signal and selecting a sub-phase from each of the plurality of reference phases to form a set of selected sub-phases. In the method selecting operates in response to synchronized outputs of a multi-phase phase accumulator that operates synchronously in accordance with one of the sub-phases of the set of sub-phases, and where the outputs of the multi-phase phase accumulator may be synchronized using at least one additional sub-phase.

Abstract: An output signal is generated from a received input data stream representing a sequence of digital data values. For each group of successive data values in the sequence of data values, a respective waveform pattern is assigned in dependence of the data content of the respective group of successive data values. The output signal is generated by generating the assigned respective waveform patterns corresponding to the input data stream.

Abstract: The present invention relates to a direct digital frequency synthesizer using a variable sine wave-weighted digital to analog converter with improved size and efficiency and a synthesizing method thereof. The direct digital frequency synthesizer and the synthesizing method thereof are capable of simplifying a configuration for matching output data of a phase accumulator to sine wave amplitude without increase in complexity of a DAC by applying a nonlinear DAC for directly generating a current corresponding to base points with sine weights and a variable sine wave-weighted DAC for generating fine currents to be combined with variable weights based on the base points. Accordingly, it is possible to provide a high quality output, reduce a size and power consumption, and increase a speed.

Abstract: A hybrid numeric-analog clock synchronizer, for establishing a clock or carrier locked to a timing reference. The clock may include a framing component. The reference may have a low update rate. The synchronizer achieves high jitter rejection, low phase noise and wide frequency range. It can be integrated on chip. It may comprise a numeric time-locked loop (TLL) with an analog phase-locked loop (PLL). Moreover a high-performance number-controlled oscillator (NCO), for creating an event clock from a master clock according to a period control signal. It processes edge times rather than period values, allowing direct control of the spectrum and peak amplitude of the justification jitter. Moreover a combined clock-and-frame asynchrony detector, for measuring the phase or time offset between composite signals. It responds e.g. to event clocks and frame syncs, enabling frame locking with loop bandwidths greater than the frame rate.

Abstract: The present invention relates to d a direct digital frequency synthesizer using a hybrid digital to analog converter, which is capable of synthesizing an analog signal with high quality without base decoding, thereby providing improved size and efficiency, and a synthesizing method thereof. The direct digital frequency synthesizer using a hybrid digital to analog converter, and a synthesizing method thereof are capable of simplifying a configuration of a PAM which matches output data of a phase accumulator to sine wave amplitude with an application of a hybrid DAC including a non-linear DAC and a linear DAC, without increase of complexity of a DAC, by causing the non-linear DAC to output a direct base point current using some bits of output data of a phase accumulator, causing the linear DAC to output a gradient current based on gradient information generated using other bits of the output data of the phase accumulator, and summing these currents for analog output.

Abstract: A digitally controlled frequency generator includes an oscillator module for generating a first clock signal having an oscillating frequency, a programmable control module operable so as to generate a control signal corresponding to a desired frequency, and a direct digital frequency synthesizer coupled to the oscillator module and the programmable control module for receiving the first clock signal and the control signal therefrom, and for generating a second clock signal having the desired frequency based on the first clock signal from the oscillator module and the control signal from the programmable control module.

Abstract: A method for controlling a synthesized local oscillator (SLO) includes: receiving a control input specifying a desired SLO output; receiving reference clock signal; generating a predefined set of dynamic clock signals from the reference clock signal; selecting a dynamic clock signal from the predefined set of dynamic clock signals in response to the control input; using the dynamic clock signal as an input to a direct digital synthesizer (DDS) module to generate a DDS output signal; selecting a DDS output band in response to the control input, the DDS output band including one of a baseband and an alias band; and processing the DDS output band to generate the SLO output.

Abstract: To provide a synthesizer module that can be used not only in a destination area but also in the whole world and that can be readily set in output frequency. In the synthesizer module, a calculation formula table of a nonvolatile memory stores a plurality of frequency modes and the calculation formula of carrier frequencies corresponding to those frequency modes, and further stores, in its certain area, a frequency mode set during an initial setting of the device. A CPU, when receiving a channel number from a rotary SW during a frequency setting, calculates, based on a calculation formula corresponding to a currently set frequency mode, a carrier frequency corresponding to the channel number. This carrier frequency is set to a CONT of a PLL part.

Abstract: A digital waveform synthesiser (1) is implemented as a single chip integrated circuit on a single chip (2) and comprises a direct digital synthesiser (10) which produces a synthesised output signal waveform on an output terminal (4) which is substantially phase and frequency locked to the phase and frequency of an externally generated input signal applied to an input terminal (5).

Abstract: In an embodiment, an apparatus, comprises a phase accumulator configured to provide an output comprising a truncated phase word representative of an instantaneous phase; a multiplexer configured to provide an output representative of a phase rotation, wherein the output representative of the phase rotation is randomly selected from a group of phase rotation representation outputs; an adder configured to receive the output from the phase accumulator and the output from the multiplexer, wherein the adder provides an output representative of the instantaneous phase rotated by the phase rotation; a lookup table configured to receive the output representative of the instantaneous phase and to provide an amplitude output; and a rotator configured to receive the amplitude output and substantially to cancel the phase rotation. Other embodiments do not comprise a rotator. A method is also described.

Abstract: A polyphase numerically controlled oscillator is disclosed. An input signal is received at a phase accumulator. The phase accumulator provides a phase to a phase interpolator. The phase interpolator then provides a plurality of output phases. The plurality of output phases are provided to a plurality of phase to amplitude converters. Each of said plurality of phase to amplitude converters process one of said plurality of output phases.

Abstract: An apparatus for generating sine/cosine values of an input phase is disclosed. The apparatus includes a phase projector, an LUT-arithmetic unit, a temp sine/cosine generator and a sine/cosine value generator. The phase projector maps the input phase angle into an octant phase and determines an octant index indicating which octant the input phase angle actually locates and a flag indicating whether or not the input phase happens to be pi/4, 3*pi/4, 5*pi/4 or 7*pi/4. The LUT-arithmetic unit receives the octant phase for provision of its corresponding sine/cosine values. The temp sine/cosine generator receives the corresponding sine/cosine values of the octant phase for provision of temp sine/cosine values based on the flag. The sine/cosine value generator selectively swaps and inverts the temp sine/cosine values as the sine/cosine values of the input phase based on a swap index derived from the octant index.

Abstract: A method is provided for reducing inter modulation distortion products using multi-carrier phase alignment of the type where a combined carrier signal is generated from the combined output carried waves of a plurality of numerically controlled oscillators in which the frequency of the carrier wave can be altered by changing an input value into the oscillator. In particular the initial phase of the output carrier waves is adjusted so that the peak amplitude of the combined carrier signal is minimized so that compression of the higher amplitude portions of the combined signal is reduced.

Abstract: The purpose is to provide a waveform generator that generates signals with a frequency lower than the minimum sampling frequency of the DAC. In the waveform generator 10, the clock generator 106 generates a clock signal 140. The frequency divider 112 divides the frequency of the clock signal 140 and generates the frequency-divided clock signal 144. The reader 118 provides an address signal at the period of frequency-divided clock signal 144 for the waveform memory 120 and reads the pattern data from the waveform memory 120 into the DAC 130. The DAC 130 converts the data provided from the waveform generator 120 at the period of clock signal 140 into an analog value and outputs a waveform of arbitrary shape.

Abstract: Provided is a waveform generating apparatus that generates a signal having an arbitrary waveform, comprising a waveform memory that stores a plurality of pieces of waveform data that each include a sequence of signal values; a filtering section that (i) reads from the waveform memory a piece of waveform data serving as a basis for a waveform to be generated, from among the plurality of pieces of waveform data, (ii) performs a conversion by filtering the read piece of waveform data to obtain a piece of converted waveform data, and (iii) writes to the waveform memory the piece of converted waveform data; and a waveform output section that reads the piece of converted waveform data from the waveform memory and outputs a signal having a waveform corresponding to the sequence of signal values of the read piece of converted waveform data.

Abstract: Jitterless transition of the programmable clock waveform is generated employing a set of two coupled direct digital synthesis (DDS) circuits. The first phase accumulator in the first DDS circuit runs at least one cycle of a common reference clock for the DDS circuits ahead of the second phase accumulator in the second DDS circuit. As a phase transition through the beginning of a phase cycle is detected from the first phase accumulator, a first phase offset word and a second phase offset word for the first and second phase accumulators are calculated and loaded into the first and second DDS circuits. The programmable clock waveform is employed as a clock input for the RAM address controller. A well defined jitterless transition in frequency of the arbitrary waveform is provided which coincides with the beginning of the phase cycle of the DDS output signal from the second DDS circuit.

Abstract: Phase-to-sinusoid conversion and method for direct digital synthesis are described. At least one quadrant of values for a sinusoidal signal are real-to-finite bit resolution mapped to provide preconditioned values which are on average shifted down by half of a LSB position. The at least one quadrant of preconditioned values are stored in a lookup table. MSBs of a phase-accumulated signal are used as an address for accessing from the lookup table a sinusoid value. At least a logic 1 is added as an LSB to an interim output associated with the sinusoid value to provide an adjusted sinusoid value having a bit width greater than that of the sinusoid value to provide a digitally synthesized sinusoidal value.

Abstract: The present invention reduces adjacent channel interference for a wireless peripheral device. A direct digital synthesizer generates a waveform having intermediate angular changes during a transition time between symbol intervals. After the transition time, the direct digital synthesizer generates the waveform with an angular value that corresponds to the symbol being transmitted. In an exemplary embodiment, a generated waveform is characterized by one of two designated frequencies in response to a value of an input information bit. The waveform is further characterized by at least one intermediate frequency during a transition time between a change of the designated frequency. Another embodiment of the invention utilizes phase changes rather than frequency changes during reduce adjacent channel interference. With another aspect of the invention, methods are provided to determine waveform parameters for reducing adjacent channel power (ACP) to a maximum level of interference.

Abstract: The circuits and methods of the various embodiments of the present invention enable changing the frequency of a frequency synthesizer. According to one embodiment, a method of changing a frequency of a clock signal generated by a frequency synthesizer comprises the steps of receiving a reference clock signal; receiving a command comprising a new frequency synthesizer value; locking to a new frequency based upon the new frequency synthesizer value; and dynamically outputting a generated clock signal based upon the new frequency synthesizer value. According to another embodiment, a method of changing a frequency of a clock signal comprises adaptively adjusting the digital loop bandwidth of the frequency synthesizer. A circuit for changing a frequency of a clock signal generated in an integrated circuit is also disclosed.

Abstract: Comb generators include a nonlinear transmission line (NLTL) having one or more NLTL sections. Each NLTL section includes one or more nonlinear elements and transmission line portions that provide transmission line dispersion. Typically, the nonlinear elements are Schottky diodes, and a pulse forming bias network is configured to establish Schottky diode bias conditions using a periodic signal that is input to the comb generator. For input periodic signals at frequencies between about 500 MHz and 1 GHz, output signals are produced having substantial power in frequency components at frequencies up to at least about 50 GHz.

Abstract: A phase controlling apparatus is disclosed. The phase controlling apparatus controls phases of signals which are output from a plurality of signal sources corresponding to first phase information which indicates a phase of a predetermined signal. The phase controlling apparatus includes a phase information storing section and a phase controlling section. The phase information storing section stores second phase information which indicates a phase of a signal which is output from each of the plurality of signal sources. The phase controlling section changes a phase of a signal which is output from at least one of the plurality of signal sources corresponding to the second phase information stored in the phase information storing means to control the difference of phases of signals which are output from the plurality of signal sources.

Abstract: A multichannel numerically controlled oscillator is provided. The multichannel numerically controlled oscillator has a dual port memory. An output function generation lookup table in the dual port memory is used to generate output functions for the numerically controlled oscillator. A first channel of output is generated based on a first address signal that is presented on a first port of the dual port memory. A second channel of output is generated based on a second address signal that is presented on a second port of the dual port memory. First and second phase accumulators may be used to produce the address signals for the first and second ports of the dual port memory, respectively. The phase accumulators may each contain a register, an adder, and a feedback path. The registers in the phase accumulators and the dual port memory may handle signals at the clock rate of the output channels.

Abstract: Method and apparatus for digital frequency synthesis are described. A frequency synthesizer has an accumulator, an adder, and a predictive filter. The adder is configured to subtract a predicted error from a phase profile signal. A quantized version of the phase profile signal is separated from an error portion thereof. The predictive filter, set for a fraction of a sample frequency bandwidth, is coupled to receive the error portion for generation of a next predicted error. A storage device has digital representations of sinusoidal signals accessible responsive to the quantized version of the phase profile signal. A digital-to-analog converter is coupled to receive a digital representation of a sinusoidal signal obtained from the storage device to provide an analog sinusoidal signal. An anti-imaging filter is coupled to receive the analog sinusoidal signal and configured to filter out noise.

Abstract: A jitter generator for generating a jittered clock signal, includes a jitter control signal generator and a jittered clock generator. The jitter control signal generator is utilized for selecting a digital control code from a plurality of candidate digital control codes at individual time points and respectively outputting a plurality of selected digital control codes. The jittered clock generator is coupled to the jitter control signal generator, and utilized for generating the jittered clock signal. The jittered clock generator dynamically adjusts the jittered clock signal according to the plurality of different digital control codes.

Abstract: To provide a synthesizer module that can be used not only in a destination area but also in the whole world and that can be readily set in output frequency. In the synthesizer module, a calculation formula table of a nonvolatile memory stores a plurality of frequency modes and the calculation formula of carrier frequencies corresponding to those frequency modes, and further stores in its certain area, a frequency mode set during an initial setting of the device. A CPU, when receiving a channel number from a rotary SW during a frequency setting, calculates, based on a calculation formula corresponding to a currently set frequency mode, a carrier frequency corresponding to the channel number. This carrier frequency is set to a CONT of a PLL part.

Abstract: Methods and systems for a local oscillator generator based on quadrature mixing using a phase shifter. Aspects of one method may include generating a local oscillator signal, where a frequency of the local oscillator signal may be determined by controlling a phase of in-phase (I) components and quadrature phase (Q) components of a first signal and a second signal. For example, by appropriately controlling a phase of each component that is to be mixed, the local oscillator signal may have a frequency that is the sum of a frequency of the first signal and a frequency of the second signal, or a difference of the frequency of the first signal and the frequency of the second signal.

Abstract: Circuits, methods, and apparatus for adjusting an NCO output in order to provide a signal that is phase-locked to a reference signal. This is particularly beneficial where the frequencies of the NCO output and reference signal are unrelated. One embodiment provides a circuit that corrects the phase of the NCO output in two steps in order to reduce the chance of metastability. During the first, the output of the NCO is phase shifted to the closest correct portion of a cycle of a clock signal. A second correction is then performed by steering a number of currents under the control of at least some of a number of remainder bits from the NCO. The current steering provides a die area efficient, low-noise phase correction. The decoded remainder bits are latched using a feed forward circuit that prevents the device from entering a locked state.

Abstract: A method for identifying and reducing spurious frequency components is provided. A method in accordance with at least one embodiment of the present disclosure may include generating a digital sinusoidal waveform at a direct digital synthesizer (DDS) and receiving the digital sinusoidal waveform at an audio digital-to-analog converter. The method may further include converting the digital sinusoidal waveform to an analog sinusoidal waveform containing spurious frequency components, combining the analog sinusoidal waveform with an analog distortion correction waveform to generate a composite output waveform and receiving the composite output waveform at notch filter circuitry. The method may also include filtering the composite output waveform to generate a filtered composite output waveform and amplifying a difference between the filtered composite output waveform and a signal from a circuit-under-test (CUT) to generate an amplified analog signal.

Abstract: A system and method are provided for synthesizing signal frequencies using rational division. The method accepts a reference frequency value and a synthesized frequency value. In response to dividing the synthesized frequency value by the reference frequency value, an integer value numerator (dp) and an integer value denominator (dq) are determined. The method reduces the ratio of dp/dq to an integer N and a ratio of p/q (dp/dq=N(p/q)), where p/q<1 (decimal). The numerator (p) and the denominator (q) are supplied to a flexible accumulator module, and a divisor is generated as a result. N is summed with a k-bit quotient to create the divisor. In a phase-locked loop (PLL), the divisor and the reference signal are used to generate a synthesized signal having a frequency equal to the synthesized frequency value.

Abstract: A frequency synthesizer is disclosed. The frequency synthesizer includes a period control word generator, a delta-sigma modulator, and a delay line unit. The period control word generator generates a period control word. The delta-sigma modulator receives the period control word and generates a phase selection signal. The delay line unit generates an output clock based on the phase selection signal. The delta-sigma modulator performs a carry-in operation based on a base number and the base number is adjustable and determined by a calibration process of the delay line unit.

Abstract: A system and method for asynchronous triggering in a waveform generator comprising a DAC sample clock for generating DAC sample clock signal. The system includes a sequencer clock for generating a sequencer clock signal having a frequency of 1/N of the DAC sample clock. The system also includes an output data generator having I outputs to receive a waveform data stream of samples shifted into the data generator at the rate of the sequencer clock signal. An output multiplexer coupled receives samples from each of the I outputs of the output data generator and outputs the samples as a multiplexed data stream to the DAC. A triggering system receives an asynchronous trigger and splits the signal into an integer multiple M trigger inputs, each trigger input delayed by a DAC sample clock cycle. A shift controller determines a trigger position based on the trigger inputs and shifts a different waveform data stream into the data generator in accordance with the trigger position.