Abstract: An apparatus according to a preferred embodiment of the present invention includes two memories each storing different octants of a sine (or cosine) waveform. The sine and cosine waveforms may be concurrently generated by alternately accessing each memory in succession. It is unnecessary to access one memory concurrently, so that both waveforms may be concurrently generated without requiring either two accesses to the same memory or a doubled memory size.

Abstract: A shape modulation transmit loop with digital frequency control permits spectral shaping of a digital pulse stream (12) by controlling the slew rate of the transition signal (16) between successive pulses. The loop is formed when the digital data stream is fed into an up/down counter (152) whose output is coupled to a programmable memory means (154), such as RAM, EEPROM, flash memory or similar electronic storage means. The output (108) of the programmable memory (154) forms a first input to an adder (112) which drives an accumulator (52) with specified steps. Values corresponding to the desired waveform (70) are stored in a lookup table (60) which is coupled to a digital-to-analog conversion circuit (64) which uses the values in the lookup table (60) to construct a sine wave output signal (70) corresponding to the frequency set by the current specified step of the up/down counter (152).

Abstract: A frequency correction circuit includes a temperature sensor (100) disposed to measure temperature and produce temperature signals representing sensed temperatures. A data supplier (110) stores information items, receives digital input signals representing and produces a digital output information signal representing an item selected in accordance with the digital input signal. A control circuit (120) receives the temperature signals and receives the digital output information signal. The control circuit (120) produces control signals based on the temperature signals. A clock circuit (150) is disposed to generate a reference frequency signal. A digital synthesizer (130) receives the reference frequency signal and the control signals. The digital synthesizer produces an output frequency signal as directed by the control signals received from the control circuit (120).

Abstract: A waveform generator 30 for generating a desired waveform includes a plurality of rectangular wave generators (40a to 40n) for generating a plurality of rectangular waves and a waveform synthesizing unit 42 for synthesizing the rectangular waves to generate a multi-level synthesized wave, and generate the desired wave based on the synthesized wave.

Abstract: A switched converter uses two series connected complementary CMOS devices and has a square wave source for activating one CMOS device while deactivating the other; and a break before make circuit connected between the square wave source and said complementary CMOS devices to ensure that one device is substantially completely off before the other device turns on. The switched converter is programmable as to frequency, phase and duty cycle.

Abstract: A signal generator and a method of generating a signal are disclosed that offsets phase and frequency of the output signal relative to the input signal by small increments, providing high resolution. The signal generator utilizes numerically controlled oscillators to instantly and independently offset phase and/or frequency.

Abstract: A frequency correction circuit includes a temperature sensor (100) disposed to measure temperature and produce temperature signals representing sensed temperatures. A data supplier (110) stores information items, receives digital input signals representing and produces a digital output information signal representing an item selected in accordance with the digital input signal. A control circuit (120) receives the temperature signals and receives the digital output information signal. The control circuit (120) produces control signals based on the temperature signals. A clock circuit (150) is disposed to generate a reference frequency signal. A digital synthesizer (130) receives the reference frequency signal and the control signals. The digital synthesizer produces an output frequency signal as directed by the control signals received from the control circuit (120).

Abstract: A fractional synthesis approach and arrangement are presented which achieve fine frequency resolution with low phase noise while at the same time retaining a high phase comparison frequency/fast frequency changing speed. An output signal having a desired output frequency is generated by a voltage controlled oscillator (VCO). An output divider divides the output frequency by an output divisor N to produce an output pulse train. The output divisor N may be equal to an output integer N or the output integer plus one N+1, for example, and may change during the generation of a single output frequency. For different desired output frequencies, the value of the output integer N may be varied. A reference divider divides a reference frequency by a reference divisor M to produce a reference pulse train. The reference divisor M may be equal to a reference integer M or the reference integer plus one M+1, for example, and may change during the generation of a single output frequency.

Abstract: A complementary waveform driver is disclosed that generates output signals SOUT with arbitrary high and low drive states with respect to an independently controlled baseline signal SBL. Accordingly, the driver can generate very fast and flexible waveforms with multiple levels and baseline components. The driver implements complementary differential pairs of transistors that alternately source and sink programmable currents to an output port, creating an output waveform with excellent rising and falling edge symmetry, and greatly improved fidelity, especially at low level voltage swings. A complementary amplifier stage defines the baseline voltage level. When combined with a programmable active load and window comparator, the driver is particularly suited for pin electronics in automatic test equipment (ATE) applications.

Abstract: A phase-locked loop (PPL) utilizing a RAM is disclosed. The RAM is provided to store a reference clock and a clock to be controlled. The PLL further comprises a voltage-controlled oscillator section controls a phase of the clock to be controlled. The PLL further comprises a controller for retrieving, from the RAM, data of said reference clock and said clock to be controlled. The controller determines a phase difference between said reference clock and said clock to be controlled. Additionally, the controller generating a control signal so as to reduce said phase difference and applying said control signal to said voltage-controlled oscillator section.

Abstract: A system and method for reducing the computational complexity of the calculations performed by a Numerically Controlled Oscillator (NCO). Through exploitation of mathematical symmetries and other techniques, the size of a lookup table of sinusoidal values employed by the NCO to approximate sinusoids may be reduced by the combination of different frequency shifts.

Abstract: A digital oscillation generator has a first feedback-supplied adder that has an input side connected to a first control input, a second feedback-supplied adder that has an input side connected to a second control input, a further adder that has an input side connected to a third control input and to the respective outputs of the first and second feedback-supplied adder, and a memory that has an input side connected to an output of the further adder and that has a first oscillation output.

Abstract: A multichannel television access control system is disclosed wherein processing of the broadband signal is performed by gated coherent RF injection on a plurality of channels, thereby effecting selective descrambling of an arbitrary subset of channels in a channel group. The system provides for a closed loop injection signal phasor control so as to maintain substantially constant relationship between the television signals and the injected signals. The combined signals are supplied to subscribers enabling the use of their cable ready equipment.

Abstract: An apparatus and method for generating a sine wave signal for a desired phase input. The sine wave signal is generated by implementing a linear expansion of the sine function. An incoming phase value is divided into a base phase value and an incremental phase value. The sine value for each base phase value is stored in a look-up table. The sine values for phase values falling between base phase values are generated using a linear expansion of the sine function.

Abstract: An all-digital frequency synthesizing system that will eliminate spurious frequencies that degrade the overall performance of the generation of a binary waveform. The frequency synthesizing system has a count series retention table that contains a series of count integers that are selected by a count signal that chooses which series of the integers are to be linked to a periodic reference counter. The periodic reference counter will count a number of periods of a periodic reference frequency and when the counter has reached the number of counts that is equal to the number of the count integer, the periodic output signal will be toggled from logic level to another logic level. A new periodic output signal period can be chosen by selecting a new series of count integers in the count retention table. A count compiler will create the series of count integers retained in the count retention table.

Abstract: A method for calibrating a frequency device by monitoring its output cycles over a first plurality of monitoring windows is disclosed. An accumulation of these monitored cycles is used to determine a correction for the device over a second plurality of monitoring windows. A method for obtaining fractional correction values to be applied for controlling the frequency device is also disclosed.

Abstract: A circuit for automatic frequency control includes an oscillator and a digital synthesis device to which a first frequency of the oscillator is supplied as a clock frequency and which generates an output signal having a second frequency. A frequency comparison device determines a frequency difference between the second frequency and a reference frequency and generates a digital output signal reproducing the frequency difference. The digital output signal is then supplied as an addition value to the digital synthesis device. The circuit for automatic frequency control generates a highly accurate and temperature-compensated output signal with the second frequency.

Abstract: An improved circuit and technique for obtaining phase-coherent synthesis using a direct digital synthesizer (DDS). In the phase-coherent frequency synthesis device of the invention, a computational engine constructed from a large programmable gate array, a digital signal processing microprocessor, or a number of discrete digital logic blocks generates information sent to the DDS for generating an output frequency, .function..sub.out, which is in phase with all previous outputs of the device at the same frequency.

Abstract: A direct digital frequency synthesizer includes inputs for a reference clock signal and a control word, and an output for a synthesized clock signal. A phase accumulator coupled to the input for the control word and the reference clock signal has an output for a phase control signal. A phase shifter has inputs for the reference clock signal and the phase control signal and an output coupled to the output for the synthesized clock signal. The control word can be used to adjust the output frequency and phase of the synthesized clock signal.

Abstract: A frequency synthesizer comprises a direct digital frequency synthesizer (DDFS), which provides in-phase and quadrature sinewave signals at a preset frequency from digital analogue converters respectively, and a balanced mixer. The balanced mixer provides an output signal having a carrier frequency twice that provided by DDFS and reduced levels of spurious signals. A signal having a desired frequency is generated by controlling the DDFS to generate sinewave output signals at half the desired frequency. The reduced levels of spurious signals obtained by the arrangement allows improved signals for use in, for example, local oscillator applications.

Abstract: A clock signal generating circuit generates a clock signal having a frequency other than frequencies obtained by dividing a predetermined frequency by natural numbers without using a PLL circuit. An oscillator generates a reference clock signal having a reference frequency. A counter counts the reference clock signal to divide the reference frequency of the reference clock signal. A count value output from the counter is reset when the count value reaches a predetermined number. Sine-wave data of a sine-wave is output when the count value is input, a set of the sine-wave data being output for successive numbers of the count value from zero to the predetermined number. The set of the sine-wave data corresponds to a predetermined number of waves of the sine-wave. A digital-to-analog converter converts the set of the sine-wave data into an analog sine-wave signal. A filter selectively filters a predetermined frequency component contained in the analog sine-wave signal.

Abstract: A method for frequency modulation synthesis and apparatus for performing the method. The method uses additions rather than multiplies and therefore saves the space and cost of multipliers in circuit implementations. The method saves further resources by using the coordinate rotation digital computer (CORDIC) algorithm to acquire sine values as opposed to an extensive sine look-up table. The method can be implemented with either a dedicated digital circuit or a programmed special purpose processor such as a digital signal processor. The hardware for implementing the method is normally integrated onto a semiconductor device.

Abstract: A direct digital synthesizer circuit and method for reducing the harmonic content in a synthesized output signal. The direct digital synthesizer generates first and second address signals driving first and second sine look-up read only memory (sine ROM) circuits. The first and second sine ROMs generate first and second digital sine wave signals which are offset in phase from one another by 180 degrees. The first and second digital sine wave signals are converted to first and second analog sine wave signals. The first and second analog sine wave signals are combined in a subtractor circuit. As a result of the phase relationship between the first and second analog sine wave signals, the fundamental component of these signals are emphasized by subtraction while the second harmonic component of theses signals are simultaneously de-emphasized.

Abstract: A direct digital frequency synthesizer for generating a digital sine or cosine function waveform receive digital input. Memory stores digital samples along portions of sine and cosine function waveforms. The memory outputs the digital samples in response to a first portion of the digital input. Control logic is responsive to the digital input and controls the output of the digital samples from the memory to allow digital samples along a complete cycle of the sine or cosine function waveform to be output even though only portions of the sine and cosine function waveforms are stored in the memory. A linear interpolator receives a second portion of the digital input and modifies digital samples output by the memory to generate intermediate digital samples between the digital samples stored in the memory to improve accuracy.

Abstract: The invention concerns a method and apparatus to synthesize a frequency employing digital phase words to represent successive phase values. A digital dither signal generator is used to generate a succession of dither words which are summed with the phase words to form address words. The address words are used to address a store to convert the address words to waveform values. The periodic quantisation noise introduced by the digital process is made more random by means of the dither words thereby reducing the quantisation noise components while accepting an increased total noise power. The synthesizer is of particular advantage when used to generate the reference frequency for a frequency multiplier implemented as a phase lock loop. By making the dither sequence repetition frequency outside the phase lock loop bandwidth, the spurious components are removed from the frequency range of interest.

Abstract: A line card integrates subscriber line interface circuitry, A/D and D/A converters, and digital signal processing technology. The digital signal processing technology performs many line card tasks such as switch hook detection, ground key detection, DC feed control, polarity reversal, ringing tests, fault detection, power cross detection, and ring trip detection. Silent polarity reversal is achieved by modulating a digital DC feed current waveform in accordance with a programmable predetermined waveform to smoothly transition the DC voltage of subscriber loop conductors A and B between approximately ground and central office battery voltage. The modulated waveform includes little if any energy in audio frequencies. Additionally, the functionality of the line cards 308[m:1] may be implemented partially or completely in hardware of software.

Abstract: A chirp direct digital synthesizer is formed with a phase and frequency tracker circuit to provide both enhanced resolution and reduced power consumption. The phase and frequency tracker circuit operates at a sub-synchronous clock rate and provides periodic phase and frequency correction data to the direct digital synthesizer. The phase and frequency tracker circuit is suitable for both continuous wave and chirp direct digital synthesizer operation.

Abstract: A digital waveform oscillator generates digitized waveforms without distortion using a lookup table. The frequencies which may be generated using direct lookup tables at their fundamental table frequencies are increased according to this invention by including multiple cycles of the waveform within a single table. The selection of a table length L and a number of cycles N to be stored in a lookup table is done in a manner to optimize corresponding values of the frequencies to be generated and the sample rate.

Abstract: A dual-tunable direct digital synthesizer is provided with a programmable frequency multiplier that multiplies a relatively low frequency fixed clock signal F.sub.clk so that the output frequency F.sub.o of the waveform is:F.sub.o =(F.sub.n /2.sup.N).times.(M.times.F.sub.clk)where N is the resolution of the digital control word, the tuning word F.sub.n is the value of the N-bit control word, M is the multiplication factor and M*F.sub.clk is the DDS clock frequency. The multiplication factor and, hence, the DDS clock can be reduced to track changes in the output frequency thereby lowering the average power consumption. Because the synthesizer can generate the same output frequency using different tuning word-to-DDS clock ratios, it can be tuned for optimum SFDR over a narrow band around the desired output frequency. In other words, an "enhanced dynamic range band" in the harmonic and spurious performance can be mapped out for each frequency in the bandwidth.

Abstract: A digital waveform oscillator generates digitized waveforms without distortion using a lookup table. The frequencies which may be generated using direct lookup tables at their fundamental table frequencies are increased according to this invention by including multiple cycles of the waveform within a single table. The selection of a table length L and a number of cycles N to be stored in a lookup table is done in a manner to optimize corresponding values of the frequencies to be generated and the sample rate.

Abstract: The present invention relates to methods and devices for generating cycled waveforms of nonsingle period, and more particularly to an improvement from the one-way counter used by conventional cycled waveform generator of nonsingle period into an up-down counter or a programmable up-down counter, along with an adder/subtracter. Thus, only the varied values in waveform relative to a DC level have to be filled into a table, and then the varied values in waveform (i.e. the digital waveform sampling values) are input into said adder/subtracter to obtain a periodic digital values by adding/subtracting with a predetermined DC level. Finally, cycled waveforms of nonsingle period are obtained by digital-to-analog converting of said digital values. With the methods and devices of the present invention, not only the fillings in said table can be decreased to reduce the cost, but also the DC output level can be fixed or adjusted arbitrarily for convenient signal processing.

Abstract: A frequency synthesizer that can switch an output frequency fast and generates little spurious output is provided. This frequency synthesizer comprises a phase locked loop including a voltage-controlled oscillator, a high frequency divider, a phase frequency comparator and a low-pass filter. The divisor controller circuit supplies a divisor that varies cyclically to the high frequency divider for a fractional dividing operation. When switching the output frequency, a passing bandwidth of the low-pass filter is enlarged to widen a loop bandwidth of the phase locking loop for fast switching. After switching, the passing bandwidth of the low-pass filter is reduced to narrow the loop bandwidth for reduction of a spurious output, at the timing when a predetermined period has passed for the switched output frequency to stabilize substantially.

Abstract: A signal processor with a simplified circuit configuration provides an improved processing speed and can be realized of small size and at inexpensive cost. The signal processor includes signal holding means for holding output signals from plural signal sources (S1-S4), and signal mixing means (M31-M34) for mixing at least two signals among the plural signals held to output plural mixed signals. Since the mixed signals are less than the signal sources in number, the small number of signal lines can lead to an increased processing speed. Then the mixed signals corresponding to discrete signals from plural signal sources enables processing without substantially destroying information.

Abstract: A frequency synthesizer having reduced spurious components for use in a receiving and transmitting apparatus. The frequency synthesizer includes a direct digital synthesizer (DDS) for generating a first signal having a first frequency determined by channel setting data. The first signal is applied to a frequency divider to generate a divided signal having a divided frequency. The divided signal is applied to a frequency converter for shifting the divided frequency by a shift frequency interval to provide a reference signal having a reference frequency. The reference signal is applied to a phase locked loop (PLL) for generating a final signal having a predetermined frequency characteristic.

Abstract: Disclosed is a digital multiplication circuit to multiply a digital signal SN by a periodic waveform that is, in principle, a sine waveform. This circuit uses a phase digital generator .phi. varying in saw-toothed form and it uses an approximation of the samples of a function K sine .phi. by algebraic sums of positive integer values of two for each phase value, K being a coefficient identical for all the phase values. The product of SN by these sums is rapid and easy to obtain and does not require a sine table. A decoder receiving the phase .phi. defines the powers of two to be set up, and a routing circuit carries out the operation of multiplication by powers of two under the control of the decoder. One or two adders obtain the sums of powers of two. The result is an approximate result of the product SN.K. sine .phi..

Abstract: A variable frequency synthesis apparatus and method use a phase prediction signal to enable integer division in the feedback path of a phase-lock-loop to provide an output signal at a rational frequency multiple of an applied reference signal. A fixed integer divide ratio is maintained within each period of the reference signal. The output signal provided by a variable frequency oscillator is frequency divided and is phase compared to the reference signal. The phase comparison produces a predictable, time-varying phase difference signal based on a known frequency difference between the output signal and the reference signal. The phase prediction signal cancels the predictable phase difference signal and isolates an phase error signal used to steer, or adjust, the frequency of the oscillator to precisely equal the rational frequency multiple of the applied reference signal when the phase error signal is minimized.

Abstract: A look-up table circuit implemented with MOS transistors that uses combinational logic to generate signals that enable the transistors. A circuit using 16 inputs and 4 select lines is disclosed. Two of the select lines are used as inputs to combinational logic including four NOR gates to generate enable signals for transistors in a third stage of the circuit. This produces a reduction in the propagation delay of a signal from the input to the output of the look-up table circuit.

Abstract: A system for synthesizing a waveform that employs combinatorial logic to generate digital data for each of a set of preselected waveform. The system includes circuitry for selecting a sequence of the preselected waveform pulses in response to a data signal and circuitry for converting the digital data for the sequence of the preselected waveform pulses into the waveform.

Abstract: A method of increasing the spatial resolution of polar coordinates sensor devices by phase-amplitude modulating the sine-cosine excitation signals to the hollow toroid driving core. A rotating elliptical sensing pattern is generated by digital synthesis means. Values of the elliptical sensing pattern and its complete revolution are stored in digital "look-up" tables and sequentially read at a high rate into two digital-to-analog converters to produce two "staircase" approximations of the sine-cosine waveforms. The ellipse generation has a first angular frequency and the ellipse precession has a second sub-multiple frequency.

Abstract: A multiple rate waveshaping method and apparatus for converting transmission data into communications code synthesized waveforms having different protocol frequencies in the physical layer of the fast Ethernet utilizes two state machines which convert the transmission data into appropriate waveforms using predetermined wave shaping signals, the outputs of the state machines being multiplexed and transmitted over the Ethernet media using a common set of differential current sourced drivers.

Abstract: A frequency synthesizer which uses a direct digital synthesizer (DDS) to generate a highly accurate periodic signal of a frequency selected from a plurality of reference frequencies. The DDS output signal is bandpass filtered utilizing a clean-up phase lock loop (PLL) to produce a spectrally pure reference signal and promote overall fast settling time. A second or primary phase lock loop, having a much faster settling time than the first PLL, adjusts the frequency of the reference signal generated by the clean-up PLL. In one embodiment, the DDS frequency synthesizer has a digital to analog (DAC) converter coupled to the clean-up PLL. Another embodiment uses a modified DDS (without a DAC or lookup table) and feeds the most significant bit (MSB) or overflow bit from the DAC accumulator into the "clean-up" PLL. In both embodiments, the resulting synthesizer has high spectral purity, fine frequency resolution and a fast settling time.

Abstract: A system for synthesizing a waveform includes waveform synthesis circuitry that generates digital data for each of a set of waveform pulses having preselected slopes at zero-crossing. A sequencer tracks the history of information contained in a data signal and selects a sequence of the waveform pulses in response to the history such that the sequence conveys the history of information while minimizing mismatches between the slopes of adjacent waveform pulses in the sequence.

Abstract: An architecture and system for the implementation of an all digital frequency synthesizing system is described. The frequency synthesizing system has a count series retention table that contains a series of count integers that are selected by a count signal that chooses which series of the integers are to be linked to a periodic input reference frequency counter. The periodic input reference frequency counter will count a number of periods of a periodic input reference frequency and when the counter has reached the number of counts that is equal to the number of the count integer, the periodic output frequency will be toggled from logic level to another logic level. A new periodic output frequency period can be chosen by selecting a new series of count integers in the count retention table. This architecture is structured such that it can be implemented in an automated logic design system.

Abstract: A voltage-controlled crystal oscillator circuit with an extended range is presented. The circuit has a crystal oscillator circuit, a phase-locked loop (PLL), and a look-up table. The crystal oscillator circuit generates a signal having a frequency f.sub.ref at its output node responsive to a voltage at its input terminal. The PLL has its input node connected to the crystal oscillator output node and generates a signal at the PLL output node having a frequency f.sub.o. A first divider circuit of the PLL divides the f.sub.ref frequency by a first variable integer M and a second PLL divider circuit divides the f.sub.o frequency by a second variable integer N. The look-up table, which has comparators connected to the input terminal, a counter connected to the comparators and a memory responsive to the counter and storing M and N values, varies M and N responsive to the input terminal voltage so that the voltage-controlled crystal oscillator circuit has an increased frequency range.

Abstract: A frequency synthesizer includes a phase adder, a read only memory, a D/A converter, a bandpass filter, a low-pass filter, a phase comparator, a loop filter, a voltage controlled oscillator, and a frequency divider. The phase adder adds frequency setting data and output data of a plurality of bits every input clock to set the addition result as new output data. The read only memory outputs sine wave data on the basis of the output data from the phase adder. The D/A converter D/A-converts the sine wave data from the read only memory. The bandpass filter (particularly a switched capacitor filter) receives an output from the D/A converter and has a pass frequency which changes in accordance with the reference frequency of an output sine wave signal. The low-pass filter removes a high-frequency component from an output from the bandpass filter. The phase comparator compares the phase of an output from the low-pass filter with the phase of a frequency-divided output of the sine wave signal.

Abstract: A digital frequency synthesizer for use in a subscriber unit of a wireless digital communication system includes a processor, for providing an output phase signal corresponding to a selected output digital frequency a storage device having predefined stored values pertaining to the amplitude of a signal for a single quadrant, and a signal generator which receives the phase signal and generates sine and cosine waveforms utilizing amplitude values obtained from the lookup tables. The signal generator accesses the storage device differently depending upon the quadrant and sign of the phase data such that the storage device provides an amplitude value from said set of values based upon the phase data.

Abstract: A sine-wave generator circuit is provided to generate data representative of a sine wave by using a ROM which stores sine-wave data of only a selected phase region between 0 and .pi./2, for example. The circuit receives input phase data which are represented by twos complements and whose low-order bits are used as address data for the ROM; and each bit of the input phase data has a specific weight factor. When reading out data from the ROM, a normal order or a reverse order for the address data is designated in accordance with high-order bits of the input phase data, so that data representative of other phase regions are generated based on output of the ROM. Then, phase adjustment is performed on the data in accordance with the high-order bits. The data stored in the ROM has certain offset in advance in order to regenerate a sine wave accurately; however, the offset causes an error in output of the ROM.

Abstract: A digital frequency synthesizer employs a predetermined residue number system to generate phase angle information. The phase angle information is then converted from the predetermined residue number system into a weighted binary number. A part of the weighted binary phase angle information is used to address a read only memory that includes predetermined initial data points at each address. A predetermined iteration process that makes use of some or all of the weighted binary phase angle information that was not used to address the read only memory is then employed in an iterative process to generate final data points for the predetermined waveform. The initial data points are stored in the read only memory as weighted binary numbers and the iterative process employs weighted binary arithmetic. A second embodiment stores the initial data points in the read only memory as digits from a predetermined residue number system and the iterative process employs residue number system arithmetic.

Abstract: A multichannel frequency phase variable signal source is described having particular application in the simulation of an emitter environment for testing interferometer receivers. An improved direct digital frequency synthesizer produces phase information for initiating the operation of a related frequency synthesizer at a different phase point from those of the remainder of the synthesizers forming the multi channel source. An improved direct digital frequency synthesizer is described for varying this phase information.

Abstract: A fractional-N frequency synthesizer which incorporates division by a fractional value. Division is by a first value during first cycles and by a second value during second cycles. During the first cycles, an error in value accumulates, and when it reaches a certain value, causes a change in the dividing ratio to reduce the error value. The increase and decrease in error causes spurs in the output frequency spectrum. These spurs are cancelled using a cancellation network. The gain of the phase detector is temperature-compensated and the gain of the spur cancellation network is not, but the temperature compensation of the phase detector gain causes compensation of both values.