Abstract: An apparatus provides a local oscillator signal based on a selected channel of an RF input signal. For example, the apparatus can set a frequency of the local oscillator signal based on the selected channel. Digital circuitry can be used to generate the local oscillator signal. For instance, the digital circuitry can provide a digital representation of the local oscillator signal. A DAC can convert the digital representation to an analog signal. Other circuitry can provide first and second quadrature components of the local oscillator signal, based on the analog signal.

Abstract: A radar system having a transmit signal path and a receive signal path and an event generator which is responsive to command signals provided by a digital signal processor (DSP) is described. The DSP generates command signals and provides the command signals to the event generator. In response to the command signals, the event generator generates event signals in the radar system. The event signals include but are not limited to ramp control signals provided to a controllable signal source which provide RF signals to the transmit path of the radar.

Abstract: A frequency synthesizer according to the direct digital synthesis method is provided. The frequency synthesizer includes a phase accumulator for the cyclical incrementation of a phase signal by a phase increment M present at the input of the phase accumulator, a memory unit with a table of sine-function values stored in its memory cells for the determination of sine-function values corresponding to phase values of the phase signal, a digital-to-analog converter for the conversion of time-discrete sine-function values into a quasi-analog sinusoidal time function and an anti-aliasing low-pass filter for smoothing the quasi-analog sinusoidal time function. The frequency synthesizer additionally contains an adder, which is connected between the memory unit and the digital-to-analog converter and which superimposes a non-periodic signal over the time-discrete sine-function values.

Abstract: A video signal processing apparatus and a design method therefor are provided, and more particularly, a design method for a video signal processing integrated circuit (IC), in which to solve the shortage of pin ports caused by designing a video signal processor in a single IC, a vertical synchronization signal is output and a quasi synchronization signal is input through a single pin port, and an IC and a video signal processing apparatus thereby are provided. According to the design method, by designing a vertical synchronization dividing circuit inside an IC without increasing the number of pins in a video signal processing IC, the present invention can reduce the number of components, material costs, and save the PCB space. In addition, by integrating the vertical synchronization dividing circuit inside an IC, the component difference of a discrete device can be reduced, which enhances IC performance.

Abstract: A waveform output device includes a data reception unit which receives at least a part of a waveform pattern generation program transmitted from an external device connected to the data reception unit through a data line, the waveform pattern generation program being able to generate output data information and output time information, a tentative storage device which tentatively stores the waveform pattern generation program received from the data reception unit, a data processing unit which processes the waveform pattern generation program in the tentative storage device to generate the output data information and the output time information, and an output waveform generation unit which outputs waveform data to drive an electronic device based on the output data information and the output time information.

Abstract: A multi-phase signal generating apparatus is provided for readily generating multiple phase signals. The multi-phase signal generating apparatus comprises a signal data storage which stores a plurality of data segments for determining a predetermined period of one signal. A data segment selector circuit selects segments for constituting the phase signals from a plurality of data segments stored in the signal data storage for determining the predetermined period of a signal in each of a plurality of segment intervals which make up a phase signal cycle for generating a phase signal. Each phase signal generator circuit forms each phase signal using a plurality of selected segments for each phase signal during a plurality of segment intervals.

Abstract: An apparatus provides a local oscillator signal based on a selected channel of an RF input signal. For example, the apparatus can set a frequency of the local oscillator signal based on the selected channel. Digital circuitry can be used to generate the local oscillator signal. For instance, the digital circuitry can provide a digital representation of the local oscillator signal. A DAC can convert the digital representation to an analog signal. Other circuitry can provide first and second quadrature components of the local oscillator signal, based on the analog signal.

Abstract: A digital synthesizer includes a digital radio frequency memory (DRFM) for storing phase values and corresponding digital signals. The digital synthesizer includes a digital processing circuit receiving input from the DRFM, the circuit including tapped delay lines and a summer summing the output of the tapped delay lines. The digital synthesizer includes a signal modulator independently synthesizing within each tapped delay line a frequency modulated and gain scaled signal, wherein input to the tapped delay lines are phase values from the DRFM.

Abstract: A decoder for a memory device includes driving devices each applying a respective line voltage to a respective line of the memory device when turned on. The decoder also includes a control device coupled to the plurality of driving devices at a common node for generating a voltage that controls the driving devices to turn on or off. Also, a capacitor coupled to the common node increases the voltage at the common node from an initial boost voltage to a final boost voltage. Thus, a line of a memory device is driven to a boost voltage with minimized area and wiring complexity.

Abstract: A polyphase numerically controlled oscillator (PNCO) is defined to include a plurality of sub-numerically controller oscillators (SNCO's). Each SNCO is capable of receiving a clock signal at a first clock rate and an assigned phase offset signal. Each SNCO is configured to generate a digital waveform for the assigned phase offset signal. The PNCO also includes a plurality of frequency multipliers for generating a frequency multiplied representation of the digital waveform generated by each SNCO. The PNCO further includes a multiplexer configured to receive output from each of the frequency multipliers according to the first clock rate. The multiplexer is further configured to receive a select signal, wherein the select signal triggers the multiplexer at a second clock rate.

Abstract: A method and apparatus for reducing unwanted harmonics in direct digital synthesizer (DDS) output. The method comprises the steps of providing a set of k phase-shifted clock signals, examining, in succession, each DDS accumulator state, and determining whether the DDS accumulator state has a defined transition-state. For each DDS accumulator state having a defined transition-state, an interpolation is performed based upon the value of the preceding DDS accumulator state, an element of the set of phase-shifted clock signals is selected based upon the interpolation, and the most significant bit (MSB) is repositioned using the selected element of the phase-shifted clock signals. The apparatus comprises means for providing a set of k phase-shifted clock signals, means for examining, in succession, each DDS accumulator state, and means for determining whether the DDS accumulator state has a defined transition-state.

Abstract: A waveform drawing routine is disclosed that includes receiving an array of predecessor image data points, wherein the predecessor image data points form a predecessor line that has a predecessor high end point and a predecessor low end point, receiving an array of successor image data points, wherein the successor image data points form a successor line having a successor high end point and a successor low end point, comparing the successor line to the predecessor line, and maintaining any portions of the predecessor line on a display that intersect with the successor line. The method described above for drawing each line segment that forms the waveform is repeated until a complete waveform is drawn on the display that consists of the concatenation of these individual lines.

Abstract: There is disclosed a frequency synthesizer having an HF synthesizer for generating a first reference frequency signal having a variable frequency in a high-frequency band as a unit synthesizer, an LF synthesizer for generating a second reference frequency signal in a low-frequency band as another unit synthesizer, and an arithmetic circuit including a mixer for receiving the first and second reference frequency signals, a divider for receiving the second reference frequency signal, a mixer for receiving the first reference frequency signal and an output signal from the divider, a divider for receiving an output signal from the mixer, a divider for receiving an output signal from the mixer and capable of switching a division ratio, and a switch for switching and outputting output signals from the dividers, wherein an output signal of the switch is outputted as a first local signal, and an output signal from the divider is outputted as a second local signal.

Abstract: There is provided a synchronous memory device, in which a data input setup timing is calibrated. The synchronous memory device includes: a data input unit for calibrating a timing of data inputted in synchronization with a data strobe signal; and a first setup time control unit for detecting an input timing of an OCD control code data inputted to the data input unit in an OCD calibration mode, and for controlling a data output timing of the data input unit.

Abstract: The present invention provides an all-digital frequency synthesizer circuit using interpolation technique and Linear Feedback Shift Register (LFSR). This synthesizer adaptively outputs two sequences stored in a bank of memory, or shift register. Using the idea of interpolation, all synthesizable frequencies located between two predetermined threshold frequencies can be obtained, and resolution is determined by the order of LFSR thereby. A frequency synthesizing system is also included in the present invention.

Abstract: The present invention provides a technique that prevents a shift of a driving waveform due to accumulation of errors in a process of generating the driving waveform to drive driving elements on a print head. The technique of the present invention successively sums up a plurality of gradient data at a preset calculation period to give a result of summation and carries out digital-to-analog (D-A) conversion with regard to only specific upper columns in the result of summation in synchronism with the preset calculation period, so as to generate a driving waveform. Each gradient data represents a local gradient of the driving waveform and is stored in a memory. In the process of generating the driving waveform, the technique of the present invention corrects the result of summation to a preset value under a predetermined condition. One preferable embodiment clears specific lower bits in the result of summation in synchronism with a floor signal.

Abstract: A phase lock for a synthesizer phase reference oscillator that is used in conjunction with a conventional DDS circuit to synthesize an RF output frequency includes a second DDS circuit that is added with a reference increment value as an input to provide a phase offset frequency. A frequency/phase comparator compares a frequency reference oscillator output with the phase offset frequency to generate a control signal for phase locking the phase reference oscillator to the frequency reference oscillator. To determine the correct value for the reference increment value, a switch is provided between the frequency/phase comparator and the phase reference oscillator and the control signal is input to an analog-to-digital converter. During a “turn on” procedure the resulting digitized control signal is observed by a control system as the reference increment value is adjusted until a slow ramp, positive or negative, in the control signal is observed.

Abstract: A device generating a pulse signal includes at least one first register which stores waveform data therein, a pulse signal generation unit which generates a pulse signal in accordance with the waveform data of the first register, a control unit which is connected to a bus, and is controlled by control signals supplied from the bus, and a signal line which is separate from and independent of the bus, and is connected to the control unit, wherein the control unit updates the waveform data of the first register in response to a signal that is externally supplied through the signal line.

Abstract: An output driver includes a predriver circuit coupled to a complimentary MOS transistor pair. Third and fourth complimentary MOS transistors are coupled between a source-drain pair of the first and second MOS transistors, respectively and an output. The back gate of at least one of the third and fourth transistors is coupled to the output to provide a lower VT at the beginning of a transition without creating excessive undershoot or overshoot. A diode is coupled in parallel with the source-drain paths of the third and fourth transistors.

Abstract: A frequency synthesizer, especially for mobile radio base stations, transforms a digital input signal having a first frequency rapidly into a digital output signal having a second frequency. Similar to an N-fractional synthesizer, in the frequency synthesizer, the digital input signal is fed to a series connection having a phase detector, a filter and a voltage-controlled oscillator. The conventional N/N+1 divider provided in the feedback path, as in an N-fractional synthesizer, is replaced by some sort of digital synthesizer that is clocked or supplied with the digital output signal that is produced by the voltage-controlled oscillator.

Abstract: A method is provided for synthesizing an arbitrary waveform that approximates a specific waveform. The method includes specifying respective frequencies of component waveforms to be used to generate the arbitrary waveform, the frequencies being less than the maximum frequency needed to synthesize the specific waveform. The method further includes performing a least squares optimization of respective amplitudes and phases of the component waveforms across at least one predetermined time interval. The component waveforms having the amplitudes and phases optimized by the least squares optimization are then summed to produce the arbitrary waveform.

Abstract: A frequency dither technique is used for reducing spurs due to phase increment errors in a direct digital synthesizer output sinusoid. The spurs for a desired output frequency are calculated and, if the spurs fall within a phase locked loop bandwidth, a pair of phase increment values are used representing a pair of frequencies that average to the desired output frequency and the spurs of which fall outside the phase locked loop bandwidth.

Abstract: Method and apparatus for generating sinusoidal signals in quadrature. A numerically controlled oscillator includes a phase accumulator configured to generate a periodic multi-bit signal at a given frequency; a first memory configured to store an octant of a sinusoidal waveform; a second memory configured to store a complementary octant of the sinusoidal waveform; and a control circuit, responsive to at least a portion of the phase accumulator signal and coupled to the first and second memories, the control circuit configured to access the first and second memories in parallel and construct respective sine and cosine waves at the given frequency.

Abstract: A waveform generator for generating a desired waveform is provided, including a noise kernel configured to store a plurality of samples from a predetermined waveform, the plurality of samples being assigned to a plurality of memory blocks; and an address arrangement configured to randomly select a selected one of the plurality of memory blocks; wherein the noise kernel is configured to communicate the plurality of samples assigned to the selected memory block.

Abstract: A method of and apparatus for digitally generating a broadband signal comprising a plurality of CW or quadrature modulated signals having incrementally related frequencies wherein said plurality of signals are centered about a center RF frequency is disclosed. The invention provides for generating a first and second composite baseband signal each comprising a linear combination of N sinusoids, or N modulated signals each modulated in quadrature so as to achieve a desired instantaneous phasor value for each of the RF signals. The invention further provides for modulating in quadrature the first and second composite baseband signals on a local oscillator signal having a frequency equal to the center RF frequency.

Abstract: A method is provided for aligning the center frequency of an infrared transmitter. The method comprises the steps of: (a) providing a voltage-controlled oscillator for driving the infrared transmitter, where the oscillator is adapted to receive a bias voltage from a microprocessor; (b) applying a bias voltage to the oscillator; (c) receiving an output signal from the infrared transmitter into an infrared receiver; (d) determining a frequency associated with the output signal; and (e) adjusting the bias voltage based on the frequency associated with the output signal, thereby aligning the center frequency of the infrared transmitter.

Abstract: A frequency synthesizer that improves a unique DDS characteristic, while maintaining a circuit scale (ROM size) of a direct digital synthesizer (DDS). A first digital signal generator generates a quantized frequency signal, and a second digital signal generator generates a frequency signal having a fine frequency resolution and many spurious signals as compared with the first digital signal generator. A filter performs band rejection on an output of the second digital signal generator, and a mixer mixes an output of the first digital signal generator with an output of the filter.

Abstract: The numerically controlled oscillator (8) is mounted in particular in a radiofrequency signal receiver which further includes means (3) for receiving and shaping the radiofrequency signals, a correlation stage (4) and a clock signal generator. The oscillator receives at one input a clock signal with a first frequency (CLK) which clocks the oscillator operations, and a binary word of several bits (Nb) to provide at one output at least an output signal (Mb) with a frequency determined as a function of said binary word and the clock signal. The oscillator includes a first accumulation stage (12) for a first number of most-significant bits (Ob) of the binary word and a second accumulation stage (12) for a second number of least-significant bits (Pb) of said binary word. The first accumulation stage is clocked at the first clock frequency (CLK) to supply the determined frequency output signal (Mb), while the second stage is clocked at a second clock frequency (CLK/N) N times lower than the first clock frequency.

Abstract: A circuit comprising a phase detector/correction circuit, at least one column of memory cells, a control circuit and a sense amplifier. The control circuit may be configured to read a sequence from the memory cells in a predetermined order and present a first output signal. The sense amplifier may be configured to present a periodic signal in response to the first output signal.

Abstract: A first waveform data storage portion stores sine wave data or cosine wave data in either of the angular sections on both sides of a zero-crossing point of a sine wave or a cosine wave, each of the angular sections being defined by 45 degrees of an angular which is defined as one of eight sections equally divided by an angle range 0-360 degrees on the basis of 0 degrees. A second waveform data storage portion stores sine wave data or cosine wave data in an angular section adjacent to the angular section in which the data stored in the first waveform data storage portion exist. An angular data generation portion outputs address data that are a counted value of pulses at every angular section of 45 degrees, and three-bit data are carried-up at every generation of the address data. The address data are used for reading waveform data from the first and the second waveform data storage portions.

Abstract: A direct digital frequency-synthesis device includes a modulo-M coherent accumulator that generates a first phase law from a frequency-control word. A table, addressed by a second phase law derived from the first phase law, generates a digital sinusoidal signal. A digital/analog converter converts the digital sinusoidal signal into an analog sinusoidal signal. A filter filters the analog sinusoidal signal. And, a divider divides the filtered signal. The divider has a lower order than M and has a synchronization input driven by a synchronization pulse for re-synchronizing the signal after division, the synchronization pulse being derived from the phase law. Such a device may find particular application to digital synthesizers for radar.

Abstract: A subscriber unit has a processor. The processor provides an output phase signal corresponding to a selected output digital frequency. A tuning register buffers the phase signal. A lookup table has two sets of predefined stored values pertaining to the amplitude of a signal for a single quadrant. The predefined stored values comprise coarse angle approximations and fine angle approximations. A sine and cosine generator receives the phase signal and generates sine and cosine waveforms utilizing amplitude values obtained from the lookup table. The phase signal includes phase data and specifies the quadrant and the algebraic sign of the phase data. The sine and cosine generator accessing the lookup table differently depending upon the quadrant and sine of the phase data, such that the lookup table provides an amplitude value from the sets of predefined stored values based on the phase data.

Abstract: A memory mapped programmable output generator, capable of producing events such as creating complex waveforms, triggering analog to digital and digital to analog conversions, and generating processor interrupts is disclosed. These events are considered high speed since they are timed relative to a high-speed clock and require minimal processor over head. The event generator may be embodied as either a peripheral to a microcontroller or as a separate circuit. In its preferred embodiment, the output generator is a peripheral device on a microcontroller and uses a dedicated programmable, reloadable timer which is inaccessible to other blocks. Events are loaded in a serial format, where only one event is active at a given time. These events are sequenced through address pointers associated with each event. Once a given event is completed, the output generator loads the next event from a next address pointer.

Abstract: An apparatus for providing both supports including synchronous dynamic random access memory module and the double data rate dynamic random access memory module is provided. A motherboard can support standard synchronous dynamic random access memory and dual data rate dynamic random access memory by using the disable and enable functions of the terminator. The invention reduces manufacturing production waste due to complex fabrication process of memory module. In addition, the trouble of upgrading the computer by consumer can be eliminated.

Abstract: Circuits and methods for generating an accurate digital representation of a sinusoidal wave. Based on the desired output frequency, multiple samples are calculated from multiple cycles of a repeating waveform such as a sinusoidal wave. As samples are taken, they are stored in a memory location until a sufficient number of samples are accumulated. After the samples are accumulated, they are output in a specified order, which generates an accurate digital representation of a sinusoidal wave at the desired output frequency.

Abstract: A numerically controlled oscillator that generates an accurate digital representation of a repeating waveform such as a sinusoidal wave. Based on the desired output frequency, multiple samples are calculated from multiple cycles of the repeating waveform. As samples are taken, they are stored in a memory location until a sufficient number of samples are accumulated. After the samples are accumulated, they are output in a specified order, which generates an accurate digital representation of a sinusoidal wave at the desired output frequency.

Abstract: A direct digital frequency synthesizer and a hybrid frequency synthesizer combining the direct digital frequency synthesizer and a phase locked loop is provided. The direct digital frequency synthesizer includes a phase accumulator that is configured to generate a discrete phase signal. Spurious phase modulation in the discrete phase signal is reduced by a noise shaper, and the output of the noise shaper is then used to address a phase-to-amplitude translator. The phase-to-amplitude translator generates a discrete waveform which is converted to a continuous waveform by a digital to analog converter. The hybrid frequency synthesizer uses a mixer to combine a reference frequency generated by a reference source and a DDFS output signal generated by a direct digital frequency synthesizer. The output from the mixer is then coupled to the input of a phase locked loop which multiplies the mixer output to generate the frequency synthesizer output.

Abstract: A technique is described for providing a pulsed radar exciter signal, in a radar exciter including a direct digital synthesizer (DDS). The DDS is reset pulse-to-pulse to provide a pulsed DDS signal having pulse-to-pulse phase discontinuities due to the resetting of the DDS. The phase of the pulsed DDS signal can be shifted pulse-to-pulse by a phase shift that is held constant over a pulse to correct the pulse-to-pulse phasing of the DDS signal. A discrete phase modulator can provide the phase shift. The phase of the pulsed DDS signal can be shifted pulse-to-pulse by an additional phase shift which is a linear phase sequence from pulse-to-pulse, or by an additional phase shift which is a quadratic phase sequence from pulse-to-pulse to produce a ranging waveform.

Abstract: A programmable read-only memory supplied with power at a specified voltage has word-line drivers that drive the word lines of the memory-cell array to the same potential, regardless of whether the specified voltage has a first value or a second value. This effect is achieved by using different types of transistors to drive the word lines, depending on the specified voltage. As a result, the same memory-cell array, the same programming voltages, and the same wafer process can be used for memories operating at either of the two specified voltage values. Consequently, less time and effort are needed to design memories for different power-supply voltages.

Abstract: A method for generating a waveform at a particular frequency in which a segment RAM depth is determined based on the relationship between the frequency and a variable clock value, a RAM based memory system is provided with waveform information, and the waveform is sequentially generated from a combination of the waveform information in the RAM based memory system from a first memory site to a memory site dependent on the segment RAM depth. The generated waveform is filtered to obtain only the waveform at the desired frequency. The RAM based memory system is provided with the waveform information by dividing each desired waveform into segments depending on the clock value and storing each segment in a respective memory site. An analog to digital converter may be evaluated by directing the desired waveform to the analog to digital converter. The generated waveform is tuned in the filter to a center frequency if it is a sinewave or a tuned squarewave.

Abstract: For sweeping a frequency synthesizer, which is digitally tunable in frequency in small steps to have a predetermined frequency progression over time, a clock signal of an accumulator generating digital adjustment values for the frequencies is controlled via a control circuit that is programmed corresponding to a desired frequency progression.

Abstract: A clock generator for a multi-system comprising a TCXO (temperature compensated crystal oscillator) 1 controlled by an AFC (automatic frequency control) circuit 12 and a sub-system operative with a system clock supplied from the main system and including a PLL (phase locked loop) circuit having a phase comparator 5 and a VCO (voltage controlled oscillator) 3 is disclosed. The frequency division ratios of frequency dividers 2, 4 in the PLL circuit is compensated on the basis of the output of the AFC circuit 12 to absorb phase changes due to the AFC circuit 12.

Abstract: An apparatus for generating a supply signal at a predetermined frequency comprises a digital synthesizer connected with an oscillator and a processor; and a temperature sensor connected with the processor. The oscillator provides a periodic excitation signal to the synthesizer, which responds by recurrently accumulating bits in quantum bit step amounts to a maximum bit capacity and returning to a starting bit count in a bit accumulating period. The synthesizer generates the supply signal based upon the bit accumulating period. The processor provides a control signal to the synthesizer to control the quantum bit step amount. The temperature sensor and the processor cooperatively employ a predetermined temperature parameter-correction factor relationship to adjust the control signal to set the quantum bit step amount to establish the bit accumulating period appropriately for the predetermined frequency.

Abstract: An improved clock generation circuit is provided that operates with a single input clock frequency, and includes a Phase Locked Loop circuit (PLL) with a digital accumulator in the feedback loop, in which either the Most Significant Bit or the Carry Bit of the binary adder is used as the modulated feedback clock to the phase/frequency detector of the PLL. In one embodiment, a fixed add/phase amount is used to drive one of the inputs of the binary adder to generate a fixed output frequency. If it is desired to modulate the output frequency, then an Add Amount Modulator circuit can be provided that presents a varying numeric value to one of the inputs of the binary adder. The MSB or Carry Bit is communicated to an address look-up table, which then outputs an address to a memory circuit, which in turn presents a different add amount to the binary adder.

Abstract: A frequency correction circuit includes a temperature sensor (100) disposed to measure temperature and produce temperature signals representing sensed temperatures. A data supplier (110) stores information items, receives digital input signals representing and produces a digital output information signal representing an item selected in accordance with the digital input signal. A control circuit (120) receives the temperature signals and receives the digital output information signal. The control circuit (120) produces control signals based on the temperature signals. A clock circuit (150) is disposed to generate a reference frequency signal. A digital synthesizer (130) receives the reference frequency signal and the control signals. The digital synthesizer produces an output frequency signal as directed by the control signals received from the control circuit (120).

Abstract: A signal generator is disclosed. The signal generator includes a variable frequency selector that is configured to provide a variable frequency for generation of a variable frequency signal. The signal generator also includes a periodic signal generator. The periodic signal generator is used to generate a periodic signal. The periodic signal generator has an input receiving the variable frequency signal and an output providing the periodic signal. The periodic signal has a frequency approximately the same as the variable frequency selection. The periodic signal generator stores a table of values associated with a reference periodic signal, each stored value corresponding to a discrete time in the reference periodic signal. The periodic signal generator is configured to interpolate between the discrete points in the table of derivative values.

Abstract: An arbitrary waveform generator (AWG) for producing an analog output current signal includes a random access memory (RAM), a programmable logic device (PLD), a programmable pattern generator, several digital-to analog converters (DACS) and a current multiplexer. The RAM store data sequences representing the analog waveform to be generated. The pattern generator read addresses the RAM causing it to sequentially read out its stored data sequence to the PLD. The PLD routes selected fields of each data sequence word to one or more of the DACs in response to timing signals provided by the pattern generator. Each DAC produces an output current of magnitude determined by its input waveform and range data. The pattern generator also signals the analog multiplexer to sum currents produced by one or more selected DACs to produce the AWG output waveform.

Abstract: An arbitrary waveform generator (AWG) generates an output signal that linearly ramps between discrete levels to approximate a smoothly varying waveform. The AWG includes a digital-to-analog converter (DAC) formed by a set of N ramp generators, with each ramp generator producing output currents that ramp at adjustable rates between discrete levels in response to a change in state of an input waveform data bit. The output currents of all N ramp generators of the DAC, which have separately weighted magnitude levels, are summed and converted to a proportional voltage to produce the AWG's output signal.

Abstract: A direct digital frequency synthesizer and a hybrid frequency synthesizer combining the direct digital frequency synthesizer and a phase locked loop is provided. The direct digital frequency synthesizer includes a phase accumulator that is configured to generate a discrete phase signal. Spurious phase modulation in the discrete phase signal is reduced by a noise shaper, and the output of the noise shaper is then used to address a phase-to-amplitude translator. The phase-to-amplitude translator generates a discrete waveform which is converted to a continuous waveform by a digital to analog converter. The hybrid frequency synthesizer uses a mixer to combine a reference frequency generated by a reference source and a DDFS output signal generated by a direct digital frequency synthesizer. The output from the mixer is then coupled to the input of a phase locked loop which multiplies the mixer output to generate the frequency synthesizer output.

Abstract: A frequency oscillator tuning process at the manufacturing stage is replaced with an adjustment of a resonant circuit in the frequency oscillator during an operation of the oscillator. The adjustment utilizes a crystal oscillator, a frequency oscillator such as a voltage-controlled oscillator (VCO), and a trimmer in a phase-locked loop configuration to determine a correction voltage required for an untrimmed VCO to operate at a nominally specified frequency by adjusting an input tuning voltage for a resonant circuit.